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1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # I2C protocol decoder | |
23 | # | |
24 | ||
25 | # | |
26 | # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master | |
27 | # bus using two signals (SCL = serial clock line, SDA = serial data line). | |
28 | # | |
29 | # There can be many devices on the same bus. Each device can potentially be | |
30 | # master or slave (and that can change during runtime). Both slave and master | |
31 | # can potentially play the transmitter or receiver role (this can also | |
32 | # change at runtime). | |
33 | # | |
34 | # Possible maximum data rates: | |
35 | # - Standard mode: 100 kbit/s | |
36 | # - Fast mode: 400 kbit/s | |
37 | # - Fast-mode Plus: 1 Mbit/s | |
38 | # - High-speed mode: 3.4 Mbit/s | |
39 | # | |
40 | # START condition (S): SDA = falling, SCL = high | |
41 | # Repeated START condition (Sr): same as S | |
42 | # STOP condition (P): SDA = rising, SCL = high | |
43 | # | |
44 | # All data bytes on SDA are extactly 8 bits long (transmitted MSB-first). | |
45 | # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low, | |
46 | # that indicates an ACK, if it's high that indicates a NACK. | |
47 | # | |
48 | # After the first START condition, a master sends the device address of the | |
49 | # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first). | |
50 | # After those 7 bits a data direction bit is sent. If the bit is low that | |
51 | # indicates a WRITE operation, if it's high that indicates a READ operation. | |
52 | # | |
53 | # Later an optional 10bit slave addressing scheme was added. | |
54 | # | |
55 | # Documentation: | |
56 | # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec) | |
57 | # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec) | |
58 | # http://en.wikipedia.org/wiki/I2C | |
59 | # | |
60 | ||
61 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. | |
62 | # TODO: Handle clock stretching. | |
63 | # TODO: Handle combined messages / repeated START. | |
64 | # TODO: Implement support for 7bit and 10bit slave addresses. | |
65 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). | |
66 | # TODO: Implement support for detecting various bus errors. | |
67 | ||
68 | # TODO: Return two buffers, one with structured data for the GUI to parse | |
69 | # and display, and one with human-readable ASCII output. | |
70 | ||
71 | def sigrokdecode_i2c(inbuf): | |
72 | """I2C protocol decoder""" | |
73 | ||
74 | # FIXME: This should be passed in as metadata, not hardcoded here. | |
75 | signals = (2, 5) | |
76 | channels = 8 | |
77 | ||
78 | o = wr = ack = d = '' | |
79 | bitcount = data = 0 | |
80 | state = 'IDLE' | |
81 | ||
82 | # Get the bit number (and thus probe index) of the SCL/SDA signals. | |
83 | scl_bit, sda_bit = signals | |
84 | ||
85 | # Get SCL/SDA bit values (0/1 for low/high) of the first sample. | |
86 | s = ord(inbuf[0]) | |
87 | oldscl = (s & (1 << scl_bit)) != 0 | |
88 | oldsda = (s & (1 << sda_bit)) != 0 | |
89 | ||
90 | # Loop over all samples. | |
91 | # TODO: Handle LAs with more/less than 8 channels. | |
92 | for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte... | |
93 | ||
94 | s = ord(s) # FIXME | |
95 | ||
96 | # Get SCL/SDA bit values (0/1 for low/high). | |
97 | scl = (s & (1 << scl_bit)) != 0 | |
98 | sda = (s & (1 << sda_bit)) != 0 | |
99 | ||
100 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? | |
101 | ||
102 | # START condition (S): SDA = falling, SCL = high | |
103 | if (oldsda == 1 and sda == 0) and scl == 1: | |
104 | o += "%d\t\tSTART\n" % samplenum | |
105 | state = 'ADDRESS' | |
106 | bitcount = data = 0 | |
107 | ||
108 | # Data latching by transmitter: SCL = low | |
109 | elif (scl == 0): | |
110 | pass # TODO | |
111 | ||
112 | # Data sampling of receiver: SCL = rising | |
113 | elif (oldscl == 0 and scl == 1): | |
114 | bitcount += 1 | |
115 | ||
116 | # o += "%d\t\tRECEIVED BIT %d: %d\n" % \ | |
117 | # (samplenum, 8 - bitcount, sda) | |
118 | ||
119 | # Address and data are transmitted MSB-first. | |
120 | data <<= 1 | |
121 | data |= sda | |
122 | ||
123 | if bitcount != 9: | |
124 | continue | |
125 | ||
126 | # We received 8 address/data bits and the ACK/NACK bit. | |
127 | data >>= 1 # Shift out unwanted ACK/NACK bit here. | |
128 | o += "%d\t\t%s: " % (samplenum, state) | |
129 | ack = (sda == 1) and 'NACK' or 'ACK' | |
130 | d = (state == 'ADDRESS') and (data & 0xfe) or data | |
131 | wr = '' | |
132 | if state == 'ADDRESS': | |
133 | wr = (data & 1) and ' (W)' or ' (R)' | |
134 | state = 'DATA' | |
135 | o += "0x%02x%s (%s)\n" % (d, wr, ack) | |
136 | bitcount = data = 0 | |
137 | ||
138 | # STOP condition (P): SDA = rising, SCL = high | |
139 | elif (oldsda == 0 and sda == 1) and scl == 1: | |
140 | o += "%d\t\tSTOP\n" % samplenum | |
141 | state = 'IDLE' | |
142 | ||
143 | # Save current SDA/SCL values for the next round. | |
144 | oldscl = scl | |
145 | oldsda = sda | |
146 | ||
147 | return o | |
148 | ||
149 | # This is just a draft. | |
150 | def sigrokdecode_register_i2c(): | |
151 | metadata = { | |
152 | 'id': 'i2c', | |
153 | 'name': 'I2C', | |
154 | 'description': 'Inter-Integrated Circuit (I2C) bus', | |
155 | 'function': 'sigrokdecode_i2c', | |
156 | 'inputformats': ['raw'], | |
157 | 'signalnames': { | |
158 | 'SCL': 'Serial clock line', | |
159 | 'SDA': 'Serial data line', | |
160 | }, | |
161 | 'ouputformats': ['i2c', 'ascii'], | |
162 | } | |
163 | return metadata | |
164 |