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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Bert Vermeulen <bert@biot.com> | |
5 | * With protocol information from the hantekdso project, | |
6 | * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_PROTOCOL_H | |
23 | #define LIBSIGROK_HARDWARE_HANTEK_DSO_PROTOCOL_H | |
24 | ||
25 | #define LOG_PREFIX "hantek-dso" | |
26 | ||
27 | #define USB_INTERFACE 0 | |
28 | #define USB_CONFIGURATION 1 | |
29 | #define DSO_EP_IN 0x86 | |
30 | #define DSO_EP_OUT 0x02 | |
31 | ||
32 | /* FX2 renumeration delay in ms */ | |
33 | #define MAX_RENUM_DELAY_MS 3000 | |
34 | ||
35 | #define MAX_CAPTURE_EMPTY 3 | |
36 | ||
37 | #define DEFAULT_VOLTAGE VDIV_500MV | |
38 | #define DEFAULT_FRAMESIZE FRAMESIZE_SMALL | |
39 | #define DEFAULT_TIMEBASE TIME_100us | |
40 | #define DEFAULT_SAMPLERATE SR_KHZ(10) | |
41 | #define DEFAULT_TRIGGER_SOURCE "CH1" | |
42 | #define DEFAULT_COUPLING COUPLING_DC | |
43 | #define DEFAULT_CAPTURE_RATIO 100 | |
44 | #define DEFAULT_VERT_OFFSET 0.5 | |
45 | #define DEFAULT_VERT_TRIGGERPOS 0.5 | |
46 | ||
47 | #define MAX_VERT_TRIGGER 0xfe | |
48 | ||
49 | /* Hantek DSO-specific protocol values */ | |
50 | #define EEPROM_CHANNEL_OFFSETS 0x08 | |
51 | ||
52 | /* All models have this for their "fast" mode. */ | |
53 | #define FRAMESIZE_SMALL (10 * 1024) | |
54 | ||
55 | #define NUM_CHANNELS 2 | |
56 | ||
57 | enum control_requests { | |
58 | CTRL_READ_EEPROM = 0xa2, | |
59 | CTRL_GETSPEED = 0xb2, | |
60 | CTRL_BEGINCOMMAND = 0xb3, | |
61 | CTRL_SETOFFSET = 0xb4, | |
62 | CTRL_SETRELAYS = 0xb5, | |
63 | }; | |
64 | ||
65 | enum dso_commands { | |
66 | CMD_SET_FILTERS = 0x0, | |
67 | CMD_SET_TRIGGER_SAMPLERATE = 0x1, | |
68 | CMD_FORCE_TRIGGER = 0x2, | |
69 | CMD_CAPTURE_START = 0x3, | |
70 | CMD_ENABLE_TRIGGER = 0x4, | |
71 | CMD_GET_CHANNELDATA = 0x5, | |
72 | CMD_GET_CAPTURESTATE = 0x6, | |
73 | CMD_SET_VOLTAGE = 0x7, | |
74 | /* unused */ | |
75 | CMD_SET_LOGICALDATA = 0x8, | |
76 | CMD_GET_LOGICALDATA = 0x9, | |
77 | CMD__UNUSED1 = 0xa, | |
78 | /* | |
79 | * For the following and other specials please see | |
80 | * http://openhantek.sourceforge.net/doc/namespaceHantek.html#ac1cd181814cf3da74771c29800b39028 | |
81 | */ | |
82 | CMD_2250_SET_CHANNELS = 0xb, | |
83 | CMD_2250_SET_TRIGGERSOURCE = 0xc, | |
84 | CMD_2250_SET_RECORD_LENGTH = 0xd, | |
85 | CMD_2250_SET_SAMPLERATE = 0xe, | |
86 | CMD_2250_SET_TRIGGERPOS_AND_BUFFER = 0xf, | |
87 | }; | |
88 | ||
89 | /* Must match the coupling table. */ | |
90 | enum couplings { | |
91 | COUPLING_AC = 0, | |
92 | COUPLING_DC, | |
93 | /* TODO not used, how to enable? */ | |
94 | COUPLING_GND, | |
95 | }; | |
96 | ||
97 | /* Must match the timebases table. */ | |
98 | enum time_bases { | |
99 | TIME_10us = 0, | |
100 | TIME_20us, | |
101 | TIME_40us, | |
102 | TIME_100us, | |
103 | TIME_200us, | |
104 | TIME_400us, | |
105 | TIME_1ms, | |
106 | TIME_2ms, | |
107 | TIME_4ms, | |
108 | TIME_10ms, | |
109 | TIME_20ms, | |
110 | TIME_40ms, | |
111 | TIME_100ms, | |
112 | TIME_200ms, | |
113 | TIME_400ms, | |
114 | }; | |
115 | ||
116 | /* Must match the vdivs table. */ | |
117 | enum { | |
118 | VDIV_10MV, | |
119 | VDIV_20MV, | |
120 | VDIV_50MV, | |
121 | VDIV_100MV, | |
122 | VDIV_200MV, | |
123 | VDIV_500MV, | |
124 | VDIV_1V, | |
125 | VDIV_2V, | |
126 | VDIV_5V, | |
127 | }; | |
128 | ||
129 | enum trigger_slopes { | |
130 | SLOPE_POSITIVE = 0, | |
131 | SLOPE_NEGATIVE, | |
132 | }; | |
133 | ||
134 | enum trigger_sources { | |
135 | TRIGGER_CH2 = 0, | |
136 | TRIGGER_CH1, | |
137 | TRIGGER_EXT, | |
138 | }; | |
139 | ||
140 | enum capturestates { | |
141 | CAPTURE_EMPTY = 0, | |
142 | CAPTURE_FILLING = 1, | |
143 | CAPTURE_READY_8BIT = 2, | |
144 | CAPTURE_READY_2250 = 3, | |
145 | CAPTURE_READY_9BIT = 7, | |
146 | CAPTURE_TIMEOUT = 127, | |
147 | CAPTURE_UNKNOWN = 255, | |
148 | }; | |
149 | ||
150 | enum triggermodes { | |
151 | TRIGGERMODE_AUTO, | |
152 | TRIGGERMODE_NORMAL, | |
153 | TRIGGERMODE_SINGLE, | |
154 | }; | |
155 | ||
156 | enum states { | |
157 | IDLE, | |
158 | NEW_CAPTURE, | |
159 | CAPTURE, | |
160 | FETCH_DATA, | |
161 | STOPPING, | |
162 | }; | |
163 | ||
164 | struct dso_profile { | |
165 | /* VID/PID after cold boot */ | |
166 | uint16_t orig_vid; | |
167 | uint16_t orig_pid; | |
168 | /* VID/PID after firmware upload */ | |
169 | uint16_t fw_vid; | |
170 | uint16_t fw_pid; | |
171 | const char *vendor; | |
172 | const char *model; | |
173 | const uint64_t *buffersizes; | |
174 | const char *firmware; | |
175 | }; | |
176 | ||
177 | struct dev_context { | |
178 | const struct dso_profile *profile; | |
179 | uint64_t limit_frames; | |
180 | uint64_t num_frames; | |
181 | GSList *enabled_channels; | |
182 | /* We can't keep track of an FX2-based device after upgrading | |
183 | * the firmware (it re-enumerates into a different device address | |
184 | * after the upgrade) this is like a global lock. No device will open | |
185 | * until a proper delay after the last device was upgraded. | |
186 | */ | |
187 | int64_t fw_updated; | |
188 | int epin_maxpacketsize; | |
189 | int capture_empty_count; | |
190 | int dev_state; | |
191 | ||
192 | /* Oscilloscope settings. */ | |
193 | uint64_t samplerate; | |
194 | int timebase; | |
195 | gboolean ch_enabled[2]; | |
196 | int voltage[2]; | |
197 | int coupling[2]; | |
198 | // voltage offset (vertical position) | |
199 | float voffset_ch1; | |
200 | float voffset_ch2; | |
201 | float voffset_trigger; | |
202 | uint16_t channel_levels[2][9][2]; | |
203 | unsigned int framesize; | |
204 | gboolean filter[2]; | |
205 | int triggerslope; | |
206 | char *triggersource; | |
207 | int capture_ratio; | |
208 | int triggermode; | |
209 | ||
210 | /* Frame transfer */ | |
211 | unsigned int samp_received; | |
212 | unsigned int samp_buffered; | |
213 | unsigned int trigger_offset; | |
214 | unsigned char *framebuf; | |
215 | }; | |
216 | ||
217 | SR_PRIV int dso_open(struct sr_dev_inst *sdi); | |
218 | SR_PRIV void dso_close(struct sr_dev_inst *sdi); | |
219 | SR_PRIV int dso_enable_trigger(const struct sr_dev_inst *sdi); | |
220 | SR_PRIV int dso_force_trigger(const struct sr_dev_inst *sdi); | |
221 | SR_PRIV int dso_init(const struct sr_dev_inst *sdi); | |
222 | SR_PRIV int dso_get_capturestate(const struct sr_dev_inst *sdi, | |
223 | uint8_t *capturestate, uint32_t *trigger_offset); | |
224 | SR_PRIV int dso_capture_start(const struct sr_dev_inst *sdi); | |
225 | SR_PRIV int dso_get_channeldata(const struct sr_dev_inst *sdi, | |
226 | libusb_transfer_cb_fn cb); | |
227 | SR_PRIV int dso_set_trigger_samplerate(const struct sr_dev_inst *sdi); | |
228 | SR_PRIV int dso_set_voffsets(const struct sr_dev_inst *sdi); | |
229 | ||
230 | #endif |