]> sigrok.org Git - libsigrok.git/blame_incremental - hardware/zeroplus-logic-cube/analyzer.c
projects / libsigrok.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
zeroplus-logic-cube: Fix samplerate and trigger
[libsigrok.git] / hardware / zeroplus-logic-cube / analyzer.c
... / ...
CommitLineData
1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
5 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
10 * conditions are met:
11 *
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * * Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <assert.h>
33#include "analyzer.h"
34#include "gl_usb.h"
35#include "libsigrok-internal.h"
36
37enum {
38 HARD_DATA_CHECK_SUM = 0x00,
39 PASS_WORD,
40
41 DEV_ID0 = 0x10,
42 DEV_ID1,
43
44 START_STATUS = 0x20,
45 DEV_STATUS = 0x21,
46 FREQUENCY_REG0 = 0x30,
47 FREQUENCY_REG1,
48 FREQUENCY_REG2,
49 FREQUENCY_REG3,
50 FREQUENCY_REG4,
51 MEMORY_LENGTH,
52 CLOCK_SOURCE,
53
54 TRIGGER_STATUS0 = 0x40,
55 TRIGGER_STATUS1,
56 TRIGGER_STATUS2,
57 TRIGGER_STATUS3,
58 TRIGGER_STATUS4,
59 TRIGGER_STATUS5,
60 TRIGGER_STATUS6,
61 TRIGGER_STATUS7,
62 TRIGGER_STATUS8,
63
64 TRIGGER_COUNT0 = 0x50,
65 TRIGGER_COUNT1,
66
67 TRIGGER_LEVEL0 = 0x55,
68 TRIGGER_LEVEL1,
69 TRIGGER_LEVEL2,
70 TRIGGER_LEVEL3,
71
72 RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
73 RAMSIZE_TRIGGERBAR_ADDRESS1,
74 RAMSIZE_TRIGGERBAR_ADDRESS2,
75 TRIGGERBAR_ADDRESS0,
76 TRIGGERBAR_ADDRESS1,
77 TRIGGERBAR_ADDRESS2,
78 DONT_CARE_TRIGGERBAR,
79
80 FILTER_ENABLE = 0x70,
81 FILTER_STATUS,
82
83 ENABLE_DELAY_TIME0 = 0x7a,
84 ENABLE_DELAY_TIME1,
85
86 ENABLE_INSERT_DATA0 = 0x80,
87 ENABLE_INSERT_DATA1,
88 ENABLE_INSERT_DATA2,
89 ENABLE_INSERT_DATA3,
90 COMPRESSION_TYPE0,
91 COMPRESSION_TYPE1,
92
93 TRIGGER_ADDRESS0 = 0x90,
94 TRIGGER_ADDRESS1,
95 TRIGGER_ADDRESS2,
96
97 NOW_ADDRESS0 = 0x96,
98 NOW_ADDRESS1,
99 NOW_ADDRESS2,
100
101 STOP_ADDRESS0 = 0x9b,
102 STOP_ADDRESS1,
103 STOP_ADDRESS2,
104
105 READ_RAM_STATUS = 0xa0,
106};
107
108static int g_trigger_status[9] = { 0 };
109static int g_trigger_count = 1;
110static int g_filter_status[8] = { 0 };
111static int g_filter_enable = 0;
112
113static int g_freq_value = 1;
114static int g_freq_scale = FREQ_SCALE_MHZ;
115static int g_memory_size = MEMORY_SIZE_8K;
116static int g_ramsize_triggerbar_addr = 2 * 1024;
117static int g_triggerbar_addr = 0;
118static int g_compression = COMPRESSION_NONE;
119
120/* Maybe unk specifies an "endpoint" or "register" of sorts. */
121static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
122 unsigned char flags)
123{
124 assert(unk <= 3);
125 return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
126}
127
128#if 0
129static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
130{
131 int reg0 = 0, divisor = 0, reg2 = 0;
132
133 switch (scale) {
134 case FREQ_SCALE_MHZ: /* MHz */
135 if (freq >= 100 && freq <= 200) {
136 reg0 = freq * 0.1;
137 divisor = 1;
138 reg2 = 0;
139 break;
140 }
141 if (freq >= 50 && freq < 100) {
142 reg0 = freq * 0.2;
143 divisor = 2;
144 reg2 = 0;
145 break;
146 }
147 if (freq >= 10 && freq < 50) {
148 if (freq == 25) {
149 reg0 = 25;
150 divisor = 5;
151 reg2 = 1;
152 break;
153 } else {
154 reg0 = freq * 0.5;
155 divisor = 5;
156 reg2 = 1;
157 break;
158 }
159 }
160 if (freq >= 2 && freq < 10) {
161 divisor = 5;
162 reg0 = freq * 2;
163 reg2 = 2;
164 break;
165 }
166 if (freq == 1) {
167 divisor = 5;
168 reg2 = 16;
169 reg0 = 5;
170 break;
171 }
172 divisor = 5;
173 reg0 = 5;
174 reg2 = 64;
175 break;
176 case FREQ_SCALE_HZ: /* Hz */
177 if (freq >= 500 && freq < 1000) {
178 reg0 = freq * 0.01;
179 divisor = 10;
180 reg2 = 64;
181 break;
182 }
183 if (freq >= 300 && freq < 500) {
184 reg0 = freq * 0.005 * 8;
185 divisor = 5;
186 reg2 = 67;
187 break;
188 }
189 if (freq >= 100 && freq < 300) {
190 reg0 = freq * 0.005 * 16;
191 divisor = 5;
192 reg2 = 68;
193 break;
194 }
195 divisor = 5;
196 reg0 = 5;
197 reg2 = 64;
198 break;
199 case FREQ_SCALE_KHZ: /* kHz */
200 if (freq >= 500 && freq < 1000) {
201 reg0 = freq * 0.01;
202 divisor = 5;
203 reg2 = 17;
204 break;
205 }
206 if (freq >= 100 && freq < 500) {
207 reg0 = freq * 0.05;
208 divisor = 5;
209 reg2 = 32;
210 break;
211 }
212 if (freq >= 50 && freq < 100) {
213 reg0 = freq * 0.1;
214 divisor = 5;
215 reg2 = 33;
216 break;
217 }
218 if (freq >= 10 && freq < 50) {
219 if (freq == 25) {
220 reg0 = 25;
221 divisor = 5;
222 reg2 = 49;
223 break;
224 }
225 reg0 = freq * 0.5;
226 divisor = 5;
227 reg2 = 48;
228 break;
229 }
230 if (freq >= 2 && freq < 10) {
231 divisor = 5;
232 reg0 = freq * 2;
233 reg2 = 50;
234 break;
235 }
236 divisor = 5;
237 reg0 = 5;
238 reg2 = 64;
239 break;
240 default:
241 divisor = 5;
242 reg0 = 5;
243 reg2 = 64;
244 break;
245 }
246
247 sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
248 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
249 freq, scale, divisor, reg0, 0x02, reg2);
250
251 if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
252 return -1; /* Divisor maybe? */
253
254 if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
255 return -1; /* 10 / 0.2 */
256
257 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
258 return -1; /* Always 2 */
259
260 if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
261 return -1;
262
263 return 0;
264}
265#endif
266
267/*
268 * It seems that ...
269 * FREQUENCT_REG0 - division factor (?)
270 * FREQUENCT_REG1 - multiplication factor (?)
271 * FREQUENCT_REG4 - clock selection (?)
272 *
273 * clock selection
274 * 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
275 * 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
276 * 2 2.5MHz . . 50 2.5kHz 66 250Hz
277 * . . . . 67 125Hz
278 * . . . . 68 62.5Hz
279 */
280static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
281{
282 struct freq_factor {
283 int freq;
284 int scale;
285 int sel;
286 int div;
287 int mul;
288 };
289
290 static const struct freq_factor f[] = {
291 { 200, FREQ_SCALE_MHZ, 0, 1, 20 },
292 { 150, FREQ_SCALE_MHZ, 0, 1, 15 },
293 { 100, FREQ_SCALE_MHZ, 0, 1, 10 },
294 { 80, FREQ_SCALE_MHZ, 0, 2, 16 },
295 { 50, FREQ_SCALE_MHZ, 0, 2, 10 },
296 { 25, FREQ_SCALE_MHZ, 1, 5, 25 },
297 { 10, FREQ_SCALE_MHZ, 1, 5, 10 },
298 { 1, FREQ_SCALE_MHZ, 16, 5, 5 },
299 { 800, FREQ_SCALE_KHZ, 17, 5, 8 },
300 { 400, FREQ_SCALE_KHZ, 32, 5, 20 },
301 { 200, FREQ_SCALE_KHZ, 32, 5, 10 },
302 { 100, FREQ_SCALE_KHZ, 32, 5, 5 },
303 { 50, FREQ_SCALE_KHZ, 33, 5, 5 },
304 { 25, FREQ_SCALE_KHZ, 49, 5, 25 },
305 { 5, FREQ_SCALE_KHZ, 50, 5, 10 },
306 { 1, FREQ_SCALE_KHZ, 64, 5, 5 },
307 { 500, FREQ_SCALE_HZ, 64, 10, 5 },
308 { 100, FREQ_SCALE_HZ, 68, 5, 8 },
309 { 0, 0, 0, 0, 0 }
310 };
311
312 int i;
313
314 for (i = 0; f[i].freq; i++) {
315 if (scale == f[i].scale && freq == f[i].freq)
316 break;
317 }
318 if (!f[i].freq)
319 return -1;
320
321 sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
322 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
323 freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
324
325 if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
326 return -1;
327
328 if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
329 return -1;
330
331 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
332 return -1;
333
334 if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
335 return -1;
336
337 return 0;
338}
339
340static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
341 unsigned int address)
342{
343 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
344 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
345 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
346}
347
348static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
349 unsigned int address)
350{
351 gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
352 gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
353 gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
354}
355
356static void __analyzer_set_compression(libusb_device_handle *devh,
357 unsigned int type)
358{
359 gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
360 gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
361}
362
363static void __analyzer_set_trigger_count(libusb_device_handle *devh,
364 unsigned int count)
365{
366 gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
367 gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
368}
369
370static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
371{
372 gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
373 gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
374 gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
375 gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
376}
377
378static void analyzer_set_filter(libusb_device_handle *devh)
379{
380 int i;
381 gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
382 for (i = 0; i < 8; i++)
383 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
384}
385
386SR_PRIV void analyzer_reset(libusb_device_handle *devh)
387{
388 analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
389 analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
390}
391
392SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
393{
394 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
395 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
396 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
397}
398
399SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
400{
401 int status;
402 while (1) {
403 status = gl_reg_read(devh, DEV_STATUS);
404 if ((status & set) && ((status & unset) == 0))
405 return;
406 }
407}
408
409SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
410{
411 int i;
412
413 analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
414
415 for (i = 0; i < 8; i++)
416 (void)gl_reg_read(devh, READ_RAM_STATUS);
417}
418
419SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
420 unsigned int size)
421{
422 return gl_read_bulk(devh, buffer, size);
423}
424
425SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
426{
427 analyzer_write_status(devh, 3, STATUS_FLAG_20);
428 analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
429}
430
431SR_PRIV void analyzer_start(libusb_device_handle *devh)
432{
433 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
434 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
435 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
436 analyzer_write_status(devh, 1, STATUS_FLAG_GO);
437}
438
439SR_PRIV void analyzer_configure(libusb_device_handle *devh)
440{
441 int i;
442
443 /* Write_Start_Status */
444 analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
445 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
446
447 /* Start_Config_Outside_Device ? */
448 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
449 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
450
451 /* SetData_To_Frequence_Reg */
452 __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
453
454 /* SetMemory_Length */
455 gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
456
457 /* Sele_Inside_Outside_Clock */
458 gl_reg_write(devh, CLOCK_SOURCE, 0x03);
459
460 /* Set_Trigger_Status */
461 for (i = 0; i < 9; i++)
462 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
463
464 __analyzer_set_trigger_count(devh, g_trigger_count);
465
466 /* Set_Trigger_Level */
467 gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
468 gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
469 gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
470 gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
471
472 /* Size of actual memory >> 2 */
473 __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
474 __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
475
476 /* Set_Dont_Care_TriggerBar */
477 if (g_triggerbar_addr)
478 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x00);
479 else
480 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
481
482 /* Enable_Status */
483 analyzer_set_filter(devh);
484
485 /* Set_Enable_Delay_Time */
486 gl_reg_write(devh, 0x7a, 0x00);
487 gl_reg_write(devh, 0x7b, 0x00);
488 analyzer_write_enable_insert_data(devh);
489 __analyzer_set_compression(devh, g_compression);
490}
491
492SR_PRIV void analyzer_add_trigger(int channel, int type)
493{
494 switch (type) {
495 case TRIGGER_HIGH:
496 g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
497 break;
498 case TRIGGER_LOW:
499 g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
500 break;
501#if 0
502 case TRIGGER_POSEDGE:
503 g_trigger_status[8] = 0x40 | channel;
504 break;
505 case TRIGGER_NEGEDGE:
506 g_trigger_status[8] = 0x80 | channel;
507 break;
508 case TRIGGER_ANYEDGE:
509 g_trigger_status[8] = 0xc0 | channel;
510 break;
511#endif
512 default:
513 break;
514 }
515}
516
517SR_PRIV void analyzer_add_filter(int channel, int type)
518{
519 int i;
520
521 if (type != FILTER_HIGH && type != FILTER_LOW)
522 return;
523 if ((channel & 0xf) >= 8)
524 return;
525
526 if (channel & CHANNEL_A)
527 i = 0;
528 else if (channel & CHANNEL_B)
529 i = 2;
530 else if (channel & CHANNEL_C)
531 i = 4;
532 else if (channel & CHANNEL_D)
533 i = 6;
534 else
535 return;
536
537 if ((channel & 0xf) >= 4) {
538 i++;
539 channel -= 4;
540 }
541
542 g_filter_status[i] |=
543 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
544
545 g_filter_enable = 1;
546}
547
548SR_PRIV void analyzer_set_trigger_count(int count)
549{
550 g_trigger_count = count;
551}
552
553SR_PRIV void analyzer_set_freq(int freq, int scale)
554{
555 g_freq_value = freq;
556 g_freq_scale = scale;
557}
558
559SR_PRIV void analyzer_set_memory_size(unsigned int size)
560{
561 g_memory_size = size;
562}
563
564SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
565{
566 g_ramsize_triggerbar_addr = address;
567}
568
569SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
570{
571 g_triggerbar_addr = address;
572}
573
574SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
575{
576 return gl_reg_read(devh, DEV_STATUS);
577}
578
579SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
580{
581 return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
582}
583
584SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
585{
586 return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
587 STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
588}
589
590SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
591{
592 return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
593 NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
594}
595
596SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
597{
598 return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
599 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
600}
601
602SR_PRIV void analyzer_set_compression(unsigned int type)
603{
604 g_compression = type;
605}
606
607SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
608{
609 analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
610}
611
612SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
613{
614 analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
615}
616
617SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
618 void *output, unsigned int output_len)
619{
620 unsigned char *in = input;
621 unsigned char *out = output;
622 unsigned int A, B, C, count;
623 unsigned int written = 0;
624
625 while (input_len > 0) {
626 A = *in++;
627 B = *in++;
628 C = *in++;
629 count = (*in++) + 1;
630
631 if (count > output_len)
632 count = output_len;
633 output_len -= count;
634 written += count;
635
636 while (count--) {
637 *out++ = A;
638 *out++ = B;
639 *out++ = C;
640 *out++ = 0; /* Channel D */
641 }
642
643 input_len -= 4;
644 if (output_len == 0)
645 break;
646 }
647
648 return written;
649}
Hardware access and backend lib