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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
27#ifdef _WIN32
28#include <windows.h>
29#else
30#include <termios.h>
31#endif
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
35#ifdef _WIN32
36/* TODO */
37#else
38#include <arpa/inet.h>
39#endif
40#include <glib.h>
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
43#include "ols.h"
44
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
49static const int hwcaps[] = {
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
54 SR_HWCAP_RLE,
55 0,
56};
57
58/* Probes are numbered 0-31 (on the PCB silkscreen). */
59static const char *probe_names[NUM_PROBES + 1] = {
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
95/* default supported samplerates, can be overridden by device metadata */
96static const struct sr_samplerates samplerates = {
97 SR_HZ(10),
98 SR_MHZ(200),
99 SR_HZ(1),
100 NULL,
101};
102
103SR_PRIV struct sr_dev_driver ols_driver_info;
104static struct sr_dev_driver *odi = &ols_driver_info;
105
106static int send_shortcommand(int fd, uint8_t command)
107{
108 char buf[1];
109
110 sr_dbg("ols: sending cmd 0x%.2x", command);
111 buf[0] = command;
112 if (serial_write(fd, buf, 1) != 1)
113 return SR_ERR;
114
115 return SR_OK;
116}
117
118static int send_longcommand(int fd, uint8_t command, uint32_t data)
119{
120 char buf[5];
121
122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
123 buf[0] = command;
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
128 if (serial_write(fd, buf, 5) != 5)
129 return SR_ERR;
130
131 return SR_OK;
132}
133
134static int configure_probes(struct context *ctx, const GSList *probes)
135{
136 const struct sr_probe *probe;
137 const GSList *l;
138 int probe_bit, stage, i;
139 char *tc;
140
141 ctx->probe_mask = 0;
142 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
143 ctx->trigger_mask[i] = 0;
144 ctx->trigger_value[i] = 0;
145 }
146
147 ctx->num_stages = 0;
148 for (l = probes; l; l = l->next) {
149 probe = (const struct sr_probe *)l->data;
150 if (!probe->enabled)
151 continue;
152
153 /*
154 * Set up the probe mask for later configuration into the
155 * flag register.
156 */
157 probe_bit = 1 << (probe->index - 1);
158 ctx->probe_mask |= probe_bit;
159
160 if (!probe->trigger)
161 continue;
162
163 /* Configure trigger mask and value. */
164 stage = 0;
165 for (tc = probe->trigger; tc && *tc; tc++) {
166 ctx->trigger_mask[stage] |= probe_bit;
167 if (*tc == '1')
168 ctx->trigger_value[stage] |= probe_bit;
169 stage++;
170 if (stage > 3)
171 /*
172 * TODO: Only supporting parallel mode, with
173 * up to 4 stages.
174 */
175 return SR_ERR;
176 }
177 if (stage > ctx->num_stages)
178 ctx->num_stages = stage;
179 }
180
181 return SR_OK;
182}
183
184static uint32_t reverse16(uint32_t in)
185{
186 uint32_t out;
187
188 out = (in & 0xff) << 8;
189 out |= (in & 0xff00) >> 8;
190 out |= (in & 0xff0000) << 8;
191 out |= (in & 0xff000000) >> 8;
192
193 return out;
194}
195
196static uint32_t reverse32(uint32_t in)
197{
198 uint32_t out;
199
200 out = (in & 0xff) << 24;
201 out |= (in & 0xff00) << 8;
202 out |= (in & 0xff0000) >> 8;
203 out |= (in & 0xff000000) >> 24;
204
205 return out;
206}
207
208static struct context *ols_dev_new(void)
209{
210 struct context *ctx;
211
212 /* TODO: Is 'ctx' ever g_free()'d? */
213 if (!(ctx = g_try_malloc0(sizeof(struct context)))) {
214 sr_err("ols: %s: ctx malloc failed", __func__);
215 return NULL;
216 }
217
218 ctx->trigger_at = -1;
219 ctx->probe_mask = 0xffffffff;
220 ctx->cur_samplerate = SR_KHZ(200);
221 ctx->serial = NULL;
222
223 return ctx;
224}
225
226static struct sr_dev_inst *get_metadata(int fd)
227{
228 struct sr_dev_inst *sdi;
229 struct context *ctx;
230 struct sr_probe *probe;
231 uint32_t tmp_int, ui;
232 uint8_t key, type, token;
233 GString *tmp_str, *devname, *version;
234 guchar tmp_c;
235
236 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
237 sdi->driver = odi;
238 ctx = ols_dev_new();
239 sdi->priv = ctx;
240
241 devname = g_string_new("");
242 version = g_string_new("");
243
244 key = 0xff;
245 while (key) {
246 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
247 break;
248 type = key >> 5;
249 token = key & 0x1f;
250 switch (type) {
251 case 0:
252 /* NULL-terminated string */
253 tmp_str = g_string_new("");
254 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
255 g_string_append_c(tmp_str, tmp_c);
256 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
257 key, tmp_str->str);
258 switch (token) {
259 case 0x01:
260 /* Device name */
261 devname = g_string_append(devname, tmp_str->str);
262 break;
263 case 0x02:
264 /* FPGA firmware version */
265 if (version->len)
266 g_string_append(version, ", ");
267 g_string_append(version, "FPGA version ");
268 g_string_append(version, tmp_str->str);
269 break;
270 case 0x03:
271 /* Ancillary version */
272 if (version->len)
273 g_string_append(version, ", ");
274 g_string_append(version, "Ancillary version ");
275 g_string_append(version, tmp_str->str);
276 break;
277 default:
278 sr_info("ols: unknown token 0x%.2x: '%s'",
279 token, tmp_str->str);
280 break;
281 }
282 g_string_free(tmp_str, TRUE);
283 break;
284 case 1:
285 /* 32-bit unsigned integer */
286 if (serial_read(fd, &tmp_int, 4) != 4)
287 break;
288 tmp_int = reverse32(tmp_int);
289 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
290 key, tmp_int);
291 switch (token) {
292 case 0x00:
293 /* Number of usable probes */
294 for (ui = 0; ui < tmp_int; ui++) {
295 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
296 probe_names[ui])))
297 return 0;
298 sdi->probes = g_slist_append(sdi->probes, probe);
299 }
300 break;
301 case 0x01:
302 /* Amount of sample memory available (bytes) */
303 ctx->max_samples = tmp_int;
304 break;
305 case 0x02:
306 /* Amount of dynamic memory available (bytes) */
307 /* what is this for? */
308 break;
309 case 0x03:
310 /* Maximum sample rate (hz) */
311 ctx->max_samplerate = tmp_int;
312 break;
313 case 0x04:
314 /* protocol version */
315 ctx->protocol_version = tmp_int;
316 break;
317 default:
318 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
319 token, tmp_int);
320 break;
321 }
322 break;
323 case 2:
324 /* 8-bit unsigned integer */
325 if (serial_read(fd, &tmp_c, 1) != 1)
326 break;
327 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
328 key, tmp_c);
329 switch (token) {
330 case 0x00:
331 /* Number of usable probes */
332 for (ui = 0; ui < tmp_c; ui++) {
333 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
334 probe_names[ui])))
335 return 0;
336 sdi->probes = g_slist_append(sdi->probes, probe);
337 }
338 break;
339 case 0x01:
340 /* protocol version */
341 ctx->protocol_version = tmp_c;
342 break;
343 default:
344 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
345 token, tmp_c);
346 break;
347 }
348 break;
349 default:
350 /* unknown type */
351 break;
352 }
353 }
354
355 sdi->model = devname->str;
356 sdi->version = version->str;
357 g_string_free(devname, FALSE);
358 g_string_free(version, FALSE);
359
360 return sdi;
361}
362
363static int hw_init(void)
364{
365
366 /* Nothing to do. */
367
368 return SR_OK;
369}
370
371static GSList *hw_scan(GSList *options)
372{
373 struct sr_dev_inst *sdi;
374 struct context *ctx;
375 struct sr_probe *probe;
376 GSList *devices, *ports, *l;
377 GPollFD *fds, probefd;
378 int devcnt, final_devcnt, num_ports, fd, ret, i, j;
379 char buf[8], **dev_names, **serial_params;
380
381 (void)options;
382 final_devcnt = 0;
383 devices = NULL;
384
385 /* Scan all serial ports. */
386 ports = list_serial_ports();
387 num_ports = g_slist_length(ports);
388
389 if (!(fds = g_try_malloc0(num_ports * sizeof(GPollFD)))) {
390 sr_err("ols: %s: fds malloc failed", __func__);
391 goto hw_init_free_ports; /* TODO: SR_ERR_MALLOC. */
392 }
393
394 if (!(dev_names = g_try_malloc(num_ports * sizeof(char *)))) {
395 sr_err("ols: %s: dev_names malloc failed", __func__);
396 goto hw_init_free_fds; /* TODO: SR_ERR_MALLOC. */
397 }
398
399 if (!(serial_params = g_try_malloc(num_ports * sizeof(char *)))) {
400 sr_err("ols: %s: serial_params malloc failed", __func__);
401 goto hw_init_free_dev_names; /* TODO: SR_ERR_MALLOC. */
402 }
403
404 devcnt = 0;
405 for (l = ports; l; l = l->next) {
406 /* The discovery procedure is like this: first send the Reset
407 * command (0x00) 5 times, since the device could be anywhere
408 * in a 5-byte command. Then send the ID command (0x02).
409 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
410 * have a match.
411 *
412 * Since it may take the device a while to respond at 115Kb/s,
413 * we do all the sending first, then wait for all of them to
414 * respond with g_poll().
415 */
416 sr_info("ols: probing %s...", (char *)l->data);
417 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
418 if (fd != -1) {
419 serial_params[devcnt] = serial_backup_params(fd);
420 serial_set_params(fd, 115200, 8, SERIAL_PARITY_NONE, 1, 2);
421 ret = SR_OK;
422 for (i = 0; i < 5; i++) {
423 if ((ret = send_shortcommand(fd,
424 CMD_RESET)) != SR_OK) {
425 /* Serial port is not writable. */
426 break;
427 }
428 }
429 if (ret != SR_OK) {
430 serial_restore_params(fd,
431 serial_params[devcnt]);
432 serial_close(fd);
433 continue;
434 }
435 send_shortcommand(fd, CMD_ID);
436 fds[devcnt].fd = fd;
437 fds[devcnt].events = G_IO_IN;
438 dev_names[devcnt] = g_strdup(l->data);
439 devcnt++;
440 }
441 g_free(l->data);
442 }
443
444 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
445 usleep(10000);
446
447 g_poll(fds, devcnt, 1);
448
449 for (i = 0; i < devcnt; i++) {
450 if (fds[i].revents != G_IO_IN)
451 continue;
452 if (serial_read(fds[i].fd, buf, 4) != 4)
453 continue;
454 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
455 continue;
456
457 /* definitely using the OLS protocol, check if it supports
458 * the metadata command
459 */
460 send_shortcommand(fds[i].fd, CMD_METADATA);
461 probefd.fd = fds[i].fd;
462 probefd.events = G_IO_IN;
463 if (g_poll(&probefd, 1, 10) > 0) {
464 /* got metadata */
465 sdi = get_metadata(fds[i].fd);
466 sdi->index = final_devcnt;
467 ctx = sdi->priv;
468 } else {
469 /* not an OLS -- some other board that uses the sump protocol */
470 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
471 "Sump", "Logic Analyzer", "v1.0");
472 sdi->driver = odi;
473 ctx = ols_dev_new();
474 for (j = 0; j < 32; j++) {
475 if (!(probe = sr_probe_new(j, SR_PROBE_LOGIC, TRUE,
476 probe_names[j])))
477 return 0;
478 sdi->probes = g_slist_append(sdi->probes, probe);
479 }
480 sdi->priv = ctx;
481 }
482 ctx->serial = sr_serial_dev_inst_new(dev_names[i], -1);
483 odi->instances = g_slist_append(odi->instances, sdi);
484 devices = g_slist_append(devices, sdi);
485
486 final_devcnt++;
487 serial_close(fds[i].fd);
488 fds[i].fd = 0;
489 }
490
491 /* clean up after all the probing */
492 for (i = 0; i < devcnt; i++) {
493 if (fds[i].fd != 0) {
494 serial_restore_params(fds[i].fd, serial_params[i]);
495 serial_close(fds[i].fd);
496 }
497 g_free(serial_params[i]);
498 g_free(dev_names[i]);
499 }
500
501 g_free(serial_params);
502hw_init_free_dev_names:
503 g_free(dev_names);
504hw_init_free_fds:
505 g_free(fds);
506hw_init_free_ports:
507 g_slist_free(ports);
508
509 return devices;
510}
511
512static int hw_dev_open(int dev_index)
513{
514 struct sr_dev_inst *sdi;
515 struct context *ctx;
516
517 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index)))
518 return SR_ERR;
519
520 ctx = sdi->priv;
521
522 ctx->serial->fd = serial_open(ctx->serial->port, O_RDWR);
523 if (ctx->serial->fd == -1)
524 return SR_ERR;
525
526 sdi->status = SR_ST_ACTIVE;
527
528 return SR_OK;
529}
530
531static int hw_dev_close(int dev_index)
532{
533 struct sr_dev_inst *sdi;
534 struct context *ctx;
535
536 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index))) {
537 sr_err("ols: %s: sdi was NULL", __func__);
538 return SR_ERR_BUG;
539 }
540
541 ctx = sdi->priv;
542
543 /* TODO */
544 if (ctx->serial->fd != -1) {
545 serial_close(ctx->serial->fd);
546 ctx->serial->fd = -1;
547 sdi->status = SR_ST_INACTIVE;
548 }
549
550 return SR_OK;
551}
552
553static int hw_cleanup(void)
554{
555 GSList *l;
556 struct sr_dev_inst *sdi;
557 struct context *ctx;
558 int ret = SR_OK;
559
560 /* Properly close and free all devices. */
561 for (l = odi->instances; l; l = l->next) {
562 if (!(sdi = l->data)) {
563 /* Log error, but continue cleaning up the rest. */
564 sr_err("ols: %s: sdi was NULL, continuing", __func__);
565 ret = SR_ERR_BUG;
566 continue;
567 }
568 if (!(ctx = sdi->priv)) {
569 /* Log error, but continue cleaning up the rest. */
570 sr_err("ols: %s: sdi->priv was NULL, continuing",
571 __func__);
572 ret = SR_ERR_BUG;
573 continue;
574 }
575 /* TODO: Check for serial != NULL. */
576 if (ctx->serial->fd != -1)
577 serial_close(ctx->serial->fd);
578 sr_serial_dev_inst_free(ctx->serial);
579 sr_dev_inst_free(sdi);
580 }
581 g_slist_free(odi->instances);
582 odi->instances = NULL;
583
584 return ret;
585}
586
587static int hw_info_get(int info_id, const void **data,
588 const struct sr_dev_inst *sdi)
589{
590 struct context *ctx;
591
592 switch (info_id) {
593 case SR_DI_INST:
594 *data = sdi;
595 break;
596 case SR_DI_NUM_PROBES:
597 *data = GINT_TO_POINTER(1);
598 break;
599 case SR_DI_PROBE_NAMES:
600 *data = probe_names;
601 break;
602 case SR_DI_SAMPLERATES:
603 *data = &samplerates;
604 break;
605 case SR_DI_TRIGGER_TYPES:
606 *data = (char *)TRIGGER_TYPES;
607 break;
608 case SR_DI_CUR_SAMPLERATE:
609 if (sdi) {
610 ctx = sdi->priv;
611 *data = &ctx->cur_samplerate;
612 } else
613 return SR_ERR;
614 break;
615 default:
616 return SR_ERR_ARG;
617 }
618
619 return SR_OK;
620}
621
622static int hw_dev_status_get(int dev_index)
623{
624 struct sr_dev_inst *sdi;
625
626 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index)))
627 return SR_ST_NOT_FOUND;
628
629 return sdi->status;
630}
631
632static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
633{
634 struct context *ctx;
635
636 ctx = sdi->priv;
637 if (ctx->max_samplerate) {
638 if (samplerate > ctx->max_samplerate)
639 return SR_ERR_SAMPLERATE;
640 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
641 return SR_ERR_SAMPLERATE;
642
643 if (samplerate > CLOCK_RATE) {
644 ctx->flag_reg |= FLAG_DEMUX;
645 ctx->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
646 } else {
647 ctx->flag_reg &= ~FLAG_DEMUX;
648 ctx->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
649 }
650
651 /* Calculate actual samplerate used and complain if it is different
652 * from the requested.
653 */
654 ctx->cur_samplerate = CLOCK_RATE / (ctx->cur_samplerate_divider + 1);
655 if (ctx->flag_reg & FLAG_DEMUX)
656 ctx->cur_samplerate *= 2;
657 if (ctx->cur_samplerate != samplerate)
658 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
659 PRIu64, samplerate, ctx->cur_samplerate);
660
661 return SR_OK;
662}
663
664static int hw_dev_config_set(int dev_index, int hwcap, const void *value)
665{
666 struct sr_dev_inst *sdi;
667 struct context *ctx;
668 int ret;
669 const uint64_t *tmp_u64;
670
671 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index)))
672 return SR_ERR;
673 ctx = sdi->priv;
674
675 if (sdi->status != SR_ST_ACTIVE)
676 return SR_ERR;
677
678 switch (hwcap) {
679 case SR_HWCAP_SAMPLERATE:
680 ret = set_samplerate(sdi, *(const uint64_t *)value);
681 break;
682 case SR_HWCAP_PROBECONFIG:
683 ret = configure_probes(ctx, (const GSList *)value);
684 break;
685 case SR_HWCAP_LIMIT_SAMPLES:
686 tmp_u64 = value;
687 if (*tmp_u64 < MIN_NUM_SAMPLES)
688 return SR_ERR;
689 if (*tmp_u64 > ctx->max_samples)
690 sr_err("ols: sample limit exceeds hw max");
691 ctx->limit_samples = *tmp_u64;
692 sr_info("ols: sample limit %" PRIu64, ctx->limit_samples);
693 ret = SR_OK;
694 break;
695 case SR_HWCAP_CAPTURE_RATIO:
696 ctx->capture_ratio = *(const uint64_t *)value;
697 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) {
698 ctx->capture_ratio = 0;
699 ret = SR_ERR;
700 } else
701 ret = SR_OK;
702 break;
703 case SR_HWCAP_RLE:
704 if (GPOINTER_TO_INT(value)) {
705 sr_info("ols: enabling RLE");
706 ctx->flag_reg |= FLAG_RLE;
707 }
708 ret = SR_OK;
709 break;
710 default:
711 ret = SR_ERR;
712 }
713
714 return ret;
715}
716
717static int receive_data(int fd, int revents, void *cb_data)
718{
719 struct sr_datafeed_packet packet;
720 struct sr_datafeed_logic logic;
721 struct sr_dev_inst *sdi;
722 struct context *ctx;
723 GSList *l;
724 int num_channels, offset, i, j;
725 unsigned char byte;
726
727 /* Find this device's ctx struct by its fd. */
728 ctx = NULL;
729 for (l = odi->instances; l; l = l->next) {
730 sdi = l->data;
731 ctx = sdi->priv;
732 if (ctx->serial->fd == fd) {
733 break;
734 }
735 ctx = NULL;
736 }
737 if (!ctx)
738 /* Shouldn't happen. */
739 return TRUE;
740
741 if (ctx->num_transfers++ == 0) {
742 /*
743 * First time round, means the device started sending data,
744 * and will not stop until done. If it stops sending for
745 * longer than it takes to send a byte, that means it's
746 * finished. We'll double that to 30ms to be sure...
747 */
748 sr_source_remove(fd);
749 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
750 ctx->raw_sample_buf = g_try_malloc(ctx->limit_samples * 4);
751 if (!ctx->raw_sample_buf) {
752 sr_err("ols: %s: ctx->raw_sample_buf malloc failed",
753 __func__);
754 return FALSE;
755 }
756 /* fill with 1010... for debugging */
757 memset(ctx->raw_sample_buf, 0x82, ctx->limit_samples * 4);
758 }
759
760 num_channels = 0;
761 for (i = 0x20; i > 0x02; i /= 2) {
762 if ((ctx->flag_reg & i) == 0)
763 num_channels++;
764 }
765
766 if (revents == G_IO_IN) {
767 if (serial_read(fd, &byte, 1) != 1)
768 return FALSE;
769
770 /* Ignore it if we've read enough. */
771 if (ctx->num_samples >= ctx->limit_samples)
772 return TRUE;
773
774 ctx->sample[ctx->num_bytes++] = byte;
775 sr_dbg("ols: received byte 0x%.2x", byte);
776 if (ctx->num_bytes == num_channels) {
777 /* Got a full sample. */
778 sr_dbg("ols: received sample 0x%.*x",
779 ctx->num_bytes * 2, *(int *)ctx->sample);
780 if (ctx->flag_reg & FLAG_RLE) {
781 /*
782 * In RLE mode -1 should never come in as a
783 * sample, because bit 31 is the "count" flag.
784 */
785 if (ctx->sample[ctx->num_bytes - 1] & 0x80) {
786 ctx->sample[ctx->num_bytes - 1] &= 0x7f;
787 /*
788 * FIXME: This will only work on
789 * little-endian systems.
790 */
791 ctx->rle_count = *(int *)(ctx->sample);
792 sr_dbg("ols: RLE count = %d", ctx->rle_count);
793 ctx->num_bytes = 0;
794 return TRUE;
795 }
796 }
797 ctx->num_samples += ctx->rle_count + 1;
798 if (ctx->num_samples > ctx->limit_samples) {
799 /* Save us from overrunning the buffer. */
800 ctx->rle_count -= ctx->num_samples - ctx->limit_samples;
801 ctx->num_samples = ctx->limit_samples;
802 }
803
804 if (num_channels < 4) {
805 /*
806 * Some channel groups may have been turned
807 * off, to speed up transfer between the
808 * hardware and the PC. Expand that here before
809 * submitting it over the session bus --
810 * whatever is listening on the bus will be
811 * expecting a full 32-bit sample, based on
812 * the number of probes.
813 */
814 j = 0;
815 memset(ctx->tmp_sample, 0, 4);
816 for (i = 0; i < 4; i++) {
817 if (((ctx->flag_reg >> 2) & (1 << i)) == 0) {
818 /*
819 * This channel group was
820 * enabled, copy from received
821 * sample.
822 */
823 ctx->tmp_sample[i] = ctx->sample[j++];
824 }
825 }
826 memcpy(ctx->sample, ctx->tmp_sample, 4);
827 sr_dbg("ols: full sample 0x%.8x", *(int *)ctx->sample);
828 }
829
830 /* the OLS sends its sample buffer backwards.
831 * store it in reverse order here, so we can dump
832 * this on the session bus later.
833 */
834 offset = (ctx->limit_samples - ctx->num_samples) * 4;
835 for (i = 0; i <= ctx->rle_count; i++) {
836 memcpy(ctx->raw_sample_buf + offset + (i * 4),
837 ctx->sample, 4);
838 }
839 memset(ctx->sample, 0, 4);
840 ctx->num_bytes = 0;
841 ctx->rle_count = 0;
842 }
843 } else {
844 /*
845 * This is the main loop telling us a timeout was reached, or
846 * we've acquired all the samples we asked for -- we're done.
847 * Send the (properly-ordered) buffer to the frontend.
848 */
849 if (ctx->trigger_at != -1) {
850 /* a trigger was set up, so we need to tell the frontend
851 * about it.
852 */
853 if (ctx->trigger_at > 0) {
854 /* there are pre-trigger samples, send those first */
855 packet.type = SR_DF_LOGIC;
856 packet.payload = &logic;
857 logic.length = ctx->trigger_at * 4;
858 logic.unitsize = 4;
859 logic.data = ctx->raw_sample_buf +
860 (ctx->limit_samples - ctx->num_samples) * 4;
861 sr_session_send(cb_data, &packet);
862 }
863
864 /* send the trigger */
865 packet.type = SR_DF_TRIGGER;
866 sr_session_send(cb_data, &packet);
867
868 /* send post-trigger samples */
869 packet.type = SR_DF_LOGIC;
870 packet.payload = &logic;
871 logic.length = (ctx->num_samples * 4) - (ctx->trigger_at * 4);
872 logic.unitsize = 4;
873 logic.data = ctx->raw_sample_buf + ctx->trigger_at * 4 +
874 (ctx->limit_samples - ctx->num_samples) * 4;
875 sr_session_send(cb_data, &packet);
876 } else {
877 /* no trigger was used */
878 packet.type = SR_DF_LOGIC;
879 packet.payload = &logic;
880 logic.length = ctx->num_samples * 4;
881 logic.unitsize = 4;
882 logic.data = ctx->raw_sample_buf +
883 (ctx->limit_samples - ctx->num_samples) * 4;
884 sr_session_send(cb_data, &packet);
885 }
886 g_free(ctx->raw_sample_buf);
887
888 serial_flush(fd);
889 serial_close(fd);
890 packet.type = SR_DF_END;
891 sr_session_send(cb_data, &packet);
892 }
893
894 return TRUE;
895}
896
897static int hw_dev_acquisition_start(int dev_index, void *cb_data)
898{
899 struct sr_datafeed_packet *packet;
900 struct sr_datafeed_header *header;
901 struct sr_datafeed_meta_logic meta;
902 struct sr_dev_inst *sdi;
903 struct context *ctx;
904 uint32_t trigger_config[4];
905 uint32_t data;
906 uint16_t readcount, delaycount;
907 uint8_t changrp_mask;
908 int num_channels;
909 int i;
910
911 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index)))
912 return SR_ERR;
913
914 ctx = sdi->priv;
915
916 if (sdi->status != SR_ST_ACTIVE)
917 return SR_ERR;
918
919 /*
920 * Enable/disable channel groups in the flag register according to the
921 * probe mask. Calculate this here, because num_channels is needed
922 * to limit readcount.
923 */
924 changrp_mask = 0;
925 num_channels = 0;
926 for (i = 0; i < 4; i++) {
927 if (ctx->probe_mask & (0xff << (i * 8))) {
928 changrp_mask |= (1 << i);
929 num_channels++;
930 }
931 }
932
933 /*
934 * Limit readcount to prevent reading past the end of the hardware
935 * buffer.
936 */
937 readcount = MIN(ctx->max_samples / num_channels, ctx->limit_samples) / 4;
938
939 memset(trigger_config, 0, 16);
940 trigger_config[ctx->num_stages - 1] |= 0x08;
941 if (ctx->trigger_mask[0]) {
942 delaycount = readcount * (1 - ctx->capture_ratio / 100.0);
943 ctx->trigger_at = (readcount - delaycount) * 4 - ctx->num_stages;
944
945 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
946 reverse32(ctx->trigger_mask[0])) != SR_OK)
947 return SR_ERR;
948 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
949 reverse32(ctx->trigger_value[0])) != SR_OK)
950 return SR_ERR;
951 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
952 trigger_config[0]) != SR_OK)
953 return SR_ERR;
954
955 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_1,
956 reverse32(ctx->trigger_mask[1])) != SR_OK)
957 return SR_ERR;
958 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_1,
959 reverse32(ctx->trigger_value[1])) != SR_OK)
960 return SR_ERR;
961 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
962 trigger_config[1]) != SR_OK)
963 return SR_ERR;
964
965 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_2,
966 reverse32(ctx->trigger_mask[2])) != SR_OK)
967 return SR_ERR;
968 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_2,
969 reverse32(ctx->trigger_value[2])) != SR_OK)
970 return SR_ERR;
971 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
972 trigger_config[2]) != SR_OK)
973 return SR_ERR;
974
975 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_3,
976 reverse32(ctx->trigger_mask[3])) != SR_OK)
977 return SR_ERR;
978 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_3,
979 reverse32(ctx->trigger_value[3])) != SR_OK)
980 return SR_ERR;
981 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
982 trigger_config[3]) != SR_OK)
983 return SR_ERR;
984 } else {
985 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
986 ctx->trigger_mask[0]) != SR_OK)
987 return SR_ERR;
988 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
989 ctx->trigger_value[0]) != SR_OK)
990 return SR_ERR;
991 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
992 0x00000008) != SR_OK)
993 return SR_ERR;
994 delaycount = readcount;
995 }
996
997 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
998 "demux %s)", ctx->cur_samplerate, ctx->cur_samplerate_divider,
999 ctx->flag_reg & FLAG_DEMUX ? "on" : "off");
1000 if (send_longcommand(ctx->serial->fd, CMD_SET_DIVIDER,
1001 reverse32(ctx->cur_samplerate_divider)) != SR_OK)
1002 return SR_ERR;
1003
1004 /* Send sample limit and pre/post-trigger capture ratio. */
1005 data = ((readcount - 1) & 0xffff) << 16;
1006 data |= (delaycount - 1) & 0xffff;
1007 if (send_longcommand(ctx->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
1008 return SR_ERR;
1009
1010 /* The flag register wants them here, and 1 means "disable channel". */
1011 ctx->flag_reg |= ~(changrp_mask << 2) & 0x3c;
1012 ctx->flag_reg |= FLAG_FILTER;
1013 ctx->rle_count = 0;
1014 data = (ctx->flag_reg << 24) | ((ctx->flag_reg << 8) & 0xff0000);
1015 if (send_longcommand(ctx->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
1016 return SR_ERR;
1017
1018 /* Start acquisition on the device. */
1019 if (send_shortcommand(ctx->serial->fd, CMD_RUN) != SR_OK)
1020 return SR_ERR;
1021
1022 sr_source_add(ctx->serial->fd, G_IO_IN, -1, receive_data,
1023 cb_data);
1024
1025 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1026 sr_err("ols: %s: packet malloc failed", __func__);
1027 return SR_ERR_MALLOC;
1028 }
1029
1030 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1031 sr_err("ols: %s: header malloc failed", __func__);
1032 g_free(packet);
1033 return SR_ERR_MALLOC;
1034 }
1035
1036 /* Send header packet to the session bus. */
1037 packet->type = SR_DF_HEADER;
1038 packet->payload = (unsigned char *)header;
1039 header->feed_version = 1;
1040 gettimeofday(&header->starttime, NULL);
1041 sr_session_send(cb_data, packet);
1042
1043 /* Send metadata about the SR_DF_LOGIC packets to come. */
1044 packet->type = SR_DF_META_LOGIC;
1045 packet->payload = &meta;
1046 meta.samplerate = ctx->cur_samplerate;
1047 meta.num_probes = NUM_PROBES;
1048 sr_session_send(cb_data, packet);
1049
1050 g_free(header);
1051 g_free(packet);
1052
1053 return SR_OK;
1054}
1055
1056/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
1057static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1058{
1059 struct sr_datafeed_packet packet;
1060
1061 /* Avoid compiler warnings. */
1062 (void)dev_index;
1063
1064 packet.type = SR_DF_END;
1065 sr_session_send(cb_data, &packet);
1066
1067 return SR_OK;
1068}
1069
1070SR_PRIV struct sr_dev_driver ols_driver_info = {
1071 .name = "ols",
1072 .longname = "Openbench Logic Sniffer",
1073 .api_version = 1,
1074 .init = hw_init,
1075 .cleanup = hw_cleanup,
1076 .scan = hw_scan,
1077 .dev_open = hw_dev_open,
1078 .dev_close = hw_dev_close,
1079 .info_get = hw_info_get,
1080 .dev_status_get = hw_dev_status_get,
1081 .dev_config_set = hw_dev_config_set,
1082 .dev_acquisition_start = hw_dev_acquisition_start,
1083 .dev_acquisition_stop = hw_dev_acquisition_stop,
1084 .instances = NULL,
1085};
Hardware access and backend lib