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sr/drivers: change driver dev_open/dev_close calls to use sdi
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
27#ifdef _WIN32
28#include <windows.h>
29#else
30#include <termios.h>
31#endif
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
35#ifdef _WIN32
36/* TODO */
37#else
38#include <arpa/inet.h>
39#endif
40#include <glib.h>
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
43#include "ols.h"
44
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
49static const int hwcaps[] = {
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
54 SR_HWCAP_RLE,
55 0,
56};
57
58/* Probes are numbered 0-31 (on the PCB silkscreen). */
59static const char *probe_names[NUM_PROBES + 1] = {
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
95/* default supported samplerates, can be overridden by device metadata */
96static const struct sr_samplerates samplerates = {
97 SR_HZ(10),
98 SR_MHZ(200),
99 SR_HZ(1),
100 NULL,
101};
102
103SR_PRIV struct sr_dev_driver ols_driver_info;
104static struct sr_dev_driver *odi = &ols_driver_info;
105
106static int send_shortcommand(int fd, uint8_t command)
107{
108 char buf[1];
109
110 sr_dbg("ols: sending cmd 0x%.2x", command);
111 buf[0] = command;
112 if (serial_write(fd, buf, 1) != 1)
113 return SR_ERR;
114
115 return SR_OK;
116}
117
118static int send_longcommand(int fd, uint8_t command, uint32_t data)
119{
120 char buf[5];
121
122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
123 buf[0] = command;
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
128 if (serial_write(fd, buf, 5) != 5)
129 return SR_ERR;
130
131 return SR_OK;
132}
133
134static int configure_probes(struct context *ctx, const GSList *probes)
135{
136 const struct sr_probe *probe;
137 const GSList *l;
138 int probe_bit, stage, i;
139 char *tc;
140
141 ctx->probe_mask = 0;
142 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
143 ctx->trigger_mask[i] = 0;
144 ctx->trigger_value[i] = 0;
145 }
146
147 ctx->num_stages = 0;
148 for (l = probes; l; l = l->next) {
149 probe = (const struct sr_probe *)l->data;
150 if (!probe->enabled)
151 continue;
152
153 /*
154 * Set up the probe mask for later configuration into the
155 * flag register.
156 */
157 probe_bit = 1 << (probe->index - 1);
158 ctx->probe_mask |= probe_bit;
159
160 if (!probe->trigger)
161 continue;
162
163 /* Configure trigger mask and value. */
164 stage = 0;
165 for (tc = probe->trigger; tc && *tc; tc++) {
166 ctx->trigger_mask[stage] |= probe_bit;
167 if (*tc == '1')
168 ctx->trigger_value[stage] |= probe_bit;
169 stage++;
170 if (stage > 3)
171 /*
172 * TODO: Only supporting parallel mode, with
173 * up to 4 stages.
174 */
175 return SR_ERR;
176 }
177 if (stage > ctx->num_stages)
178 ctx->num_stages = stage;
179 }
180
181 return SR_OK;
182}
183
184static uint32_t reverse16(uint32_t in)
185{
186 uint32_t out;
187
188 out = (in & 0xff) << 8;
189 out |= (in & 0xff00) >> 8;
190 out |= (in & 0xff0000) << 8;
191 out |= (in & 0xff000000) >> 8;
192
193 return out;
194}
195
196static uint32_t reverse32(uint32_t in)
197{
198 uint32_t out;
199
200 out = (in & 0xff) << 24;
201 out |= (in & 0xff00) << 8;
202 out |= (in & 0xff0000) >> 8;
203 out |= (in & 0xff000000) >> 24;
204
205 return out;
206}
207
208static struct context *ols_dev_new(void)
209{
210 struct context *ctx;
211
212 /* TODO: Is 'ctx' ever g_free()'d? */
213 if (!(ctx = g_try_malloc0(sizeof(struct context)))) {
214 sr_err("ols: %s: ctx malloc failed", __func__);
215 return NULL;
216 }
217
218 ctx->trigger_at = -1;
219 ctx->probe_mask = 0xffffffff;
220 ctx->cur_samplerate = SR_KHZ(200);
221 ctx->serial = NULL;
222
223 return ctx;
224}
225
226static struct sr_dev_inst *get_metadata(int fd)
227{
228 struct sr_dev_inst *sdi;
229 struct context *ctx;
230 struct sr_probe *probe;
231 uint32_t tmp_int, ui;
232 uint8_t key, type, token;
233 GString *tmp_str, *devname, *version;
234 guchar tmp_c;
235
236 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
237 sdi->driver = odi;
238 ctx = ols_dev_new();
239 sdi->priv = ctx;
240
241 devname = g_string_new("");
242 version = g_string_new("");
243
244 key = 0xff;
245 while (key) {
246 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
247 break;
248 type = key >> 5;
249 token = key & 0x1f;
250 switch (type) {
251 case 0:
252 /* NULL-terminated string */
253 tmp_str = g_string_new("");
254 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
255 g_string_append_c(tmp_str, tmp_c);
256 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
257 key, tmp_str->str);
258 switch (token) {
259 case 0x01:
260 /* Device name */
261 devname = g_string_append(devname, tmp_str->str);
262 break;
263 case 0x02:
264 /* FPGA firmware version */
265 if (version->len)
266 g_string_append(version, ", ");
267 g_string_append(version, "FPGA version ");
268 g_string_append(version, tmp_str->str);
269 break;
270 case 0x03:
271 /* Ancillary version */
272 if (version->len)
273 g_string_append(version, ", ");
274 g_string_append(version, "Ancillary version ");
275 g_string_append(version, tmp_str->str);
276 break;
277 default:
278 sr_info("ols: unknown token 0x%.2x: '%s'",
279 token, tmp_str->str);
280 break;
281 }
282 g_string_free(tmp_str, TRUE);
283 break;
284 case 1:
285 /* 32-bit unsigned integer */
286 if (serial_read(fd, &tmp_int, 4) != 4)
287 break;
288 tmp_int = reverse32(tmp_int);
289 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
290 key, tmp_int);
291 switch (token) {
292 case 0x00:
293 /* Number of usable probes */
294 for (ui = 0; ui < tmp_int; ui++) {
295 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
296 probe_names[ui])))
297 return 0;
298 sdi->probes = g_slist_append(sdi->probes, probe);
299 }
300 break;
301 case 0x01:
302 /* Amount of sample memory available (bytes) */
303 ctx->max_samples = tmp_int;
304 break;
305 case 0x02:
306 /* Amount of dynamic memory available (bytes) */
307 /* what is this for? */
308 break;
309 case 0x03:
310 /* Maximum sample rate (hz) */
311 ctx->max_samplerate = tmp_int;
312 break;
313 case 0x04:
314 /* protocol version */
315 ctx->protocol_version = tmp_int;
316 break;
317 default:
318 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
319 token, tmp_int);
320 break;
321 }
322 break;
323 case 2:
324 /* 8-bit unsigned integer */
325 if (serial_read(fd, &tmp_c, 1) != 1)
326 break;
327 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
328 key, tmp_c);
329 switch (token) {
330 case 0x00:
331 /* Number of usable probes */
332 for (ui = 0; ui < tmp_c; ui++) {
333 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
334 probe_names[ui])))
335 return 0;
336 sdi->probes = g_slist_append(sdi->probes, probe);
337 }
338 break;
339 case 0x01:
340 /* protocol version */
341 ctx->protocol_version = tmp_c;
342 break;
343 default:
344 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
345 token, tmp_c);
346 break;
347 }
348 break;
349 default:
350 /* unknown type */
351 break;
352 }
353 }
354
355 sdi->model = devname->str;
356 sdi->version = version->str;
357 g_string_free(devname, FALSE);
358 g_string_free(version, FALSE);
359
360 return sdi;
361}
362
363static int hw_init(void)
364{
365
366 /* Nothing to do. */
367
368 return SR_OK;
369}
370
371static GSList *hw_scan(GSList *options)
372{
373 struct sr_dev_inst *sdi;
374 struct context *ctx;
375 struct sr_probe *probe;
376 GSList *devices, *ports, *l;
377 GPollFD *fds, probefd;
378 int devcnt, final_devcnt, num_ports, fd, ret, i, j;
379 char buf[8], **dev_names, **serial_params;
380
381 (void)options;
382 final_devcnt = 0;
383 devices = NULL;
384
385 /* Scan all serial ports. */
386 ports = list_serial_ports();
387 num_ports = g_slist_length(ports);
388
389 if (!(fds = g_try_malloc0(num_ports * sizeof(GPollFD)))) {
390 sr_err("ols: %s: fds malloc failed", __func__);
391 goto hw_init_free_ports; /* TODO: SR_ERR_MALLOC. */
392 }
393
394 if (!(dev_names = g_try_malloc(num_ports * sizeof(char *)))) {
395 sr_err("ols: %s: dev_names malloc failed", __func__);
396 goto hw_init_free_fds; /* TODO: SR_ERR_MALLOC. */
397 }
398
399 if (!(serial_params = g_try_malloc(num_ports * sizeof(char *)))) {
400 sr_err("ols: %s: serial_params malloc failed", __func__);
401 goto hw_init_free_dev_names; /* TODO: SR_ERR_MALLOC. */
402 }
403
404 devcnt = 0;
405 for (l = ports; l; l = l->next) {
406 /* The discovery procedure is like this: first send the Reset
407 * command (0x00) 5 times, since the device could be anywhere
408 * in a 5-byte command. Then send the ID command (0x02).
409 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
410 * have a match.
411 *
412 * Since it may take the device a while to respond at 115Kb/s,
413 * we do all the sending first, then wait for all of them to
414 * respond with g_poll().
415 */
416 sr_info("ols: probing %s...", (char *)l->data);
417 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
418 if (fd != -1) {
419 serial_params[devcnt] = serial_backup_params(fd);
420 serial_set_params(fd, 115200, 8, SERIAL_PARITY_NONE, 1, 2);
421 ret = SR_OK;
422 for (i = 0; i < 5; i++) {
423 if ((ret = send_shortcommand(fd,
424 CMD_RESET)) != SR_OK) {
425 /* Serial port is not writable. */
426 break;
427 }
428 }
429 if (ret != SR_OK) {
430 serial_restore_params(fd,
431 serial_params[devcnt]);
432 serial_close(fd);
433 continue;
434 }
435 send_shortcommand(fd, CMD_ID);
436 fds[devcnt].fd = fd;
437 fds[devcnt].events = G_IO_IN;
438 dev_names[devcnt] = g_strdup(l->data);
439 devcnt++;
440 }
441 g_free(l->data);
442 }
443
444 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
445 usleep(10000);
446
447 g_poll(fds, devcnt, 1);
448
449 for (i = 0; i < devcnt; i++) {
450 if (fds[i].revents != G_IO_IN)
451 continue;
452 if (serial_read(fds[i].fd, buf, 4) != 4)
453 continue;
454 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
455 continue;
456
457 /* definitely using the OLS protocol, check if it supports
458 * the metadata command
459 */
460 send_shortcommand(fds[i].fd, CMD_METADATA);
461 probefd.fd = fds[i].fd;
462 probefd.events = G_IO_IN;
463 if (g_poll(&probefd, 1, 10) > 0) {
464 /* got metadata */
465 sdi = get_metadata(fds[i].fd);
466 sdi->index = final_devcnt;
467 ctx = sdi->priv;
468 } else {
469 /* not an OLS -- some other board that uses the sump protocol */
470 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
471 "Sump", "Logic Analyzer", "v1.0");
472 sdi->driver = odi;
473 ctx = ols_dev_new();
474 for (j = 0; j < 32; j++) {
475 if (!(probe = sr_probe_new(j, SR_PROBE_LOGIC, TRUE,
476 probe_names[j])))
477 return 0;
478 sdi->probes = g_slist_append(sdi->probes, probe);
479 }
480 sdi->priv = ctx;
481 }
482 ctx->serial = sr_serial_dev_inst_new(dev_names[i], -1);
483 odi->instances = g_slist_append(odi->instances, sdi);
484 devices = g_slist_append(devices, sdi);
485
486 final_devcnt++;
487 serial_close(fds[i].fd);
488 fds[i].fd = 0;
489 }
490
491 /* clean up after all the probing */
492 for (i = 0; i < devcnt; i++) {
493 if (fds[i].fd != 0) {
494 serial_restore_params(fds[i].fd, serial_params[i]);
495 serial_close(fds[i].fd);
496 }
497 g_free(serial_params[i]);
498 g_free(dev_names[i]);
499 }
500
501 g_free(serial_params);
502hw_init_free_dev_names:
503 g_free(dev_names);
504hw_init_free_fds:
505 g_free(fds);
506hw_init_free_ports:
507 g_slist_free(ports);
508
509 return devices;
510}
511
512static int hw_dev_open(struct sr_dev_inst *sdi)
513{
514 struct context *ctx;
515
516 ctx = sdi->priv;
517
518 ctx->serial->fd = serial_open(ctx->serial->port, O_RDWR);
519 if (ctx->serial->fd == -1)
520 return SR_ERR;
521
522 sdi->status = SR_ST_ACTIVE;
523
524 return SR_OK;
525}
526
527static int hw_dev_close(struct sr_dev_inst *sdi)
528{
529 struct context *ctx;
530
531 ctx = sdi->priv;
532
533 if (ctx->serial->fd != -1) {
534 serial_close(ctx->serial->fd);
535 ctx->serial->fd = -1;
536 sdi->status = SR_ST_INACTIVE;
537 }
538
539 return SR_OK;
540}
541
542static int hw_cleanup(void)
543{
544 GSList *l;
545 struct sr_dev_inst *sdi;
546 struct context *ctx;
547 int ret = SR_OK;
548
549 /* Properly close and free all devices. */
550 for (l = odi->instances; l; l = l->next) {
551 if (!(sdi = l->data)) {
552 /* Log error, but continue cleaning up the rest. */
553 sr_err("ols: %s: sdi was NULL, continuing", __func__);
554 ret = SR_ERR_BUG;
555 continue;
556 }
557 if (!(ctx = sdi->priv)) {
558 /* Log error, but continue cleaning up the rest. */
559 sr_err("ols: %s: sdi->priv was NULL, continuing",
560 __func__);
561 ret = SR_ERR_BUG;
562 continue;
563 }
564 /* TODO: Check for serial != NULL. */
565 if (ctx->serial->fd != -1)
566 serial_close(ctx->serial->fd);
567 sr_serial_dev_inst_free(ctx->serial);
568 sr_dev_inst_free(sdi);
569 }
570 g_slist_free(odi->instances);
571 odi->instances = NULL;
572
573 return ret;
574}
575
576static int hw_info_get(int info_id, const void **data,
577 const struct sr_dev_inst *sdi)
578{
579 struct context *ctx;
580
581 switch (info_id) {
582 case SR_DI_INST:
583 *data = sdi;
584 break;
585 case SR_DI_HWCAPS:
586 *data = hwcaps;
587 break;
588 case SR_DI_NUM_PROBES:
589 *data = GINT_TO_POINTER(1);
590 break;
591 case SR_DI_PROBE_NAMES:
592 *data = probe_names;
593 break;
594 case SR_DI_SAMPLERATES:
595 *data = &samplerates;
596 break;
597 case SR_DI_TRIGGER_TYPES:
598 *data = (char *)TRIGGER_TYPES;
599 break;
600 case SR_DI_CUR_SAMPLERATE:
601 if (sdi) {
602 ctx = sdi->priv;
603 *data = &ctx->cur_samplerate;
604 } else
605 return SR_ERR;
606 break;
607 default:
608 return SR_ERR_ARG;
609 }
610
611 return SR_OK;
612}
613
614static int hw_dev_status_get(int dev_index)
615{
616 struct sr_dev_inst *sdi;
617
618 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index)))
619 return SR_ST_NOT_FOUND;
620
621 return sdi->status;
622}
623
624static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
625{
626 struct context *ctx;
627
628 ctx = sdi->priv;
629 if (ctx->max_samplerate) {
630 if (samplerate > ctx->max_samplerate)
631 return SR_ERR_SAMPLERATE;
632 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
633 return SR_ERR_SAMPLERATE;
634
635 if (samplerate > CLOCK_RATE) {
636 ctx->flag_reg |= FLAG_DEMUX;
637 ctx->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
638 } else {
639 ctx->flag_reg &= ~FLAG_DEMUX;
640 ctx->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
641 }
642
643 /* Calculate actual samplerate used and complain if it is different
644 * from the requested.
645 */
646 ctx->cur_samplerate = CLOCK_RATE / (ctx->cur_samplerate_divider + 1);
647 if (ctx->flag_reg & FLAG_DEMUX)
648 ctx->cur_samplerate *= 2;
649 if (ctx->cur_samplerate != samplerate)
650 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
651 PRIu64, samplerate, ctx->cur_samplerate);
652
653 return SR_OK;
654}
655
656static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
657 const void *value)
658{
659 struct context *ctx;
660 int ret;
661 const uint64_t *tmp_u64;
662
663 ctx = sdi->priv;
664
665 if (sdi->status != SR_ST_ACTIVE)
666 return SR_ERR;
667
668 switch (hwcap) {
669 case SR_HWCAP_SAMPLERATE:
670 ret = set_samplerate(sdi, *(const uint64_t *)value);
671 break;
672 case SR_HWCAP_PROBECONFIG:
673 ret = configure_probes(ctx, (const GSList *)value);
674 break;
675 case SR_HWCAP_LIMIT_SAMPLES:
676 tmp_u64 = value;
677 if (*tmp_u64 < MIN_NUM_SAMPLES)
678 return SR_ERR;
679 if (*tmp_u64 > ctx->max_samples)
680 sr_err("ols: sample limit exceeds hw max");
681 ctx->limit_samples = *tmp_u64;
682 sr_info("ols: sample limit %" PRIu64, ctx->limit_samples);
683 ret = SR_OK;
684 break;
685 case SR_HWCAP_CAPTURE_RATIO:
686 ctx->capture_ratio = *(const uint64_t *)value;
687 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) {
688 ctx->capture_ratio = 0;
689 ret = SR_ERR;
690 } else
691 ret = SR_OK;
692 break;
693 case SR_HWCAP_RLE:
694 if (GPOINTER_TO_INT(value)) {
695 sr_info("ols: enabling RLE");
696 ctx->flag_reg |= FLAG_RLE;
697 }
698 ret = SR_OK;
699 break;
700 default:
701 ret = SR_ERR;
702 }
703
704 return ret;
705}
706
707static int receive_data(int fd, int revents, void *cb_data)
708{
709 struct sr_datafeed_packet packet;
710 struct sr_datafeed_logic logic;
711 struct sr_dev_inst *sdi;
712 struct context *ctx;
713 GSList *l;
714 int num_channels, offset, i, j;
715 unsigned char byte;
716
717 /* Find this device's ctx struct by its fd. */
718 ctx = NULL;
719 for (l = odi->instances; l; l = l->next) {
720 sdi = l->data;
721 ctx = sdi->priv;
722 if (ctx->serial->fd == fd) {
723 break;
724 }
725 ctx = NULL;
726 }
727 if (!ctx)
728 /* Shouldn't happen. */
729 return TRUE;
730
731 if (ctx->num_transfers++ == 0) {
732 /*
733 * First time round, means the device started sending data,
734 * and will not stop until done. If it stops sending for
735 * longer than it takes to send a byte, that means it's
736 * finished. We'll double that to 30ms to be sure...
737 */
738 sr_source_remove(fd);
739 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
740 ctx->raw_sample_buf = g_try_malloc(ctx->limit_samples * 4);
741 if (!ctx->raw_sample_buf) {
742 sr_err("ols: %s: ctx->raw_sample_buf malloc failed",
743 __func__);
744 return FALSE;
745 }
746 /* fill with 1010... for debugging */
747 memset(ctx->raw_sample_buf, 0x82, ctx->limit_samples * 4);
748 }
749
750 num_channels = 0;
751 for (i = 0x20; i > 0x02; i /= 2) {
752 if ((ctx->flag_reg & i) == 0)
753 num_channels++;
754 }
755
756 if (revents == G_IO_IN) {
757 if (serial_read(fd, &byte, 1) != 1)
758 return FALSE;
759
760 /* Ignore it if we've read enough. */
761 if (ctx->num_samples >= ctx->limit_samples)
762 return TRUE;
763
764 ctx->sample[ctx->num_bytes++] = byte;
765 sr_dbg("ols: received byte 0x%.2x", byte);
766 if (ctx->num_bytes == num_channels) {
767 /* Got a full sample. */
768 sr_dbg("ols: received sample 0x%.*x",
769 ctx->num_bytes * 2, *(int *)ctx->sample);
770 if (ctx->flag_reg & FLAG_RLE) {
771 /*
772 * In RLE mode -1 should never come in as a
773 * sample, because bit 31 is the "count" flag.
774 */
775 if (ctx->sample[ctx->num_bytes - 1] & 0x80) {
776 ctx->sample[ctx->num_bytes - 1] &= 0x7f;
777 /*
778 * FIXME: This will only work on
779 * little-endian systems.
780 */
781 ctx->rle_count = *(int *)(ctx->sample);
782 sr_dbg("ols: RLE count = %d", ctx->rle_count);
783 ctx->num_bytes = 0;
784 return TRUE;
785 }
786 }
787 ctx->num_samples += ctx->rle_count + 1;
788 if (ctx->num_samples > ctx->limit_samples) {
789 /* Save us from overrunning the buffer. */
790 ctx->rle_count -= ctx->num_samples - ctx->limit_samples;
791 ctx->num_samples = ctx->limit_samples;
792 }
793
794 if (num_channels < 4) {
795 /*
796 * Some channel groups may have been turned
797 * off, to speed up transfer between the
798 * hardware and the PC. Expand that here before
799 * submitting it over the session bus --
800 * whatever is listening on the bus will be
801 * expecting a full 32-bit sample, based on
802 * the number of probes.
803 */
804 j = 0;
805 memset(ctx->tmp_sample, 0, 4);
806 for (i = 0; i < 4; i++) {
807 if (((ctx->flag_reg >> 2) & (1 << i)) == 0) {
808 /*
809 * This channel group was
810 * enabled, copy from received
811 * sample.
812 */
813 ctx->tmp_sample[i] = ctx->sample[j++];
814 }
815 }
816 memcpy(ctx->sample, ctx->tmp_sample, 4);
817 sr_dbg("ols: full sample 0x%.8x", *(int *)ctx->sample);
818 }
819
820 /* the OLS sends its sample buffer backwards.
821 * store it in reverse order here, so we can dump
822 * this on the session bus later.
823 */
824 offset = (ctx->limit_samples - ctx->num_samples) * 4;
825 for (i = 0; i <= ctx->rle_count; i++) {
826 memcpy(ctx->raw_sample_buf + offset + (i * 4),
827 ctx->sample, 4);
828 }
829 memset(ctx->sample, 0, 4);
830 ctx->num_bytes = 0;
831 ctx->rle_count = 0;
832 }
833 } else {
834 /*
835 * This is the main loop telling us a timeout was reached, or
836 * we've acquired all the samples we asked for -- we're done.
837 * Send the (properly-ordered) buffer to the frontend.
838 */
839 if (ctx->trigger_at != -1) {
840 /* a trigger was set up, so we need to tell the frontend
841 * about it.
842 */
843 if (ctx->trigger_at > 0) {
844 /* there are pre-trigger samples, send those first */
845 packet.type = SR_DF_LOGIC;
846 packet.payload = &logic;
847 logic.length = ctx->trigger_at * 4;
848 logic.unitsize = 4;
849 logic.data = ctx->raw_sample_buf +
850 (ctx->limit_samples - ctx->num_samples) * 4;
851 sr_session_send(cb_data, &packet);
852 }
853
854 /* send the trigger */
855 packet.type = SR_DF_TRIGGER;
856 sr_session_send(cb_data, &packet);
857
858 /* send post-trigger samples */
859 packet.type = SR_DF_LOGIC;
860 packet.payload = &logic;
861 logic.length = (ctx->num_samples * 4) - (ctx->trigger_at * 4);
862 logic.unitsize = 4;
863 logic.data = ctx->raw_sample_buf + ctx->trigger_at * 4 +
864 (ctx->limit_samples - ctx->num_samples) * 4;
865 sr_session_send(cb_data, &packet);
866 } else {
867 /* no trigger was used */
868 packet.type = SR_DF_LOGIC;
869 packet.payload = &logic;
870 logic.length = ctx->num_samples * 4;
871 logic.unitsize = 4;
872 logic.data = ctx->raw_sample_buf +
873 (ctx->limit_samples - ctx->num_samples) * 4;
874 sr_session_send(cb_data, &packet);
875 }
876 g_free(ctx->raw_sample_buf);
877
878 serial_flush(fd);
879 serial_close(fd);
880 packet.type = SR_DF_END;
881 sr_session_send(cb_data, &packet);
882 }
883
884 return TRUE;
885}
886
887static int hw_dev_acquisition_start(int dev_index, void *cb_data)
888{
889 struct sr_datafeed_packet *packet;
890 struct sr_datafeed_header *header;
891 struct sr_datafeed_meta_logic meta;
892 struct sr_dev_inst *sdi;
893 struct context *ctx;
894 uint32_t trigger_config[4];
895 uint32_t data;
896 uint16_t readcount, delaycount;
897 uint8_t changrp_mask;
898 int num_channels;
899 int i;
900
901 if (!(sdi = sr_dev_inst_get(odi->instances, dev_index)))
902 return SR_ERR;
903
904 ctx = sdi->priv;
905
906 if (sdi->status != SR_ST_ACTIVE)
907 return SR_ERR;
908
909 /*
910 * Enable/disable channel groups in the flag register according to the
911 * probe mask. Calculate this here, because num_channels is needed
912 * to limit readcount.
913 */
914 changrp_mask = 0;
915 num_channels = 0;
916 for (i = 0; i < 4; i++) {
917 if (ctx->probe_mask & (0xff << (i * 8))) {
918 changrp_mask |= (1 << i);
919 num_channels++;
920 }
921 }
922
923 /*
924 * Limit readcount to prevent reading past the end of the hardware
925 * buffer.
926 */
927 readcount = MIN(ctx->max_samples / num_channels, ctx->limit_samples) / 4;
928
929 memset(trigger_config, 0, 16);
930 trigger_config[ctx->num_stages - 1] |= 0x08;
931 if (ctx->trigger_mask[0]) {
932 delaycount = readcount * (1 - ctx->capture_ratio / 100.0);
933 ctx->trigger_at = (readcount - delaycount) * 4 - ctx->num_stages;
934
935 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
936 reverse32(ctx->trigger_mask[0])) != SR_OK)
937 return SR_ERR;
938 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
939 reverse32(ctx->trigger_value[0])) != SR_OK)
940 return SR_ERR;
941 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
942 trigger_config[0]) != SR_OK)
943 return SR_ERR;
944
945 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_1,
946 reverse32(ctx->trigger_mask[1])) != SR_OK)
947 return SR_ERR;
948 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_1,
949 reverse32(ctx->trigger_value[1])) != SR_OK)
950 return SR_ERR;
951 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
952 trigger_config[1]) != SR_OK)
953 return SR_ERR;
954
955 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_2,
956 reverse32(ctx->trigger_mask[2])) != SR_OK)
957 return SR_ERR;
958 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_2,
959 reverse32(ctx->trigger_value[2])) != SR_OK)
960 return SR_ERR;
961 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
962 trigger_config[2]) != SR_OK)
963 return SR_ERR;
964
965 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_3,
966 reverse32(ctx->trigger_mask[3])) != SR_OK)
967 return SR_ERR;
968 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_3,
969 reverse32(ctx->trigger_value[3])) != SR_OK)
970 return SR_ERR;
971 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
972 trigger_config[3]) != SR_OK)
973 return SR_ERR;
974 } else {
975 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
976 ctx->trigger_mask[0]) != SR_OK)
977 return SR_ERR;
978 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
979 ctx->trigger_value[0]) != SR_OK)
980 return SR_ERR;
981 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
982 0x00000008) != SR_OK)
983 return SR_ERR;
984 delaycount = readcount;
985 }
986
987 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
988 "demux %s)", ctx->cur_samplerate, ctx->cur_samplerate_divider,
989 ctx->flag_reg & FLAG_DEMUX ? "on" : "off");
990 if (send_longcommand(ctx->serial->fd, CMD_SET_DIVIDER,
991 reverse32(ctx->cur_samplerate_divider)) != SR_OK)
992 return SR_ERR;
993
994 /* Send sample limit and pre/post-trigger capture ratio. */
995 data = ((readcount - 1) & 0xffff) << 16;
996 data |= (delaycount - 1) & 0xffff;
997 if (send_longcommand(ctx->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
998 return SR_ERR;
999
1000 /* The flag register wants them here, and 1 means "disable channel". */
1001 ctx->flag_reg |= ~(changrp_mask << 2) & 0x3c;
1002 ctx->flag_reg |= FLAG_FILTER;
1003 ctx->rle_count = 0;
1004 data = (ctx->flag_reg << 24) | ((ctx->flag_reg << 8) & 0xff0000);
1005 if (send_longcommand(ctx->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
1006 return SR_ERR;
1007
1008 /* Start acquisition on the device. */
1009 if (send_shortcommand(ctx->serial->fd, CMD_RUN) != SR_OK)
1010 return SR_ERR;
1011
1012 sr_source_add(ctx->serial->fd, G_IO_IN, -1, receive_data,
1013 cb_data);
1014
1015 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1016 sr_err("ols: %s: packet malloc failed", __func__);
1017 return SR_ERR_MALLOC;
1018 }
1019
1020 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1021 sr_err("ols: %s: header malloc failed", __func__);
1022 g_free(packet);
1023 return SR_ERR_MALLOC;
1024 }
1025
1026 /* Send header packet to the session bus. */
1027 packet->type = SR_DF_HEADER;
1028 packet->payload = (unsigned char *)header;
1029 header->feed_version = 1;
1030 gettimeofday(&header->starttime, NULL);
1031 sr_session_send(cb_data, packet);
1032
1033 /* Send metadata about the SR_DF_LOGIC packets to come. */
1034 packet->type = SR_DF_META_LOGIC;
1035 packet->payload = &meta;
1036 meta.samplerate = ctx->cur_samplerate;
1037 meta.num_probes = NUM_PROBES;
1038 sr_session_send(cb_data, packet);
1039
1040 g_free(header);
1041 g_free(packet);
1042
1043 return SR_OK;
1044}
1045
1046/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
1047static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1048{
1049 struct sr_datafeed_packet packet;
1050
1051 /* Avoid compiler warnings. */
1052 (void)dev_index;
1053
1054 packet.type = SR_DF_END;
1055 sr_session_send(cb_data, &packet);
1056
1057 return SR_OK;
1058}
1059
1060SR_PRIV struct sr_dev_driver ols_driver_info = {
1061 .name = "ols",
1062 .longname = "Openbench Logic Sniffer",
1063 .api_version = 1,
1064 .init = hw_init,
1065 .cleanup = hw_cleanup,
1066 .scan = hw_scan,
1067 .dev_open = hw_dev_open,
1068 .dev_close = hw_dev_close,
1069 .info_get = hw_info_get,
1070 .dev_status_get = hw_dev_status_get,
1071 .dev_config_set = hw_dev_config_set,
1072 .dev_acquisition_start = hw_dev_acquisition_start,
1073 .dev_acquisition_stop = hw_dev_acquisition_stop,
1074 .instances = NULL,
1075};
Hardware access and backend lib