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1 | /* | |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef ASIX_SIGMA_H | |
23 | #define ASIX_SIGMA_H | |
24 | ||
25 | enum sigma_write_register { | |
26 | WRITE_CLOCK_SELECT = 0, | |
27 | WRITE_TRIGGER_SELECT0 = 1, | |
28 | WRITE_TRIGGER_SELECT1 = 2, | |
29 | WRITE_MODE = 3, | |
30 | WRITE_MEMROW = 4, | |
31 | WRITE_POST_TRIGGER = 5, | |
32 | WRITE_TRIGGER_OPTION = 6, | |
33 | WRITE_PIN_VIEW = 7, | |
34 | ||
35 | WRITE_TEST = 15, | |
36 | }; | |
37 | ||
38 | enum sigma_read_register { | |
39 | READ_ID = 0, | |
40 | READ_TRIGGER_POS_LOW = 1, | |
41 | READ_TRIGGER_POS_HIGH = 2, | |
42 | READ_TRIGGER_POS_UP = 3, | |
43 | READ_STOP_POS_LOW = 4, | |
44 | READ_STOP_POS_HIGH = 5, | |
45 | READ_STOP_POS_UP = 6, | |
46 | READ_MODE = 7, | |
47 | READ_PIN_CHANGE_LOW = 8, | |
48 | READ_PIN_CHANGE_HIGH = 9, | |
49 | READ_BLOCK_LAST_TS_LOW = 10, | |
50 | READ_BLOCK_LAST_TS_HIGH = 11, | |
51 | READ_PIN_VIEW = 12, | |
52 | ||
53 | READ_TEST = 15, | |
54 | }; | |
55 | ||
56 | #define REG_ADDR_LOW (0 << 4) | |
57 | #define REG_ADDR_HIGH (1 << 4) | |
58 | #define REG_DATA_LOW (2 << 4) | |
59 | #define REG_DATA_HIGH_WRITE (3 << 4) | |
60 | #define REG_READ_ADDR (4 << 4) | |
61 | #define REG_DRAM_WAIT_ACK (5 << 4) | |
62 | ||
63 | /* Bit (1 << 4) can be low or high (double buffer / cache) */ | |
64 | #define REG_DRAM_BLOCK (6 << 4) | |
65 | #define REG_DRAM_BLOCK_BEGIN (8 << 4) | |
66 | #define REG_DRAM_BLOCK_DATA (10 << 4) | |
67 | ||
68 | #define LEDSEL0 6 | |
69 | #define LEDSEL1 7 | |
70 | ||
71 | #define NEXT_REG 1 | |
72 | ||
73 | #define EVENTS_PER_CLUSTER 7 | |
74 | ||
75 | #define CHUNK_SIZE 1024 | |
76 | ||
77 | struct clockselect_50 { | |
78 | uint8_t async; | |
79 | uint8_t fraction; | |
80 | uint16_t disabled_probes; | |
81 | }; | |
82 | ||
83 | /* The effect of all these are still a bit unclear. */ | |
84 | struct triggerinout { | |
85 | uint8_t trgout_resistor_enable : 1; | |
86 | uint8_t trgout_resistor_pullup : 1; | |
87 | uint8_t reserved1 : 1; | |
88 | uint8_t trgout_bytrigger : 1; | |
89 | uint8_t trgout_byevent : 1; | |
90 | uint8_t trgout_bytriggerin : 1; | |
91 | uint8_t reserved2 : 2; | |
92 | ||
93 | /* Should be set same as the first two */ | |
94 | uint8_t trgout_resistor_enable2 : 1; | |
95 | uint8_t trgout_resistor_pullup2 : 1; | |
96 | ||
97 | uint8_t reserved3 : 1; | |
98 | uint8_t trgout_long : 1; | |
99 | uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */ | |
100 | uint8_t trgin_negate : 1; | |
101 | uint8_t trgout_enable : 1; | |
102 | uint8_t trgin_enable : 1; | |
103 | }; | |
104 | ||
105 | struct triggerlut { | |
106 | /* The actual LUTs. */ | |
107 | uint16_t m0d[4], m1d[4], m2d[4]; | |
108 | uint16_t m3, m3s, m4; | |
109 | ||
110 | /* Paramters should be sent as a single register write. */ | |
111 | struct { | |
112 | uint8_t selc : 2; | |
113 | uint8_t selpresc : 6; | |
114 | ||
115 | uint8_t selinc : 2; | |
116 | uint8_t selres : 2; | |
117 | uint8_t sela : 2; | |
118 | uint8_t selb : 2; | |
119 | ||
120 | uint16_t cmpb; | |
121 | uint16_t cmpa; | |
122 | } params; | |
123 | }; | |
124 | ||
125 | /* Trigger configuration */ | |
126 | struct sigma_trigger { | |
127 | /* Single-pin trigger support (100 and 200 MHz).*/ | |
128 | uint8_t fast_pin; | |
129 | uint8_t fast_fall; | |
130 | ||
131 | /* Simple trigger support (<= 50 MHz). */ | |
132 | uint16_t simplemask; | |
133 | uint16_t simplevalue; | |
134 | ||
135 | /* Only two probes can be used in mask */ | |
136 | uint16_t risingmask; | |
137 | uint16_t fallingmask; | |
138 | ||
139 | /* TODO: Advanced trigger support (boolean expressions). */ | |
140 | }; | |
141 | ||
142 | /* Events for trigger operation. */ | |
143 | enum triggerop { | |
144 | OP_LEVEL = 1, | |
145 | OP_NOT, | |
146 | OP_RISE, | |
147 | OP_FALL, | |
148 | OP_RISEFALL, | |
149 | OP_NOTRISE, | |
150 | OP_NOTFALL, | |
151 | OP_NOTRISEFALL, | |
152 | }; | |
153 | ||
154 | /* Logical functions for trigger operation. */ | |
155 | enum triggerfunc { | |
156 | FUNC_AND = 1, | |
157 | FUNC_NAND, | |
158 | FUNC_OR, | |
159 | FUNC_NOR, | |
160 | FUNC_XOR, | |
161 | FUNC_NXOR, | |
162 | }; | |
163 | ||
164 | #endif |