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sr: remove obsolete SR_DI_INST
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45
46static const uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60/*
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *probe_names[NUM_PROBES + 1] = {
66 "1",
67 "2",
68 "3",
69 "4",
70 "5",
71 "6",
72 "7",
73 "8",
74 "9",
75 "10",
76 "11",
77 "12",
78 "13",
79 "14",
80 "15",
81 "16",
82 NULL,
83};
84
85static const struct sr_samplerates samplerates = {
86 0,
87 0,
88 0,
89 supported_samplerates,
90};
91
92static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
94 SR_HWCAP_SAMPLERATE,
95 SR_HWCAP_CAPTURE_RATIO,
96 SR_HWCAP_PROBECONFIG,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
127 void *cb_data);
128
129static int sigma_read(void *buf, size_t size, struct context *ctx)
130{
131 int ret;
132
133 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
134 if (ret < 0) {
135 sr_err("sigma: ftdi_read_data failed: %s",
136 ftdi_get_error_string(&ctx->ftdic));
137 }
138
139 return ret;
140}
141
142static int sigma_write(void *buf, size_t size, struct context *ctx)
143{
144 int ret;
145
146 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
147 if (ret < 0) {
148 sr_err("sigma: ftdi_write_data failed: %s",
149 ftdi_get_error_string(&ctx->ftdic));
150 } else if ((size_t) ret != size) {
151 sr_err("sigma: ftdi_write_data did not complete write.");
152 }
153
154 return ret;
155}
156
157static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
158 struct context *ctx)
159{
160 size_t i;
161 uint8_t buf[len + 2];
162 int idx = 0;
163
164 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
165 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166
167 for (i = 0; i < len; ++i) {
168 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
169 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
170 }
171
172 return sigma_write(buf, idx, ctx);
173}
174
175static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
176{
177 return sigma_write_register(reg, &value, 1, ctx);
178}
179
180static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
181 struct context *ctx)
182{
183 uint8_t buf[3];
184
185 buf[0] = REG_ADDR_LOW | (reg & 0xf);
186 buf[1] = REG_ADDR_HIGH | (reg >> 4);
187 buf[2] = REG_READ_ADDR;
188
189 sigma_write(buf, sizeof(buf), ctx);
190
191 return sigma_read(data, len, ctx);
192}
193
194static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
195{
196 uint8_t value;
197
198 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
199 sr_err("sigma: sigma_get_register: 1 byte expected");
200 return 0;
201 }
202
203 return value;
204}
205
206static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
207 struct context *ctx)
208{
209 uint8_t buf[] = {
210 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 REG_READ_ADDR | NEXT_REG,
218 };
219 uint8_t result[6];
220
221 sigma_write(buf, sizeof(buf), ctx);
222
223 sigma_read(result, sizeof(result), ctx);
224
225 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
226 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227
228 /* Not really sure why this must be done, but according to spec. */
229 if ((--*stoppos & 0x1ff) == 0x1ff)
230 stoppos -= 64;
231
232 if ((*--triggerpos & 0x1ff) == 0x1ff)
233 triggerpos -= 64;
234
235 return 1;
236}
237
238static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
239 uint8_t *data, struct context *ctx)
240{
241 size_t i;
242 uint8_t buf[4096];
243 int idx = 0;
244
245 /* Send the startchunk. Index start with 1. */
246 buf[0] = startchunk >> 8;
247 buf[1] = startchunk & 0xff;
248 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
249
250 /* Read the DRAM. */
251 buf[idx++] = REG_DRAM_BLOCK;
252 buf[idx++] = REG_DRAM_WAIT_ACK;
253
254 for (i = 0; i < numchunks; ++i) {
255 /* Alternate bit to copy from DRAM to cache. */
256 if (i != (numchunks - 1))
257 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258
259 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260
261 if (i != (numchunks - 1))
262 buf[idx++] = REG_DRAM_WAIT_ACK;
263 }
264
265 sigma_write(buf, idx, ctx);
266
267 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
268}
269
270/* Upload trigger look-up tables to Sigma. */
271static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
272{
273 int i;
274 uint8_t tmp[2];
275 uint16_t bit;
276
277 /* Transpose the table and send to Sigma. */
278 for (i = 0; i < 16; ++i) {
279 bit = 1 << i;
280
281 tmp[0] = tmp[1] = 0;
282
283 if (lut->m2d[0] & bit)
284 tmp[0] |= 0x01;
285 if (lut->m2d[1] & bit)
286 tmp[0] |= 0x02;
287 if (lut->m2d[2] & bit)
288 tmp[0] |= 0x04;
289 if (lut->m2d[3] & bit)
290 tmp[0] |= 0x08;
291
292 if (lut->m3 & bit)
293 tmp[0] |= 0x10;
294 if (lut->m3s & bit)
295 tmp[0] |= 0x20;
296 if (lut->m4 & bit)
297 tmp[0] |= 0x40;
298
299 if (lut->m0d[0] & bit)
300 tmp[1] |= 0x01;
301 if (lut->m0d[1] & bit)
302 tmp[1] |= 0x02;
303 if (lut->m0d[2] & bit)
304 tmp[1] |= 0x04;
305 if (lut->m0d[3] & bit)
306 tmp[1] |= 0x08;
307
308 if (lut->m1d[0] & bit)
309 tmp[1] |= 0x10;
310 if (lut->m1d[1] & bit)
311 tmp[1] |= 0x20;
312 if (lut->m1d[2] & bit)
313 tmp[1] |= 0x40;
314 if (lut->m1d[3] & bit)
315 tmp[1] |= 0x80;
316
317 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 ctx);
319 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
320 }
321
322 /* Send the parameters */
323 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
324 sizeof(lut->params), ctx);
325
326 return SR_OK;
327}
328
329/* Generate the bitbang stream for programming the FPGA. */
330static int bin2bitbang(const char *filename,
331 unsigned char **buf, size_t *buf_size)
332{
333 FILE *f;
334 unsigned long file_size;
335 unsigned long offset = 0;
336 unsigned char *p;
337 uint8_t *firmware;
338 unsigned long fwsize = 0;
339 const int buffer_size = 65536;
340 size_t i;
341 int c, bit, v;
342 uint32_t imm = 0x3f6df2ab;
343
344 f = g_fopen(filename, "rb");
345 if (!f) {
346 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
347 return SR_ERR;
348 }
349
350 if (-1 == fseek(f, 0, SEEK_END)) {
351 sr_err("sigma: fseek on %s failed", filename);
352 fclose(f);
353 return SR_ERR;
354 }
355
356 file_size = ftell(f);
357
358 fseek(f, 0, SEEK_SET);
359
360 if (!(firmware = g_try_malloc(buffer_size))) {
361 sr_err("sigma: %s: firmware malloc failed", __func__);
362 fclose(f);
363 return SR_ERR_MALLOC;
364 }
365
366 while ((c = getc(f)) != EOF) {
367 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
368 firmware[fwsize++] = c ^ imm;
369 }
370 fclose(f);
371
372 if(fwsize != file_size) {
373 sr_err("sigma: %s: Error reading firmware", filename);
374 fclose(f);
375 g_free(firmware);
376 return SR_ERR;
377 }
378
379 *buf_size = fwsize * 2 * 8;
380
381 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
382 if (!p) {
383 sr_err("sigma: %s: buf/p malloc failed", __func__);
384 g_free(firmware);
385 return SR_ERR_MALLOC;
386 }
387
388 for (i = 0; i < fwsize; ++i) {
389 for (bit = 7; bit >= 0; --bit) {
390 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
391 p[offset++] = v | 0x01;
392 p[offset++] = v;
393 }
394 }
395
396 g_free(firmware);
397
398 if (offset != *buf_size) {
399 g_free(*buf);
400 sr_err("sigma: Error reading firmware %s "
401 "offset=%ld, file_size=%ld, buf_size=%zd.",
402 filename, offset, file_size, *buf_size);
403
404 return SR_ERR;
405 }
406
407 return SR_OK;
408}
409
410static void clear_instances(void)
411{
412 GSList *l;
413 struct sr_dev_inst *sdi;
414 struct context *ctx;
415
416 /* Properly close all devices. */
417 for (l = adi->instances; l; l = l->next) {
418 if (!(sdi = l->data)) {
419 /* Log error, but continue cleaning up the rest. */
420 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
421 continue;
422 }
423 if (sdi->priv) {
424 ctx = sdi->priv;
425 ftdi_free(&ctx->ftdic);
426 g_free(ctx);
427 }
428 sr_dev_inst_free(sdi);
429 }
430 g_slist_free(adi->instances);
431 adi->instances = NULL;
432
433}
434
435static int hw_init(void)
436{
437
438 /* Nothing to do. */
439
440 return SR_OK;
441}
442
443static GSList *hw_scan(GSList *options)
444{
445 struct sr_dev_inst *sdi;
446 struct sr_probe *probe;
447 struct context *ctx;
448 GSList *devices;
449 struct ftdi_device_list *devlist;
450 char serial_txt[10];
451 uint32_t serial;
452 int ret, i;
453
454 (void)options;
455 devices = NULL;
456 clear_instances();
457
458 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
459 sr_err("sigma: %s: ctx malloc failed", __func__);
460 return NULL;
461 }
462
463 ftdi_init(&ctx->ftdic);
464
465 /* Look for SIGMAs. */
466
467 if ((ret = ftdi_usb_find_all(&ctx->ftdic, &devlist,
468 USB_VENDOR, USB_PRODUCT)) <= 0) {
469 if (ret < 0)
470 sr_err("ftdi_usb_find_all(): %d", ret);
471 goto free;
472 }
473
474 /* Make sure it's a version 1 or 2 SIGMA. */
475 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
476 serial_txt, sizeof(serial_txt));
477 sscanf(serial_txt, "%x", &serial);
478
479 if (serial < 0xa6010000 || serial > 0xa602ffff) {
480 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
481 "in this version of sigrok.");
482 goto free;
483 }
484
485 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
486
487 ctx->cur_samplerate = 0;
488 ctx->period_ps = 0;
489 ctx->limit_msec = 0;
490 ctx->cur_firmware = -1;
491 ctx->num_probes = 0;
492 ctx->samples_per_event = 0;
493 ctx->capture_ratio = 50;
494 ctx->use_triggers = 0;
495
496 /* Register SIGMA device. */
497 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
498 USB_MODEL_NAME, USB_MODEL_VERSION))) {
499 sr_err("sigma: %s: sdi was NULL", __func__);
500 goto free;
501 }
502 sdi->driver = adi;
503
504 for (i = 0; probe_names[i]; i++) {
505 if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE,
506 probe_names[i])))
507 return NULL;
508 sdi->probes = g_slist_append(sdi->probes, probe);
509 }
510
511 devices = g_slist_append(devices, sdi);
512 adi->instances = g_slist_append(adi->instances, sdi);
513 sdi->priv = ctx;
514
515 /* We will open the device again when we need it. */
516 ftdi_list_free(&devlist);
517
518 return devices;
519
520free:
521 ftdi_deinit(&ctx->ftdic);
522 g_free(ctx);
523 return NULL;
524}
525
526static int upload_firmware(int firmware_idx, struct context *ctx)
527{
528 int ret;
529 unsigned char *buf;
530 unsigned char pins;
531 size_t buf_size;
532 unsigned char result[32];
533 char firmware_path[128];
534
535 /* Make sure it's an ASIX SIGMA. */
536 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
537 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
538 sr_err("sigma: ftdi_usb_open failed: %s",
539 ftdi_get_error_string(&ctx->ftdic));
540 return 0;
541 }
542
543 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
544 sr_err("sigma: ftdi_set_bitmode failed: %s",
545 ftdi_get_error_string(&ctx->ftdic));
546 return 0;
547 }
548
549 /* Four times the speed of sigmalogan - Works well. */
550 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
551 sr_err("sigma: ftdi_set_baudrate failed: %s",
552 ftdi_get_error_string(&ctx->ftdic));
553 return 0;
554 }
555
556 /* Force the FPGA to reboot. */
557 sigma_write(suicide, sizeof(suicide), ctx);
558 sigma_write(suicide, sizeof(suicide), ctx);
559 sigma_write(suicide, sizeof(suicide), ctx);
560 sigma_write(suicide, sizeof(suicide), ctx);
561
562 /* Prepare to upload firmware (FPGA specific). */
563 sigma_write(init, sizeof(init), ctx);
564
565 ftdi_usb_purge_buffers(&ctx->ftdic);
566
567 /* Wait until the FPGA asserts INIT_B. */
568 while (1) {
569 ret = sigma_read(result, 1, ctx);
570 if (result[0] & 0x20)
571 break;
572 }
573
574 /* Prepare firmware. */
575 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
576 firmware_files[firmware_idx]);
577
578 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
579 sr_err("sigma: An error occured while reading the firmware: %s",
580 firmware_path);
581 return ret;
582 }
583
584 /* Upload firmare. */
585 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
586 sigma_write(buf, buf_size, ctx);
587
588 g_free(buf);
589
590 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
591 sr_err("sigma: ftdi_set_bitmode failed: %s",
592 ftdi_get_error_string(&ctx->ftdic));
593 return SR_ERR;
594 }
595
596 ftdi_usb_purge_buffers(&ctx->ftdic);
597
598 /* Discard garbage. */
599 while (1 == sigma_read(&pins, 1, ctx))
600 ;
601
602 /* Initialize the logic analyzer mode. */
603 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
604
605 /* Expect a 3 byte reply. */
606 ret = sigma_read(result, 3, ctx);
607 if (ret != 3 ||
608 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
609 sr_err("sigma: Configuration failed. Invalid reply received.");
610 return SR_ERR;
611 }
612
613 ctx->cur_firmware = firmware_idx;
614
615 sr_info("sigma: Firmware uploaded");
616
617 return SR_OK;
618}
619
620static int hw_dev_open(struct sr_dev_inst *sdi)
621{
622 struct context *ctx;
623 int ret;
624
625 ctx = sdi->priv;
626
627 /* Make sure it's an ASIX SIGMA. */
628 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
629 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
630
631 sr_err("sigma: ftdi_usb_open failed: %s",
632 ftdi_get_error_string(&ctx->ftdic));
633
634 return 0;
635 }
636
637 sdi->status = SR_ST_ACTIVE;
638
639 return SR_OK;
640}
641
642static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
643{
644 int i, ret;
645 struct context *ctx = sdi->priv;
646
647 for (i = 0; supported_samplerates[i]; i++) {
648 if (supported_samplerates[i] == samplerate)
649 break;
650 }
651 if (supported_samplerates[i] == 0)
652 return SR_ERR_SAMPLERATE;
653
654 if (samplerate <= SR_MHZ(50)) {
655 ret = upload_firmware(0, ctx);
656 ctx->num_probes = 16;
657 }
658 if (samplerate == SR_MHZ(100)) {
659 ret = upload_firmware(1, ctx);
660 ctx->num_probes = 8;
661 }
662 else if (samplerate == SR_MHZ(200)) {
663 ret = upload_firmware(2, ctx);
664 ctx->num_probes = 4;
665 }
666
667 ctx->cur_samplerate = samplerate;
668 ctx->period_ps = 1000000000000 / samplerate;
669 ctx->samples_per_event = 16 / ctx->num_probes;
670 ctx->state.state = SIGMA_IDLE;
671
672 return ret;
673}
674
675/*
676 * In 100 and 200 MHz mode, only a single pin rising/falling can be
677 * set as trigger. In other modes, two rising/falling triggers can be set,
678 * in addition to value/mask trigger for any number of probes.
679 *
680 * The Sigma supports complex triggers using boolean expressions, but this
681 * has not been implemented yet.
682 */
683static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes)
684{
685 struct context *ctx = sdi->priv;
686 const struct sr_probe *probe;
687 const GSList *l;
688 int trigger_set = 0;
689 int probebit;
690
691 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
692
693 for (l = probes; l; l = l->next) {
694 probe = (struct sr_probe *)l->data;
695 probebit = 1 << (probe->index);
696
697 if (!probe->enabled || !probe->trigger)
698 continue;
699
700 if (ctx->cur_samplerate >= SR_MHZ(100)) {
701 /* Fast trigger support. */
702 if (trigger_set) {
703 sr_err("sigma: ASIX SIGMA only supports a single "
704 "pin trigger in 100 and 200MHz mode.");
705 return SR_ERR;
706 }
707 if (probe->trigger[0] == 'f')
708 ctx->trigger.fallingmask |= probebit;
709 else if (probe->trigger[0] == 'r')
710 ctx->trigger.risingmask |= probebit;
711 else {
712 sr_err("sigma: ASIX SIGMA only supports "
713 "rising/falling trigger in 100 "
714 "and 200MHz mode.");
715 return SR_ERR;
716 }
717
718 ++trigger_set;
719 } else {
720 /* Simple trigger support (event). */
721 if (probe->trigger[0] == '1') {
722 ctx->trigger.simplevalue |= probebit;
723 ctx->trigger.simplemask |= probebit;
724 }
725 else if (probe->trigger[0] == '0') {
726 ctx->trigger.simplevalue &= ~probebit;
727 ctx->trigger.simplemask |= probebit;
728 }
729 else if (probe->trigger[0] == 'f') {
730 ctx->trigger.fallingmask |= probebit;
731 ++trigger_set;
732 }
733 else if (probe->trigger[0] == 'r') {
734 ctx->trigger.risingmask |= probebit;
735 ++trigger_set;
736 }
737
738 /*
739 * Actually, Sigma supports 2 rising/falling triggers,
740 * but they are ORed and the current trigger syntax
741 * does not permit ORed triggers.
742 */
743 if (trigger_set > 1) {
744 sr_err("sigma: ASIX SIGMA only supports 1 "
745 "rising/falling triggers.");
746 return SR_ERR;
747 }
748 }
749
750 if (trigger_set)
751 ctx->use_triggers = 1;
752 }
753
754 return SR_OK;
755}
756
757static int hw_dev_close(struct sr_dev_inst *sdi)
758{
759 struct context *ctx;
760
761 if (!(ctx = sdi->priv)) {
762 sr_err("sigma: %s: sdi->priv was NULL", __func__);
763 return SR_ERR_BUG;
764 }
765
766 /* TODO */
767 if (sdi->status == SR_ST_ACTIVE)
768 ftdi_usb_close(&ctx->ftdic);
769
770 sdi->status = SR_ST_INACTIVE;
771
772 return SR_OK;
773}
774
775static int hw_cleanup(void)
776{
777
778 clear_instances();
779
780 return SR_OK;
781}
782
783static int hw_info_get(int info_id, const void **data,
784 const struct sr_dev_inst *sdi)
785{
786 struct context *ctx;
787
788 switch (info_id) {
789 case SR_DI_HWCAPS:
790 *data = hwcaps;
791 break;
792 case SR_DI_NUM_PROBES:
793 *data = GINT_TO_POINTER(NUM_PROBES);
794 break;
795 case SR_DI_PROBE_NAMES:
796 *data = probe_names;
797 break;
798 case SR_DI_SAMPLERATES:
799 *data = &samplerates;
800 break;
801 case SR_DI_TRIGGER_TYPES:
802 *data = (char *)TRIGGER_TYPES;
803 break;
804 case SR_DI_CUR_SAMPLERATE:
805 if (sdi) {
806 ctx = sdi->priv;
807 *data = &ctx->cur_samplerate;
808 } else
809 return SR_ERR;
810 break;
811 default:
812 return SR_ERR_ARG;
813 }
814
815 return SR_OK;
816}
817
818static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
819 const void *value)
820{
821 struct context *ctx;
822 int ret;
823
824 ctx = sdi->priv;
825
826 if (hwcap == SR_HWCAP_SAMPLERATE) {
827 ret = set_samplerate(sdi, *(const uint64_t *)value);
828 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
829 ret = configure_probes(sdi, value);
830 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
831 ctx->limit_msec = *(const uint64_t *)value;
832 if (ctx->limit_msec > 0)
833 ret = SR_OK;
834 else
835 ret = SR_ERR;
836 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
837 ctx->capture_ratio = *(const uint64_t *)value;
838 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
839 ret = SR_ERR;
840 else
841 ret = SR_OK;
842 } else {
843 ret = SR_ERR;
844 }
845
846 return ret;
847}
848
849/* Software trigger to determine exact trigger position. */
850static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
851 struct sigma_trigger *t)
852{
853 int i;
854
855 for (i = 0; i < 8; ++i) {
856 if (i > 0)
857 last_sample = samples[i-1];
858
859 /* Simple triggers. */
860 if ((samples[i] & t->simplemask) != t->simplevalue)
861 continue;
862
863 /* Rising edge. */
864 if ((last_sample & t->risingmask) != 0 || (samples[i] &
865 t->risingmask) != t->risingmask)
866 continue;
867
868 /* Falling edge. */
869 if ((last_sample & t->fallingmask) != t->fallingmask ||
870 (samples[i] & t->fallingmask) != 0)
871 continue;
872
873 break;
874 }
875
876 /* If we did not match, return original trigger pos. */
877 return i & 0x7;
878}
879
880/*
881 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
882 * Each event is 20ns apart, and can contain multiple samples.
883 *
884 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
885 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
886 * For 50 MHz and below, events contain one sample for each channel,
887 * spread 20 ns apart.
888 */
889static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
890 uint16_t *lastsample, int triggerpos,
891 uint16_t limit_chunk, void *cb_data)
892{
893 struct sr_dev_inst *sdi = cb_data;
894 struct context *ctx = sdi->priv;
895 uint16_t tsdiff, ts;
896 uint16_t samples[65536 * ctx->samples_per_event];
897 struct sr_datafeed_packet packet;
898 struct sr_datafeed_logic logic;
899 int i, j, k, l, numpad, tosend;
900 size_t n = 0, sent = 0;
901 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
902 uint16_t *event;
903 uint16_t cur_sample;
904 int triggerts = -1;
905
906 /* Check if trigger is in this chunk. */
907 if (triggerpos != -1) {
908 if (ctx->cur_samplerate <= SR_MHZ(50))
909 triggerpos -= EVENTS_PER_CLUSTER - 1;
910
911 if (triggerpos < 0)
912 triggerpos = 0;
913
914 /* Find in which cluster the trigger occured. */
915 triggerts = triggerpos / 7;
916 }
917
918 /* For each ts. */
919 for (i = 0; i < 64; ++i) {
920 ts = *(uint16_t *) &buf[i * 16];
921 tsdiff = ts - *lastts;
922 *lastts = ts;
923
924 /* Decode partial chunk. */
925 if (limit_chunk && ts > limit_chunk)
926 return SR_OK;
927
928 /* Pad last sample up to current point. */
929 numpad = tsdiff * ctx->samples_per_event - clustersize;
930 if (numpad > 0) {
931 for (j = 0; j < numpad; ++j)
932 samples[j] = *lastsample;
933
934 n = numpad;
935 }
936
937 /* Send samples between previous and this timestamp to sigrok. */
938 sent = 0;
939 while (sent < n) {
940 tosend = MIN(2048, n - sent);
941
942 packet.type = SR_DF_LOGIC;
943 packet.payload = &logic;
944 logic.length = tosend * sizeof(uint16_t);
945 logic.unitsize = 2;
946 logic.data = samples + sent;
947 sr_session_send(ctx->session_dev_id, &packet);
948
949 sent += tosend;
950 }
951 n = 0;
952
953 event = (uint16_t *) &buf[i * 16 + 2];
954 cur_sample = 0;
955
956 /* For each event in cluster. */
957 for (j = 0; j < 7; ++j) {
958
959 /* For each sample in event. */
960 for (k = 0; k < ctx->samples_per_event; ++k) {
961 cur_sample = 0;
962
963 /* For each probe. */
964 for (l = 0; l < ctx->num_probes; ++l)
965 cur_sample |= (!!(event[j] & (1 << (l *
966 ctx->samples_per_event + k)))) << l;
967
968 samples[n++] = cur_sample;
969 }
970 }
971
972 /* Send data up to trigger point (if triggered). */
973 sent = 0;
974 if (i == triggerts) {
975 /*
976 * Trigger is not always accurate to sample because of
977 * pipeline delay. However, it always triggers before
978 * the actual event. We therefore look at the next
979 * samples to pinpoint the exact position of the trigger.
980 */
981 tosend = get_trigger_offset(samples, *lastsample,
982 &ctx->trigger);
983
984 if (tosend > 0) {
985 packet.type = SR_DF_LOGIC;
986 packet.payload = &logic;
987 logic.length = tosend * sizeof(uint16_t);
988 logic.unitsize = 2;
989 logic.data = samples;
990 sr_session_send(ctx->session_dev_id, &packet);
991
992 sent += tosend;
993 }
994
995 /* Only send trigger if explicitly enabled. */
996 if (ctx->use_triggers) {
997 packet.type = SR_DF_TRIGGER;
998 sr_session_send(ctx->session_dev_id, &packet);
999 }
1000 }
1001
1002 /* Send rest of the chunk to sigrok. */
1003 tosend = n - sent;
1004
1005 if (tosend > 0) {
1006 packet.type = SR_DF_LOGIC;
1007 packet.payload = &logic;
1008 logic.length = tosend * sizeof(uint16_t);
1009 logic.unitsize = 2;
1010 logic.data = samples + sent;
1011 sr_session_send(ctx->session_dev_id, &packet);
1012 }
1013
1014 *lastsample = samples[n - 1];
1015 }
1016
1017 return SR_OK;
1018}
1019
1020static int receive_data(int fd, int revents, void *cb_data)
1021{
1022 struct sr_dev_inst *sdi = cb_data;
1023 struct context *ctx = sdi->priv;
1024 struct sr_datafeed_packet packet;
1025 const int chunks_per_read = 32;
1026 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1027 int bufsz, numchunks, i, newchunks;
1028 uint64_t running_msec;
1029 struct timeval tv;
1030
1031 /* Avoid compiler warnings. */
1032 (void)fd;
1033 (void)revents;
1034
1035 /* Get the current position. */
1036 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1037
1038 numchunks = (ctx->state.stoppos + 511) / 512;
1039
1040 if (ctx->state.state == SIGMA_IDLE)
1041 return TRUE;
1042
1043 if (ctx->state.state == SIGMA_CAPTURE) {
1044 /* Check if the timer has expired, or memory is full. */
1045 gettimeofday(&tv, 0);
1046 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1047 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1048
1049 if (running_msec < ctx->limit_msec && numchunks < 32767)
1050 return TRUE; /* While capturing... */
1051 else
1052 hw_dev_acquisition_stop(sdi, sdi);
1053
1054 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1055 if (ctx->state.chunks_downloaded >= numchunks) {
1056 /* End of samples. */
1057 packet.type = SR_DF_END;
1058 sr_session_send(ctx->session_dev_id, &packet);
1059
1060 ctx->state.state = SIGMA_IDLE;
1061
1062 return TRUE;
1063 }
1064
1065 newchunks = MIN(chunks_per_read,
1066 numchunks - ctx->state.chunks_downloaded);
1067
1068 sr_info("sigma: Downloading sample data: %.0f %%",
1069 100.0 * ctx->state.chunks_downloaded / numchunks);
1070
1071 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1072 newchunks, buf, ctx);
1073 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1074 (void)bufsz;
1075
1076 /* Find first ts. */
1077 if (ctx->state.chunks_downloaded == 0) {
1078 ctx->state.lastts = *(uint16_t *) buf - 1;
1079 ctx->state.lastsample = 0;
1080 }
1081
1082 /* Decode chunks and send them to sigrok. */
1083 for (i = 0; i < newchunks; ++i) {
1084 int limit_chunk = 0;
1085
1086 /* The last chunk may potentially be only in part. */
1087 if (ctx->state.chunks_downloaded == numchunks - 1) {
1088 /* Find the last valid timestamp */
1089 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1090 }
1091
1092 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1093 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1094 &ctx->state.lastts,
1095 &ctx->state.lastsample,
1096 ctx->state.triggerpos & 0x1ff,
1097 limit_chunk, sdi);
1098 else
1099 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1100 &ctx->state.lastts,
1101 &ctx->state.lastsample,
1102 -1, limit_chunk, sdi);
1103
1104 ++ctx->state.chunks_downloaded;
1105 }
1106 }
1107
1108 return TRUE;
1109}
1110
1111/* Build a LUT entry used by the trigger functions. */
1112static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1113{
1114 int i, j, k, bit;
1115
1116 /* For each quad probe. */
1117 for (i = 0; i < 4; ++i) {
1118 entry[i] = 0xffff;
1119
1120 /* For each bit in LUT. */
1121 for (j = 0; j < 16; ++j)
1122
1123 /* For each probe in quad. */
1124 for (k = 0; k < 4; ++k) {
1125 bit = 1 << (i * 4 + k);
1126
1127 /* Set bit in entry */
1128 if ((mask & bit) &&
1129 ((!(value & bit)) !=
1130 (!(j & (1 << k)))))
1131 entry[i] &= ~(1 << j);
1132 }
1133 }
1134}
1135
1136/* Add a logical function to LUT mask. */
1137static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1138 int index, int neg, uint16_t *mask)
1139{
1140 int i, j;
1141 int x[2][2], tmp, a, b, aset, bset, rset;
1142
1143 memset(x, 0, 4 * sizeof(int));
1144
1145 /* Trigger detect condition. */
1146 switch (oper) {
1147 case OP_LEVEL:
1148 x[0][1] = 1;
1149 x[1][1] = 1;
1150 break;
1151 case OP_NOT:
1152 x[0][0] = 1;
1153 x[1][0] = 1;
1154 break;
1155 case OP_RISE:
1156 x[0][1] = 1;
1157 break;
1158 case OP_FALL:
1159 x[1][0] = 1;
1160 break;
1161 case OP_RISEFALL:
1162 x[0][1] = 1;
1163 x[1][0] = 1;
1164 break;
1165 case OP_NOTRISE:
1166 x[1][1] = 1;
1167 x[0][0] = 1;
1168 x[1][0] = 1;
1169 break;
1170 case OP_NOTFALL:
1171 x[1][1] = 1;
1172 x[0][0] = 1;
1173 x[0][1] = 1;
1174 break;
1175 case OP_NOTRISEFALL:
1176 x[1][1] = 1;
1177 x[0][0] = 1;
1178 break;
1179 }
1180
1181 /* Transpose if neg is set. */
1182 if (neg) {
1183 for (i = 0; i < 2; ++i) {
1184 for (j = 0; j < 2; ++j) {
1185 tmp = x[i][j];
1186 x[i][j] = x[1-i][1-j];
1187 x[1-i][1-j] = tmp;
1188 }
1189 }
1190 }
1191
1192 /* Update mask with function. */
1193 for (i = 0; i < 16; ++i) {
1194 a = (i >> (2 * index + 0)) & 1;
1195 b = (i >> (2 * index + 1)) & 1;
1196
1197 aset = (*mask >> i) & 1;
1198 bset = x[b][a];
1199
1200 if (func == FUNC_AND || func == FUNC_NAND)
1201 rset = aset & bset;
1202 else if (func == FUNC_OR || func == FUNC_NOR)
1203 rset = aset | bset;
1204 else if (func == FUNC_XOR || func == FUNC_NXOR)
1205 rset = aset ^ bset;
1206
1207 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1208 rset = !rset;
1209
1210 *mask &= ~(1 << i);
1211
1212 if (rset)
1213 *mask |= 1 << i;
1214 }
1215}
1216
1217/*
1218 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1219 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1220 * set at any time, but a full mask and value can be set (0/1).
1221 */
1222static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1223{
1224 int i,j;
1225 uint16_t masks[2] = { 0, 0 };
1226
1227 memset(lut, 0, sizeof(struct triggerlut));
1228
1229 /* Contant for simple triggers. */
1230 lut->m4 = 0xa000;
1231
1232 /* Value/mask trigger support. */
1233 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1234 lut->m2d);
1235
1236 /* Rise/fall trigger support. */
1237 for (i = 0, j = 0; i < 16; ++i) {
1238 if (ctx->trigger.risingmask & (1 << i) ||
1239 ctx->trigger.fallingmask & (1 << i))
1240 masks[j++] = 1 << i;
1241 }
1242
1243 build_lut_entry(masks[0], masks[0], lut->m0d);
1244 build_lut_entry(masks[1], masks[1], lut->m1d);
1245
1246 /* Add glue logic */
1247 if (masks[0] || masks[1]) {
1248 /* Transition trigger. */
1249 if (masks[0] & ctx->trigger.risingmask)
1250 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1251 if (masks[0] & ctx->trigger.fallingmask)
1252 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1253 if (masks[1] & ctx->trigger.risingmask)
1254 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1255 if (masks[1] & ctx->trigger.fallingmask)
1256 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1257 } else {
1258 /* Only value/mask trigger. */
1259 lut->m3 = 0xffff;
1260 }
1261
1262 /* Triggertype: event. */
1263 lut->params.selres = 3;
1264
1265 return SR_OK;
1266}
1267
1268static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1269 void *cb_data)
1270{
1271 struct context *ctx;
1272 struct sr_datafeed_packet *packet;
1273 struct sr_datafeed_header *header;
1274 struct sr_datafeed_meta_logic meta;
1275 struct clockselect_50 clockselect;
1276 int frac, triggerpin, ret;
1277 uint8_t triggerselect;
1278 struct triggerinout triggerinout_conf;
1279 struct triggerlut lut;
1280
1281 ctx = sdi->priv;
1282
1283 /* If the samplerate has not been set, default to 200 kHz. */
1284 if (ctx->cur_firmware == -1) {
1285 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1286 return ret;
1287 }
1288
1289 /* Enter trigger programming mode. */
1290 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1291
1292 /* 100 and 200 MHz mode. */
1293 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1294 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1295
1296 /* Find which pin to trigger on from mask. */
1297 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1298 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1299 (1 << triggerpin))
1300 break;
1301
1302 /* Set trigger pin and light LED on trigger. */
1303 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1304
1305 /* Default rising edge. */
1306 if (ctx->trigger.fallingmask)
1307 triggerselect |= 1 << 3;
1308
1309 /* All other modes. */
1310 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1311 build_basic_trigger(&lut, ctx);
1312
1313 sigma_write_trigger_lut(&lut, ctx);
1314
1315 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1316 }
1317
1318 /* Setup trigger in and out pins to default values. */
1319 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1320 triggerinout_conf.trgout_bytrigger = 1;
1321 triggerinout_conf.trgout_enable = 1;
1322
1323 sigma_write_register(WRITE_TRIGGER_OPTION,
1324 (uint8_t *) &triggerinout_conf,
1325 sizeof(struct triggerinout), ctx);
1326
1327 /* Go back to normal mode. */
1328 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1329
1330 /* Set clock select register. */
1331 if (ctx->cur_samplerate == SR_MHZ(200))
1332 /* Enable 4 probes. */
1333 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1334 else if (ctx->cur_samplerate == SR_MHZ(100))
1335 /* Enable 8 probes. */
1336 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1337 else {
1338 /*
1339 * 50 MHz mode (or fraction thereof). Any fraction down to
1340 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1341 */
1342 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1343
1344 clockselect.async = 0;
1345 clockselect.fraction = frac;
1346 clockselect.disabled_probes = 0;
1347
1348 sigma_write_register(WRITE_CLOCK_SELECT,
1349 (uint8_t *) &clockselect,
1350 sizeof(clockselect), ctx);
1351 }
1352
1353 /* Setup maximum post trigger time. */
1354 sigma_set_register(WRITE_POST_TRIGGER,
1355 (ctx->capture_ratio * 255) / 100, ctx);
1356
1357 /* Start acqusition. */
1358 gettimeofday(&ctx->start_tv, 0);
1359 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1360
1361 ctx->session_dev_id = cb_data;
1362
1363 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1364 sr_err("sigma: %s: packet malloc failed.", __func__);
1365 return SR_ERR_MALLOC;
1366 }
1367
1368 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1369 sr_err("sigma: %s: header malloc failed.", __func__);
1370 return SR_ERR_MALLOC;
1371 }
1372
1373 /* Send header packet to the session bus. */
1374 packet->type = SR_DF_HEADER;
1375 packet->payload = header;
1376 header->feed_version = 1;
1377 gettimeofday(&header->starttime, NULL);
1378 sr_session_send(ctx->session_dev_id, packet);
1379
1380 /* Send metadata about the SR_DF_LOGIC packets to come. */
1381 packet->type = SR_DF_META_LOGIC;
1382 packet->payload = &meta;
1383 meta.samplerate = ctx->cur_samplerate;
1384 meta.num_probes = ctx->num_probes;
1385 sr_session_send(ctx->session_dev_id, packet);
1386
1387 /* Add capture source. */
1388 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1389
1390 g_free(header);
1391 g_free(packet);
1392
1393 ctx->state.state = SIGMA_CAPTURE;
1394
1395 return SR_OK;
1396}
1397
1398static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1399 void *cb_data)
1400{
1401 struct context *ctx;
1402 uint8_t modestatus;
1403
1404 /* Avoid compiler warnings. */
1405 (void)cb_data;
1406
1407 if (!(ctx = sdi->priv)) {
1408 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1409 return SR_ERR_BUG;
1410 }
1411
1412 /* Stop acquisition. */
1413 sigma_set_register(WRITE_MODE, 0x11, ctx);
1414
1415 /* Set SDRAM Read Enable. */
1416 sigma_set_register(WRITE_MODE, 0x02, ctx);
1417
1418 /* Get the current position. */
1419 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1420
1421 /* Check if trigger has fired. */
1422 modestatus = sigma_get_register(READ_MODE, ctx);
1423 if (modestatus & 0x20)
1424 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1425 else
1426 ctx->state.triggerchunk = -1;
1427
1428 ctx->state.chunks_downloaded = 0;
1429
1430 ctx->state.state = SIGMA_DOWNLOAD;
1431
1432 return SR_OK;
1433}
1434
1435SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1436 .name = "asix-sigma",
1437 .longname = "ASIX SIGMA/SIGMA2",
1438 .api_version = 1,
1439 .init = hw_init,
1440 .cleanup = hw_cleanup,
1441 .scan = hw_scan,
1442 .dev_open = hw_dev_open,
1443 .dev_close = hw_dev_close,
1444 .info_get = hw_info_get,
1445 .dev_config_set = hw_dev_config_set,
1446 .dev_acquisition_start = hw_dev_acquisition_start,
1447 .dev_acquisition_stop = hw_dev_acquisition_stop,
1448 .instances = NULL,
1449};
Hardware access and backend lib