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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA Logic Analyzer Driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include <zlib.h>
31#include "sigrok.h"
32#include "sigrok-internal.h"
33#include "asix-sigma.h"
34
35#define USB_VENDOR 0xa600
36#define USB_PRODUCT 0xa000
37#define USB_DESCRIPTION "ASIX SIGMA"
38#define USB_VENDOR_NAME "ASIX"
39#define USB_MODEL_NAME "SIGMA"
40#define USB_MODEL_VERSION ""
41#define TRIGGER_TYPES "rf10"
42#define NUM_PROBES 16
43
44static GSList *dev_insts = NULL;
45
46static uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60static const char *probe_names[NUM_PROBES + 1] = {
61 "0",
62 "1",
63 "2",
64 "3",
65 "4",
66 "5",
67 "6",
68 "7",
69 "8",
70 "9",
71 "10",
72 "11",
73 "12",
74 "13",
75 "14",
76 "15",
77 NULL,
78};
79
80static struct sr_samplerates samplerates = {
81 SR_KHZ(200),
82 SR_MHZ(200),
83 SR_HZ(0),
84 supported_samplerates,
85};
86
87static int hwcaps[] = {
88 SR_HWCAP_LOGIC_ANALYZER,
89 SR_HWCAP_SAMPLERATE,
90 SR_HWCAP_CAPTURE_RATIO,
91 SR_HWCAP_PROBECONFIG,
92
93 SR_HWCAP_LIMIT_MSEC,
94 0,
95};
96
97/* Force the FPGA to reboot. */
98static uint8_t suicide[] = {
99 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
100};
101
102/* Prepare to upload firmware (FPGA specific). */
103static uint8_t init[] = {
104 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
105};
106
107/* Initialize the logic analyzer mode. */
108static uint8_t logic_mode_start[] = {
109 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
110 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
111};
112
113static const char *firmware_files[] = {
114 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
115 "asix-sigma-100.fw", /* 100 MHz */
116 "asix-sigma-200.fw", /* 200 MHz */
117 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
118 "asix-sigma-phasor.fw", /* Frequency counter */
119};
120
121static int hw_dev_acquisition_stop(int dev_index, gpointer session_data);
122
123static int sigma_read(void *buf, size_t size, struct context *ctx)
124{
125 int ret;
126
127 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
128 if (ret < 0) {
129 sr_err("sigma: ftdi_read_data failed: %s",
130 ftdi_get_error_string(&ctx->ftdic));
131 }
132
133 return ret;
134}
135
136static int sigma_write(void *buf, size_t size, struct context *ctx)
137{
138 int ret;
139
140 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
141 if (ret < 0) {
142 sr_err("sigma: ftdi_write_data failed: %s",
143 ftdi_get_error_string(&ctx->ftdic));
144 } else if ((size_t) ret != size) {
145 sr_err("sigma: ftdi_write_data did not complete write\n");
146 }
147
148 return ret;
149}
150
151static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
152 struct context *ctx)
153{
154 size_t i;
155 uint8_t buf[len + 2];
156 int idx = 0;
157
158 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
159 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
160
161 for (i = 0; i < len; ++i) {
162 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
163 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
164 }
165
166 return sigma_write(buf, idx, ctx);
167}
168
169static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
170{
171 return sigma_write_register(reg, &value, 1, ctx);
172}
173
174static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
175 struct context *ctx)
176{
177 uint8_t buf[3];
178
179 buf[0] = REG_ADDR_LOW | (reg & 0xf);
180 buf[1] = REG_ADDR_HIGH | (reg >> 4);
181 buf[2] = REG_READ_ADDR;
182
183 sigma_write(buf, sizeof(buf), ctx);
184
185 return sigma_read(data, len, ctx);
186}
187
188static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
189{
190 uint8_t value;
191
192 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
193 sr_err("sigma: sigma_get_register: 1 byte expected");
194 return 0;
195 }
196
197 return value;
198}
199
200static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
201 struct context *ctx)
202{
203 uint8_t buf[] = {
204 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
205
206 REG_READ_ADDR | NEXT_REG,
207 REG_READ_ADDR | NEXT_REG,
208 REG_READ_ADDR | NEXT_REG,
209 REG_READ_ADDR | NEXT_REG,
210 REG_READ_ADDR | NEXT_REG,
211 REG_READ_ADDR | NEXT_REG,
212 };
213 uint8_t result[6];
214
215 sigma_write(buf, sizeof(buf), ctx);
216
217 sigma_read(result, sizeof(result), ctx);
218
219 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
220 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
221
222 /* Not really sure why this must be done, but according to spec. */
223 if ((--*stoppos & 0x1ff) == 0x1ff)
224 stoppos -= 64;
225
226 if ((*--triggerpos & 0x1ff) == 0x1ff)
227 triggerpos -= 64;
228
229 return 1;
230}
231
232static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
233 uint8_t *data, struct context *ctx)
234{
235 size_t i;
236 uint8_t buf[4096];
237 int idx = 0;
238
239 /* Send the startchunk. Index start with 1. */
240 buf[0] = startchunk >> 8;
241 buf[1] = startchunk & 0xff;
242 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
243
244 /* Read the DRAM. */
245 buf[idx++] = REG_DRAM_BLOCK;
246 buf[idx++] = REG_DRAM_WAIT_ACK;
247
248 for (i = 0; i < numchunks; ++i) {
249 /* Alternate bit to copy from DRAM to cache. */
250 if (i != (numchunks - 1))
251 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
252
253 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
254
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_WAIT_ACK;
257 }
258
259 sigma_write(buf, idx, ctx);
260
261 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
262}
263
264/* Upload trigger look-up tables to Sigma. */
265static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
266{
267 int i;
268 uint8_t tmp[2];
269 uint16_t bit;
270
271 /* Transpose the table and send to Sigma. */
272 for (i = 0; i < 16; ++i) {
273 bit = 1 << i;
274
275 tmp[0] = tmp[1] = 0;
276
277 if (lut->m2d[0] & bit)
278 tmp[0] |= 0x01;
279 if (lut->m2d[1] & bit)
280 tmp[0] |= 0x02;
281 if (lut->m2d[2] & bit)
282 tmp[0] |= 0x04;
283 if (lut->m2d[3] & bit)
284 tmp[0] |= 0x08;
285
286 if (lut->m3 & bit)
287 tmp[0] |= 0x10;
288 if (lut->m3s & bit)
289 tmp[0] |= 0x20;
290 if (lut->m4 & bit)
291 tmp[0] |= 0x40;
292
293 if (lut->m0d[0] & bit)
294 tmp[1] |= 0x01;
295 if (lut->m0d[1] & bit)
296 tmp[1] |= 0x02;
297 if (lut->m0d[2] & bit)
298 tmp[1] |= 0x04;
299 if (lut->m0d[3] & bit)
300 tmp[1] |= 0x08;
301
302 if (lut->m1d[0] & bit)
303 tmp[1] |= 0x10;
304 if (lut->m1d[1] & bit)
305 tmp[1] |= 0x20;
306 if (lut->m1d[2] & bit)
307 tmp[1] |= 0x40;
308 if (lut->m1d[3] & bit)
309 tmp[1] |= 0x80;
310
311 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
312 ctx);
313 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
314 }
315
316 /* Send the parameters */
317 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
318 sizeof(lut->params), ctx);
319
320 return SR_OK;
321}
322
323/* Generate the bitbang stream for programming the FPGA. */
324static int bin2bitbang(const char *filename,
325 unsigned char **buf, size_t *buf_size)
326{
327 FILE *f;
328 long file_size;
329 unsigned long offset = 0;
330 unsigned char *p;
331 uint8_t *compressed_buf, *firmware;
332 uLongf csize, fwsize;
333 const int buffer_size = 65536;
334 size_t i;
335 int c, ret, bit, v;
336 uint32_t imm = 0x3f6df2ab;
337
338 f = g_fopen(filename, "rb");
339 if (!f) {
340 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
341 return SR_ERR;
342 }
343
344 if (-1 == fseek(f, 0, SEEK_END)) {
345 sr_err("sigma: fseek on %s failed", filename);
346 fclose(f);
347 return SR_ERR;
348 }
349
350 file_size = ftell(f);
351
352 fseek(f, 0, SEEK_SET);
353
354 if (!(compressed_buf = g_try_malloc(file_size))) {
355 sr_err("sigma: %s: compressed_buf malloc failed", __func__);
356 fclose(f);
357 return SR_ERR_MALLOC;
358 }
359
360 if (!(firmware = g_try_malloc(buffer_size))) {
361 sr_err("sigma: %s: firmware malloc failed", __func__);
362 fclose(f);
363 g_free(compressed_buf);
364 return SR_ERR_MALLOC;
365 }
366
367 csize = 0;
368 while ((c = getc(f)) != EOF) {
369 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
370 compressed_buf[csize++] = c ^ imm;
371 }
372 fclose(f);
373
374 fwsize = buffer_size;
375 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
376 if (ret < 0) {
377 g_free(compressed_buf);
378 g_free(firmware);
379 sr_err("sigma: Could not unpack Sigma firmware. "
380 "(Error %d)\n", ret);
381 return SR_ERR;
382 }
383
384 g_free(compressed_buf);
385
386 *buf_size = fwsize * 2 * 8;
387
388 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
389 if (!p) {
390 sr_err("sigma: %s: buf/p malloc failed", __func__);
391 g_free(compressed_buf);
392 g_free(firmware);
393 return SR_ERR_MALLOC;
394 }
395
396 for (i = 0; i < fwsize; ++i) {
397 for (bit = 7; bit >= 0; --bit) {
398 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
399 p[offset++] = v | 0x01;
400 p[offset++] = v;
401 }
402 }
403
404 g_free(firmware);
405
406 if (offset != *buf_size) {
407 g_free(*buf);
408 sr_err("sigma: Error reading firmware %s "
409 "offset=%ld, file_size=%ld, buf_size=%zd\n",
410 filename, offset, file_size, *buf_size);
411
412 return SR_ERR;
413 }
414
415 return SR_OK;
416}
417
418static int hw_init(const char *devinfo)
419{
420 struct sr_dev_inst *sdi;
421 struct context *ctx;
422
423 /* Avoid compiler warnings. */
424 (void)devinfo;
425
426 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
427 sr_err("sigma: %s: ctx malloc failed", __func__);
428 return 0; /* FIXME: Should be SR_ERR_MALLOC. */
429 }
430
431 ftdi_init(&ctx->ftdic);
432
433 /* Look for SIGMAs. */
434 if (ftdi_usb_open_desc(&ctx->ftdic, USB_VENDOR, USB_PRODUCT,
435 USB_DESCRIPTION, NULL) < 0)
436 goto free;
437
438 ctx->cur_samplerate = 0;
439 ctx->period_ps = 0;
440 ctx->limit_msec = 0;
441 ctx->cur_firmware = -1;
442 ctx->num_probes = 0;
443 ctx->samples_per_event = 0;
444 ctx->capture_ratio = 50;
445 ctx->use_triggers = 0;
446
447 /* Register SIGMA device. */
448 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
449 USB_MODEL_NAME, USB_MODEL_VERSION))) {
450 sr_err("sigma: %s: sdi was NULL", __func__);
451 goto free;
452 }
453
454 sdi->priv = ctx;
455
456 dev_insts = g_slist_append(dev_insts, sdi);
457
458 /* We will open the device again when we need it. */
459 ftdi_usb_close(&ctx->ftdic);
460
461 return 1;
462
463free:
464 g_free(ctx);
465 return 0;
466}
467
468static int upload_firmware(int firmware_idx, struct context *ctx)
469{
470 int ret;
471 unsigned char *buf;
472 unsigned char pins;
473 size_t buf_size;
474 unsigned char result[32];
475 char firmware_path[128];
476
477 /* Make sure it's an ASIX SIGMA. */
478 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
479 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
480 sr_err("sigma: ftdi_usb_open failed: %s",
481 ftdi_get_error_string(&ctx->ftdic));
482 return 0;
483 }
484
485 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
486 sr_err("sigma: ftdi_set_bitmode failed: %s",
487 ftdi_get_error_string(&ctx->ftdic));
488 return 0;
489 }
490
491 /* Four times the speed of sigmalogan - Works well. */
492 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
493 sr_err("sigma: ftdi_set_baudrate failed: %s",
494 ftdi_get_error_string(&ctx->ftdic));
495 return 0;
496 }
497
498 /* Force the FPGA to reboot. */
499 sigma_write(suicide, sizeof(suicide), ctx);
500 sigma_write(suicide, sizeof(suicide), ctx);
501 sigma_write(suicide, sizeof(suicide), ctx);
502 sigma_write(suicide, sizeof(suicide), ctx);
503
504 /* Prepare to upload firmware (FPGA specific). */
505 sigma_write(init, sizeof(init), ctx);
506
507 ftdi_usb_purge_buffers(&ctx->ftdic);
508
509 /* Wait until the FPGA asserts INIT_B. */
510 while (1) {
511 ret = sigma_read(result, 1, ctx);
512 if (result[0] & 0x20)
513 break;
514 }
515
516 /* Prepare firmware. */
517 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
518 firmware_files[firmware_idx]);
519
520 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
521 sr_err("sigma: An error occured while reading the firmware: %s",
522 firmware_path);
523 return ret;
524 }
525
526 /* Upload firmare. */
527 sigma_write(buf, buf_size, ctx);
528
529 g_free(buf);
530
531 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
532 sr_err("sigma: ftdi_set_bitmode failed: %s",
533 ftdi_get_error_string(&ctx->ftdic));
534 return SR_ERR;
535 }
536
537 ftdi_usb_purge_buffers(&ctx->ftdic);
538
539 /* Discard garbage. */
540 while (1 == sigma_read(&pins, 1, ctx))
541 ;
542
543 /* Initialize the logic analyzer mode. */
544 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
545
546 /* Expect a 3 byte reply. */
547 ret = sigma_read(result, 3, ctx);
548 if (ret != 3 ||
549 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
550 sr_err("sigma: Configuration failed. Invalid reply received.");
551 return SR_ERR;
552 }
553
554 ctx->cur_firmware = firmware_idx;
555
556 return SR_OK;
557}
558
559static int hw_dev_open(int dev_index)
560{
561 struct sr_dev_inst *sdi;
562 struct context *ctx;
563 int ret;
564
565 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
566 return SR_ERR;
567
568 ctx = sdi->priv;
569
570 /* Make sure it's an ASIX SIGMA. */
571 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
572 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
573
574 sr_err("sigma: ftdi_usb_open failed: %s",
575 ftdi_get_error_string(&ctx->ftdic));
576
577 return 0;
578 }
579
580 sdi->status = SR_ST_ACTIVE;
581
582 return SR_OK;
583}
584
585static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
586{
587 int i, ret;
588 struct context *ctx = sdi->priv;
589
590 for (i = 0; supported_samplerates[i]; i++) {
591 if (supported_samplerates[i] == samplerate)
592 break;
593 }
594 if (supported_samplerates[i] == 0)
595 return SR_ERR_SAMPLERATE;
596
597 if (samplerate <= SR_MHZ(50)) {
598 ret = upload_firmware(0, ctx);
599 ctx->num_probes = 16;
600 }
601 if (samplerate == SR_MHZ(100)) {
602 ret = upload_firmware(1, ctx);
603 ctx->num_probes = 8;
604 }
605 else if (samplerate == SR_MHZ(200)) {
606 ret = upload_firmware(2, ctx);
607 ctx->num_probes = 4;
608 }
609
610 ctx->cur_samplerate = samplerate;
611 ctx->period_ps = 1000000000000 / samplerate;
612 ctx->samples_per_event = 16 / ctx->num_probes;
613 ctx->state.state = SIGMA_IDLE;
614
615 sr_info("sigma: Firmware uploaded");
616
617 return ret;
618}
619
620/*
621 * In 100 and 200 MHz mode, only a single pin rising/falling can be
622 * set as trigger. In other modes, two rising/falling triggers can be set,
623 * in addition to value/mask trigger for any number of probes.
624 *
625 * The Sigma supports complex triggers using boolean expressions, but this
626 * has not been implemented yet.
627 */
628static int configure_probes(struct sr_dev_inst *sdi, GSList *probes)
629{
630 struct context *ctx = sdi->priv;
631 struct sr_probe *probe;
632 GSList *l;
633 int trigger_set = 0;
634 int probebit;
635
636 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
637
638 for (l = probes; l; l = l->next) {
639 probe = (struct sr_probe *)l->data;
640 probebit = 1 << (probe->index - 1);
641
642 if (!probe->enabled || !probe->trigger)
643 continue;
644
645 if (ctx->cur_samplerate >= SR_MHZ(100)) {
646 /* Fast trigger support. */
647 if (trigger_set) {
648 sr_err("sigma: ASIX SIGMA only supports a single "
649 "pin trigger in 100 and 200MHz mode.");
650 return SR_ERR;
651 }
652 if (probe->trigger[0] == 'f')
653 ctx->trigger.fallingmask |= probebit;
654 else if (probe->trigger[0] == 'r')
655 ctx->trigger.risingmask |= probebit;
656 else {
657 sr_err("sigma: ASIX SIGMA only supports "
658 "rising/falling trigger in 100 "
659 "and 200MHz mode.");
660 return SR_ERR;
661 }
662
663 ++trigger_set;
664 } else {
665 /* Simple trigger support (event). */
666 if (probe->trigger[0] == '1') {
667 ctx->trigger.simplevalue |= probebit;
668 ctx->trigger.simplemask |= probebit;
669 }
670 else if (probe->trigger[0] == '0') {
671 ctx->trigger.simplevalue &= ~probebit;
672 ctx->trigger.simplemask |= probebit;
673 }
674 else if (probe->trigger[0] == 'f') {
675 ctx->trigger.fallingmask |= probebit;
676 ++trigger_set;
677 }
678 else if (probe->trigger[0] == 'r') {
679 ctx->trigger.risingmask |= probebit;
680 ++trigger_set;
681 }
682
683 /*
684 * Actually, Sigma supports 2 rising/falling triggers,
685 * but they are ORed and the current trigger syntax
686 * does not permit ORed triggers.
687 */
688 if (trigger_set > 1) {
689 sr_err("sigma: ASIX SIGMA only supports 1 "
690 "rising/falling triggers.");
691 return SR_ERR;
692 }
693 }
694
695 if (trigger_set)
696 ctx->use_triggers = 1;
697 }
698
699 return SR_OK;
700}
701
702static int hw_dev_close(int dev_index)
703{
704 struct sr_dev_inst *sdi;
705 struct context *ctx;
706
707 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
708 sr_err("sigma: %s: sdi was NULL", __func__);
709 return SR_ERR; /* TODO: SR_ERR_ARG? */
710 }
711
712 if (!(ctx = sdi->priv)) {
713 sr_err("sigma: %s: sdi->priv was NULL", __func__);
714 return SR_ERR; /* TODO: SR_ERR_ARG? */
715 }
716
717 /* TODO */
718 if (sdi->status == SR_ST_ACTIVE)
719 ftdi_usb_close(&ctx->ftdic);
720
721 sdi->status = SR_ST_INACTIVE;
722
723 return SR_OK;
724}
725
726static int hw_cleanup(void)
727{
728 GSList *l;
729 struct sr_dev_inst *sdi;
730 int ret = SR_OK;
731
732 /* Properly close all devices. */
733 for (l = dev_insts; l; l = l->next) {
734 if (!(sdi = l->data)) {
735 /* Log error, but continue cleaning up the rest. */
736 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
737 ret = SR_ERR_BUG;
738 continue;
739 }
740 sr_dev_inst_free(sdi);
741 }
742 g_slist_free(dev_insts);
743 dev_insts = NULL;
744
745 return ret;
746}
747
748static void *hw_dev_info_get(int dev_index, int dev_info_id)
749{
750 struct sr_dev_inst *sdi;
751 struct context *ctx;
752 void *info = NULL;
753
754 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
755 sr_err("sigma: %s: sdi was NULL", __func__);
756 return NULL;
757 }
758
759 ctx = sdi->priv;
760
761 switch (dev_info_id) {
762 case SR_DI_INST:
763 info = sdi;
764 break;
765 case SR_DI_NUM_PROBES:
766 info = GINT_TO_POINTER(NUM_PROBES);
767 break;
768 case SR_DI_PROBE_NAMES:
769 info = probe_names;
770 break;
771 case SR_DI_SAMPLERATES:
772 info = &samplerates;
773 break;
774 case SR_DI_TRIGGER_TYPES:
775 info = (char *)TRIGGER_TYPES;
776 break;
777 case SR_DI_CUR_SAMPLERATE:
778 info = &ctx->cur_samplerate;
779 break;
780 }
781
782 return info;
783}
784
785static int hw_dev_status_get(int dev_index)
786{
787 struct sr_dev_inst *sdi;
788
789 sdi = sr_dev_inst_get(dev_insts, dev_index);
790 if (sdi)
791 return sdi->status;
792 else
793 return SR_ST_NOT_FOUND;
794}
795
796static int *hw_hwcap_get_all(void)
797{
798 return hwcaps;
799}
800
801static int hw_dev_config_set(int dev_index, int hwcap, void *value)
802{
803 struct sr_dev_inst *sdi;
804 struct context *ctx;
805 int ret;
806
807 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
808 return SR_ERR;
809
810 ctx = sdi->priv;
811
812 if (hwcap == SR_HWCAP_SAMPLERATE) {
813 ret = set_samplerate(sdi, *(uint64_t *)value);
814 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
815 ret = configure_probes(sdi, value);
816 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
817 ctx->limit_msec = *(uint64_t *)value;
818 if (ctx->limit_msec > 0)
819 ret = SR_OK;
820 else
821 ret = SR_ERR;
822 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
823 ctx->capture_ratio = *(uint64_t *)value;
824 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
825 ret = SR_ERR;
826 else
827 ret = SR_OK;
828 } else {
829 ret = SR_ERR;
830 }
831
832 return ret;
833}
834
835/* Software trigger to determine exact trigger position. */
836static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
837 struct sigma_trigger *t)
838{
839 int i;
840
841 for (i = 0; i < 8; ++i) {
842 if (i > 0)
843 last_sample = samples[i-1];
844
845 /* Simple triggers. */
846 if ((samples[i] & t->simplemask) != t->simplevalue)
847 continue;
848
849 /* Rising edge. */
850 if ((last_sample & t->risingmask) != 0 || (samples[i] &
851 t->risingmask) != t->risingmask)
852 continue;
853
854 /* Falling edge. */
855 if ((last_sample & t->fallingmask) != t->fallingmask ||
856 (samples[i] & t->fallingmask) != 0)
857 continue;
858
859 break;
860 }
861
862 /* If we did not match, return original trigger pos. */
863 return i & 0x7;
864}
865
866/*
867 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
868 * Each event is 20ns apart, and can contain multiple samples.
869 *
870 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
871 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
872 * For 50 MHz and below, events contain one sample for each channel,
873 * spread 20 ns apart.
874 */
875static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
876 uint16_t *lastsample, int triggerpos,
877 uint16_t limit_chunk, void *session_data)
878{
879 struct sr_dev_inst *sdi = session_data;
880 struct context *ctx = sdi->priv;
881 uint16_t tsdiff, ts;
882 uint16_t samples[65536 * ctx->samples_per_event];
883 struct sr_datafeed_packet packet;
884 struct sr_datafeed_logic logic;
885 int i, j, k, l, numpad, tosend;
886 size_t n = 0, sent = 0;
887 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
888 uint16_t *event;
889 uint16_t cur_sample;
890 int triggerts = -1;
891
892 /* Check if trigger is in this chunk. */
893 if (triggerpos != -1) {
894 if (ctx->cur_samplerate <= SR_MHZ(50))
895 triggerpos -= EVENTS_PER_CLUSTER - 1;
896
897 if (triggerpos < 0)
898 triggerpos = 0;
899
900 /* Find in which cluster the trigger occured. */
901 triggerts = triggerpos / 7;
902 }
903
904 /* For each ts. */
905 for (i = 0; i < 64; ++i) {
906 ts = *(uint16_t *) &buf[i * 16];
907 tsdiff = ts - *lastts;
908 *lastts = ts;
909
910 /* Decode partial chunk. */
911 if (limit_chunk && ts > limit_chunk)
912 return SR_OK;
913
914 /* Pad last sample up to current point. */
915 numpad = tsdiff * ctx->samples_per_event - clustersize;
916 if (numpad > 0) {
917 for (j = 0; j < numpad; ++j)
918 samples[j] = *lastsample;
919
920 n = numpad;
921 }
922
923 /* Send samples between previous and this timestamp to sigrok. */
924 sent = 0;
925 while (sent < n) {
926 tosend = MIN(2048, n - sent);
927
928 packet.type = SR_DF_LOGIC;
929 packet.payload = &logic;
930 logic.length = tosend * sizeof(uint16_t);
931 logic.unitsize = 2;
932 logic.data = samples + sent;
933 sr_session_bus(ctx->session_id, &packet);
934
935 sent += tosend;
936 }
937 n = 0;
938
939 event = (uint16_t *) &buf[i * 16 + 2];
940 cur_sample = 0;
941
942 /* For each event in cluster. */
943 for (j = 0; j < 7; ++j) {
944
945 /* For each sample in event. */
946 for (k = 0; k < ctx->samples_per_event; ++k) {
947 cur_sample = 0;
948
949 /* For each probe. */
950 for (l = 0; l < ctx->num_probes; ++l)
951 cur_sample |= (!!(event[j] & (1 << (l *
952 ctx->samples_per_event + k)))) << l;
953
954 samples[n++] = cur_sample;
955 }
956 }
957
958 /* Send data up to trigger point (if triggered). */
959 sent = 0;
960 if (i == triggerts) {
961 /*
962 * Trigger is not always accurate to sample because of
963 * pipeline delay. However, it always triggers before
964 * the actual event. We therefore look at the next
965 * samples to pinpoint the exact position of the trigger.
966 */
967 tosend = get_trigger_offset(samples, *lastsample,
968 &ctx->trigger);
969
970 if (tosend > 0) {
971 packet.type = SR_DF_LOGIC;
972 packet.payload = &logic;
973 logic.length = tosend * sizeof(uint16_t);
974 logic.unitsize = 2;
975 logic.data = samples;
976 sr_session_bus(ctx->session_id, &packet);
977
978 sent += tosend;
979 }
980
981 /* Only send trigger if explicitly enabled. */
982 if (ctx->use_triggers) {
983 packet.type = SR_DF_TRIGGER;
984 sr_session_bus(ctx->session_id, &packet);
985 }
986 }
987
988 /* Send rest of the chunk to sigrok. */
989 tosend = n - sent;
990
991 if (tosend > 0) {
992 packet.type = SR_DF_LOGIC;
993 packet.payload = &logic;
994 logic.length = tosend * sizeof(uint16_t);
995 logic.unitsize = 2;
996 logic.data = samples + sent;
997 sr_session_bus(ctx->session_id, &packet);
998 }
999
1000 *lastsample = samples[n - 1];
1001 }
1002
1003 return SR_OK;
1004}
1005
1006static int receive_data(int fd, int revents, void *session_data)
1007{
1008 struct sr_dev_inst *sdi = session_data;
1009 struct context *ctx = sdi->priv;
1010 struct sr_datafeed_packet packet;
1011 const int chunks_per_read = 32;
1012 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1013 int bufsz, numchunks, i, newchunks;
1014 uint64_t running_msec;
1015 struct timeval tv;
1016
1017 /* Avoid compiler warnings. */
1018 (void)fd;
1019 (void)revents;
1020
1021 numchunks = (ctx->state.stoppos + 511) / 512;
1022
1023 if (ctx->state.state == SIGMA_IDLE)
1024 return FALSE;
1025
1026 if (ctx->state.state == SIGMA_CAPTURE) {
1027 /* Check if the timer has expired, or memory is full. */
1028 gettimeofday(&tv, 0);
1029 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1030 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1031
1032 if (running_msec < ctx->limit_msec && numchunks < 32767)
1033 return FALSE;
1034
1035 hw_dev_acquisition_stop(sdi->index, session_data);
1036
1037 return FALSE;
1038 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1039 if (ctx->state.chunks_downloaded >= numchunks) {
1040 /* End of samples. */
1041 packet.type = SR_DF_END;
1042 sr_session_bus(ctx->session_id, &packet);
1043
1044 ctx->state.state = SIGMA_IDLE;
1045
1046 return TRUE;
1047 }
1048
1049 newchunks = MIN(chunks_per_read,
1050 numchunks - ctx->state.chunks_downloaded);
1051
1052 sr_info("sigma: Downloading sample data: %.0f %%",
1053 100.0 * ctx->state.chunks_downloaded / numchunks);
1054
1055 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1056 newchunks, buf, ctx);
1057 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1058 (void)bufsz;
1059
1060 /* Find first ts. */
1061 if (ctx->state.chunks_downloaded == 0) {
1062 ctx->state.lastts = *(uint16_t *) buf - 1;
1063 ctx->state.lastsample = 0;
1064 }
1065
1066 /* Decode chunks and send them to sigrok. */
1067 for (i = 0; i < newchunks; ++i) {
1068 int limit_chunk = 0;
1069
1070 /* The last chunk may potentially be only in part. */
1071 if (ctx->state.chunks_downloaded == numchunks - 1) {
1072 /* Find the last valid timestamp */
1073 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1074 }
1075
1076 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1077 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1078 &ctx->state.lastts,
1079 &ctx->state.lastsample,
1080 ctx->state.triggerpos & 0x1ff,
1081 limit_chunk, session_data);
1082 else
1083 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1084 &ctx->state.lastts,
1085 &ctx->state.lastsample,
1086 -1, limit_chunk, session_data);
1087
1088 ++ctx->state.chunks_downloaded;
1089 }
1090 }
1091
1092 return TRUE;
1093}
1094
1095/* Build a LUT entry used by the trigger functions. */
1096static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1097{
1098 int i, j, k, bit;
1099
1100 /* For each quad probe. */
1101 for (i = 0; i < 4; ++i) {
1102 entry[i] = 0xffff;
1103
1104 /* For each bit in LUT. */
1105 for (j = 0; j < 16; ++j)
1106
1107 /* For each probe in quad. */
1108 for (k = 0; k < 4; ++k) {
1109 bit = 1 << (i * 4 + k);
1110
1111 /* Set bit in entry */
1112 if ((mask & bit) &&
1113 ((!(value & bit)) !=
1114 (!(j & (1 << k)))))
1115 entry[i] &= ~(1 << j);
1116 }
1117 }
1118}
1119
1120/* Add a logical function to LUT mask. */
1121static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1122 int index, int neg, uint16_t *mask)
1123{
1124 int i, j;
1125 int x[2][2], tmp, a, b, aset, bset, rset;
1126
1127 memset(x, 0, 4 * sizeof(int));
1128
1129 /* Trigger detect condition. */
1130 switch (oper) {
1131 case OP_LEVEL:
1132 x[0][1] = 1;
1133 x[1][1] = 1;
1134 break;
1135 case OP_NOT:
1136 x[0][0] = 1;
1137 x[1][0] = 1;
1138 break;
1139 case OP_RISE:
1140 x[0][1] = 1;
1141 break;
1142 case OP_FALL:
1143 x[1][0] = 1;
1144 break;
1145 case OP_RISEFALL:
1146 x[0][1] = 1;
1147 x[1][0] = 1;
1148 break;
1149 case OP_NOTRISE:
1150 x[1][1] = 1;
1151 x[0][0] = 1;
1152 x[1][0] = 1;
1153 break;
1154 case OP_NOTFALL:
1155 x[1][1] = 1;
1156 x[0][0] = 1;
1157 x[0][1] = 1;
1158 break;
1159 case OP_NOTRISEFALL:
1160 x[1][1] = 1;
1161 x[0][0] = 1;
1162 break;
1163 }
1164
1165 /* Transpose if neg is set. */
1166 if (neg) {
1167 for (i = 0; i < 2; ++i) {
1168 for (j = 0; j < 2; ++j) {
1169 tmp = x[i][j];
1170 x[i][j] = x[1-i][1-j];
1171 x[1-i][1-j] = tmp;
1172 }
1173 }
1174 }
1175
1176 /* Update mask with function. */
1177 for (i = 0; i < 16; ++i) {
1178 a = (i >> (2 * index + 0)) & 1;
1179 b = (i >> (2 * index + 1)) & 1;
1180
1181 aset = (*mask >> i) & 1;
1182 bset = x[b][a];
1183
1184 if (func == FUNC_AND || func == FUNC_NAND)
1185 rset = aset & bset;
1186 else if (func == FUNC_OR || func == FUNC_NOR)
1187 rset = aset | bset;
1188 else if (func == FUNC_XOR || func == FUNC_NXOR)
1189 rset = aset ^ bset;
1190
1191 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1192 rset = !rset;
1193
1194 *mask &= ~(1 << i);
1195
1196 if (rset)
1197 *mask |= 1 << i;
1198 }
1199}
1200
1201/*
1202 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1203 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1204 * set at any time, but a full mask and value can be set (0/1).
1205 */
1206static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1207{
1208 int i,j;
1209 uint16_t masks[2] = { 0, 0 };
1210
1211 memset(lut, 0, sizeof(struct triggerlut));
1212
1213 /* Contant for simple triggers. */
1214 lut->m4 = 0xa000;
1215
1216 /* Value/mask trigger support. */
1217 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1218 lut->m2d);
1219
1220 /* Rise/fall trigger support. */
1221 for (i = 0, j = 0; i < 16; ++i) {
1222 if (ctx->trigger.risingmask & (1 << i) ||
1223 ctx->trigger.fallingmask & (1 << i))
1224 masks[j++] = 1 << i;
1225 }
1226
1227 build_lut_entry(masks[0], masks[0], lut->m0d);
1228 build_lut_entry(masks[1], masks[1], lut->m1d);
1229
1230 /* Add glue logic */
1231 if (masks[0] || masks[1]) {
1232 /* Transition trigger. */
1233 if (masks[0] & ctx->trigger.risingmask)
1234 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1235 if (masks[0] & ctx->trigger.fallingmask)
1236 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1237 if (masks[1] & ctx->trigger.risingmask)
1238 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1239 if (masks[1] & ctx->trigger.fallingmask)
1240 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1241 } else {
1242 /* Only value/mask trigger. */
1243 lut->m3 = 0xffff;
1244 }
1245
1246 /* Triggertype: event. */
1247 lut->params.selres = 3;
1248
1249 return SR_OK;
1250}
1251
1252static int hw_dev_acquisition_start(int dev_index, gpointer session_data)
1253{
1254 struct sr_dev_inst *sdi;
1255 struct context *ctx;
1256 struct sr_datafeed_packet packet;
1257 struct sr_datafeed_header header;
1258 struct clockselect_50 clockselect;
1259 int frac, triggerpin, ret;
1260 uint8_t triggerselect;
1261 struct triggerinout triggerinout_conf;
1262 struct triggerlut lut;
1263
1264 /* Avoid compiler warnings. */
1265 (void)session_data;
1266
1267 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
1268 return SR_ERR;
1269
1270 ctx = sdi->priv;
1271
1272 /* If the samplerate has not been set, default to 200 kHz. */
1273 if (ctx->cur_firmware == -1) {
1274 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1275 return ret;
1276 }
1277
1278 /* Enter trigger programming mode. */
1279 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1280
1281 /* 100 and 200 MHz mode. */
1282 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1283 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1284
1285 /* Find which pin to trigger on from mask. */
1286 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1287 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1288 (1 << triggerpin))
1289 break;
1290
1291 /* Set trigger pin and light LED on trigger. */
1292 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1293
1294 /* Default rising edge. */
1295 if (ctx->trigger.fallingmask)
1296 triggerselect |= 1 << 3;
1297
1298 /* All other modes. */
1299 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1300 build_basic_trigger(&lut, ctx);
1301
1302 sigma_write_trigger_lut(&lut, ctx);
1303
1304 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1305 }
1306
1307 /* Setup trigger in and out pins to default values. */
1308 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1309 triggerinout_conf.trgout_bytrigger = 1;
1310 triggerinout_conf.trgout_enable = 1;
1311
1312 sigma_write_register(WRITE_TRIGGER_OPTION,
1313 (uint8_t *) &triggerinout_conf,
1314 sizeof(struct triggerinout), ctx);
1315
1316 /* Go back to normal mode. */
1317 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1318
1319 /* Set clock select register. */
1320 if (ctx->cur_samplerate == SR_MHZ(200))
1321 /* Enable 4 probes. */
1322 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1323 else if (ctx->cur_samplerate == SR_MHZ(100))
1324 /* Enable 8 probes. */
1325 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1326 else {
1327 /*
1328 * 50 MHz mode (or fraction thereof). Any fraction down to
1329 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1330 */
1331 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1332
1333 clockselect.async = 0;
1334 clockselect.fraction = frac;
1335 clockselect.disabled_probes = 0;
1336
1337 sigma_write_register(WRITE_CLOCK_SELECT,
1338 (uint8_t *) &clockselect,
1339 sizeof(clockselect), ctx);
1340 }
1341
1342 /* Setup maximum post trigger time. */
1343 sigma_set_register(WRITE_POST_TRIGGER,
1344 (ctx->capture_ratio * 255) / 100, ctx);
1345
1346 /* Start acqusition. */
1347 gettimeofday(&ctx->start_tv, 0);
1348 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1349
1350 ctx->session_id = session_data;
1351
1352 /* Send header packet to the session bus. */
1353 packet.type = SR_DF_HEADER;
1354 packet.payload = &header;
1355 header.feed_version = 1;
1356 gettimeofday(&header.starttime, NULL);
1357 header.samplerate = ctx->cur_samplerate;
1358 header.num_logic_probes = ctx->num_probes;
1359 sr_session_bus(session_data, &packet);
1360
1361 /* Add capture source. */
1362 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1363
1364 ctx->state.state = SIGMA_CAPTURE;
1365
1366 return SR_OK;
1367}
1368
1369static int hw_dev_acquisition_stop(int dev_index, gpointer session_data)
1370{
1371 struct sr_dev_inst *sdi;
1372 struct context *ctx;
1373 uint8_t modestatus;
1374
1375 /* Avoid compiler warnings. */
1376 (void)session_data;
1377
1378 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
1379 sr_err("sigma: %s: sdi was NULL", __func__);
1380 return SR_ERR_BUG;
1381 }
1382
1383 if (!(ctx = sdi->priv)) {
1384 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1385 return SR_ERR_BUG;
1386 }
1387
1388 /* Stop acquisition. */
1389 sigma_set_register(WRITE_MODE, 0x11, ctx);
1390
1391 /* Set SDRAM Read Enable. */
1392 sigma_set_register(WRITE_MODE, 0x02, ctx);
1393
1394 /* Get the current position. */
1395 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1396
1397 /* Check if trigger has fired. */
1398 modestatus = sigma_get_register(READ_MODE, ctx);
1399 if (modestatus & 0x20)
1400 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1401 else
1402 ctx->state.triggerchunk = -1;
1403
1404 ctx->state.chunks_downloaded = 0;
1405
1406 ctx->state.state = SIGMA_DOWNLOAD;
1407
1408 return SR_OK;
1409}
1410
1411SR_PRIV struct sr_dev_plugin asix_sigma_plugin_info = {
1412 .name = "asix-sigma",
1413 .longname = "ASIX SIGMA",
1414 .api_version = 1,
1415 .init = hw_init,
1416 .cleanup = hw_cleanup,
1417 .dev_open = hw_dev_open,
1418 .dev_close = hw_dev_close,
1419 .dev_info_get = hw_dev_info_get,
1420 .dev_status_get = hw_dev_status_get,
1421 .hwcap_get_all = hw_hwcap_get_all,
1422 .dev_config_set = hw_dev_config_set,
1423 .dev_acquisition_start = hw_dev_acquisition_start,
1424 .dev_acquisition_stop = hw_dev_acquisition_stop,
1425};
Hardware access and backend lib