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sr_driver_scan(): Improve checks.
[libsigrok.git] / hardware / asix-sigma / asix-sigma.c
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPE "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *di = &asix_sigma_driver_info;
45static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46
47static const uint64_t supported_samplerates[] = {
48 SR_KHZ(200),
49 SR_KHZ(250),
50 SR_KHZ(500),
51 SR_MHZ(1),
52 SR_MHZ(5),
53 SR_MHZ(10),
54 SR_MHZ(25),
55 SR_MHZ(50),
56 SR_MHZ(100),
57 SR_MHZ(200),
58 0,
59};
60
61/*
62 * Probe numbers seem to go from 1-16, according to this image:
63 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
64 * (the cable has two additional GND pins, and a TI and TO pin)
65 */
66static const char *probe_names[NUM_PROBES + 1] = {
67 "1", "2", "3", "4", "5", "6", "7", "8",
68 "9", "10", "11", "12", "13", "14", "15", "16",
69 NULL,
70};
71
72static const struct sr_samplerates samplerates = {
73 0,
74 0,
75 0,
76 supported_samplerates,
77};
78
79static const int hwcaps[] = {
80 SR_CONF_LOGIC_ANALYZER,
81 SR_CONF_SAMPLERATE,
82 SR_CONF_CAPTURE_RATIO,
83
84 SR_CONF_LIMIT_MSEC,
85 0,
86};
87
88/* Force the FPGA to reboot. */
89static uint8_t suicide[] = {
90 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
91};
92
93/* Prepare to upload firmware (FPGA specific). */
94static uint8_t init[] = {
95 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
96};
97
98/* Initialize the logic analyzer mode. */
99static uint8_t logic_mode_start[] = {
100 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
101 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
102};
103
104static const char *firmware_files[] = {
105 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
106 "asix-sigma-100.fw", /* 100 MHz */
107 "asix-sigma-200.fw", /* 200 MHz */
108 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
109 "asix-sigma-phasor.fw", /* Frequency counter */
110};
111
112static int sigma_read(void *buf, size_t size, struct dev_context *devc)
113{
114 int ret;
115
116 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
117 if (ret < 0) {
118 sr_err("ftdi_read_data failed: %s",
119 ftdi_get_error_string(&devc->ftdic));
120 }
121
122 return ret;
123}
124
125static int sigma_write(void *buf, size_t size, struct dev_context *devc)
126{
127 int ret;
128
129 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
130 if (ret < 0) {
131 sr_err("ftdi_write_data failed: %s",
132 ftdi_get_error_string(&devc->ftdic));
133 } else if ((size_t) ret != size) {
134 sr_err("ftdi_write_data did not complete write.");
135 }
136
137 return ret;
138}
139
140static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
141 struct dev_context *devc)
142{
143 size_t i;
144 uint8_t buf[len + 2];
145 int idx = 0;
146
147 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
148 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
149
150 for (i = 0; i < len; ++i) {
151 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
152 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
153 }
154
155 return sigma_write(buf, idx, devc);
156}
157
158static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
159{
160 return sigma_write_register(reg, &value, 1, devc);
161}
162
163static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
164 struct dev_context *devc)
165{
166 uint8_t buf[3];
167
168 buf[0] = REG_ADDR_LOW | (reg & 0xf);
169 buf[1] = REG_ADDR_HIGH | (reg >> 4);
170 buf[2] = REG_READ_ADDR;
171
172 sigma_write(buf, sizeof(buf), devc);
173
174 return sigma_read(data, len, devc);
175}
176
177static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
178{
179 uint8_t value;
180
181 if (1 != sigma_read_register(reg, &value, 1, devc)) {
182 sr_err("sigma_get_register: 1 byte expected");
183 return 0;
184 }
185
186 return value;
187}
188
189static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
190 struct dev_context *devc)
191{
192 uint8_t buf[] = {
193 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
194
195 REG_READ_ADDR | NEXT_REG,
196 REG_READ_ADDR | NEXT_REG,
197 REG_READ_ADDR | NEXT_REG,
198 REG_READ_ADDR | NEXT_REG,
199 REG_READ_ADDR | NEXT_REG,
200 REG_READ_ADDR | NEXT_REG,
201 };
202 uint8_t result[6];
203
204 sigma_write(buf, sizeof(buf), devc);
205
206 sigma_read(result, sizeof(result), devc);
207
208 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
209 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
210
211 /* Not really sure why this must be done, but according to spec. */
212 if ((--*stoppos & 0x1ff) == 0x1ff)
213 stoppos -= 64;
214
215 if ((*--triggerpos & 0x1ff) == 0x1ff)
216 triggerpos -= 64;
217
218 return 1;
219}
220
221static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
222 uint8_t *data, struct dev_context *devc)
223{
224 size_t i;
225 uint8_t buf[4096];
226 int idx = 0;
227
228 /* Send the startchunk. Index start with 1. */
229 buf[0] = startchunk >> 8;
230 buf[1] = startchunk & 0xff;
231 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
232
233 /* Read the DRAM. */
234 buf[idx++] = REG_DRAM_BLOCK;
235 buf[idx++] = REG_DRAM_WAIT_ACK;
236
237 for (i = 0; i < numchunks; ++i) {
238 /* Alternate bit to copy from DRAM to cache. */
239 if (i != (numchunks - 1))
240 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
241
242 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
243
244 if (i != (numchunks - 1))
245 buf[idx++] = REG_DRAM_WAIT_ACK;
246 }
247
248 sigma_write(buf, idx, devc);
249
250 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
251}
252
253/* Upload trigger look-up tables to Sigma. */
254static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
255{
256 int i;
257 uint8_t tmp[2];
258 uint16_t bit;
259
260 /* Transpose the table and send to Sigma. */
261 for (i = 0; i < 16; ++i) {
262 bit = 1 << i;
263
264 tmp[0] = tmp[1] = 0;
265
266 if (lut->m2d[0] & bit)
267 tmp[0] |= 0x01;
268 if (lut->m2d[1] & bit)
269 tmp[0] |= 0x02;
270 if (lut->m2d[2] & bit)
271 tmp[0] |= 0x04;
272 if (lut->m2d[3] & bit)
273 tmp[0] |= 0x08;
274
275 if (lut->m3 & bit)
276 tmp[0] |= 0x10;
277 if (lut->m3s & bit)
278 tmp[0] |= 0x20;
279 if (lut->m4 & bit)
280 tmp[0] |= 0x40;
281
282 if (lut->m0d[0] & bit)
283 tmp[1] |= 0x01;
284 if (lut->m0d[1] & bit)
285 tmp[1] |= 0x02;
286 if (lut->m0d[2] & bit)
287 tmp[1] |= 0x04;
288 if (lut->m0d[3] & bit)
289 tmp[1] |= 0x08;
290
291 if (lut->m1d[0] & bit)
292 tmp[1] |= 0x10;
293 if (lut->m1d[1] & bit)
294 tmp[1] |= 0x20;
295 if (lut->m1d[2] & bit)
296 tmp[1] |= 0x40;
297 if (lut->m1d[3] & bit)
298 tmp[1] |= 0x80;
299
300 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
301 devc);
302 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
303 }
304
305 /* Send the parameters */
306 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
307 sizeof(lut->params), devc);
308
309 return SR_OK;
310}
311
312/* Generate the bitbang stream for programming the FPGA. */
313static int bin2bitbang(const char *filename,
314 unsigned char **buf, size_t *buf_size)
315{
316 FILE *f;
317 unsigned long file_size;
318 unsigned long offset = 0;
319 unsigned char *p;
320 uint8_t *firmware;
321 unsigned long fwsize = 0;
322 const int buffer_size = 65536;
323 size_t i;
324 int c, bit, v;
325 uint32_t imm = 0x3f6df2ab;
326
327 f = g_fopen(filename, "rb");
328 if (!f) {
329 sr_err("g_fopen(\"%s\", \"rb\")", filename);
330 return SR_ERR;
331 }
332
333 if (-1 == fseek(f, 0, SEEK_END)) {
334 sr_err("fseek on %s failed", filename);
335 fclose(f);
336 return SR_ERR;
337 }
338
339 file_size = ftell(f);
340
341 fseek(f, 0, SEEK_SET);
342
343 if (!(firmware = g_try_malloc(buffer_size))) {
344 sr_err("%s: firmware malloc failed", __func__);
345 fclose(f);
346 return SR_ERR_MALLOC;
347 }
348
349 while ((c = getc(f)) != EOF) {
350 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
351 firmware[fwsize++] = c ^ imm;
352 }
353 fclose(f);
354
355 if(fwsize != file_size) {
356 sr_err("%s: Error reading firmware", filename);
357 fclose(f);
358 g_free(firmware);
359 return SR_ERR;
360 }
361
362 *buf_size = fwsize * 2 * 8;
363
364 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
365 if (!p) {
366 sr_err("%s: buf/p malloc failed", __func__);
367 g_free(firmware);
368 return SR_ERR_MALLOC;
369 }
370
371 for (i = 0; i < fwsize; ++i) {
372 for (bit = 7; bit >= 0; --bit) {
373 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
374 p[offset++] = v | 0x01;
375 p[offset++] = v;
376 }
377 }
378
379 g_free(firmware);
380
381 if (offset != *buf_size) {
382 g_free(*buf);
383 sr_err("Error reading firmware %s "
384 "offset=%ld, file_size=%ld, buf_size=%zd.",
385 filename, offset, file_size, *buf_size);
386
387 return SR_ERR;
388 }
389
390 return SR_OK;
391}
392
393static int clear_instances(void)
394{
395 GSList *l;
396 struct sr_dev_inst *sdi;
397 struct drv_context *drvc;
398 struct dev_context *devc;
399
400 drvc = di->priv;
401
402 /* Properly close all devices. */
403 for (l = drvc->instances; l; l = l->next) {
404 if (!(sdi = l->data)) {
405 /* Log error, but continue cleaning up the rest. */
406 sr_err("%s: sdi was NULL, continuing", __func__);
407 continue;
408 }
409 if (sdi->priv) {
410 devc = sdi->priv;
411 ftdi_free(&devc->ftdic);
412 }
413 sr_dev_inst_free(sdi);
414 }
415 g_slist_free(drvc->instances);
416 drvc->instances = NULL;
417
418 return SR_OK;
419}
420
421static int hw_init(struct sr_context *sr_ctx)
422{
423 struct drv_context *drvc;
424
425 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
426 sr_err("Driver context malloc failed.");
427 return SR_ERR_MALLOC;
428 }
429
430 drvc->sr_ctx = sr_ctx;
431 di->priv = drvc;
432
433 return SR_OK;
434}
435
436static GSList *hw_scan(GSList *options)
437{
438 struct sr_dev_inst *sdi;
439 struct sr_probe *probe;
440 struct drv_context *drvc;
441 struct dev_context *devc;
442 GSList *devices;
443 struct ftdi_device_list *devlist;
444 char serial_txt[10];
445 uint32_t serial;
446 int ret, i;
447
448 (void)options;
449
450 drvc = di->priv;
451
452 devices = NULL;
453
454 clear_instances();
455
456 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
457 sr_err("%s: devc malloc failed", __func__);
458 return NULL;
459 }
460
461 ftdi_init(&devc->ftdic);
462
463 /* Look for SIGMAs. */
464
465 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
466 USB_VENDOR, USB_PRODUCT)) <= 0) {
467 if (ret < 0)
468 sr_err("ftdi_usb_find_all(): %d", ret);
469 goto free;
470 }
471
472 /* Make sure it's a version 1 or 2 SIGMA. */
473 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
474 serial_txt, sizeof(serial_txt));
475 sscanf(serial_txt, "%x", &serial);
476
477 if (serial < 0xa6010000 || serial > 0xa602ffff) {
478 sr_err("Only SIGMA and SIGMA2 are supported "
479 "in this version of libsigrok.");
480 goto free;
481 }
482
483 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
484
485 devc->cur_samplerate = 0;
486 devc->period_ps = 0;
487 devc->limit_msec = 0;
488 devc->cur_firmware = -1;
489 devc->num_probes = 0;
490 devc->samples_per_event = 0;
491 devc->capture_ratio = 50;
492 devc->use_triggers = 0;
493
494 /* Register SIGMA device. */
495 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
496 USB_MODEL_NAME, USB_MODEL_VERSION))) {
497 sr_err("%s: sdi was NULL", __func__);
498 goto free;
499 }
500 sdi->driver = di;
501
502 for (i = 0; probe_names[i]; i++) {
503 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
504 probe_names[i])))
505 return NULL;
506 sdi->probes = g_slist_append(sdi->probes, probe);
507 }
508
509 devices = g_slist_append(devices, sdi);
510 drvc->instances = g_slist_append(drvc->instances, sdi);
511 sdi->priv = devc;
512
513 /* We will open the device again when we need it. */
514 ftdi_list_free(&devlist);
515
516 return devices;
517
518free:
519 ftdi_deinit(&devc->ftdic);
520 g_free(devc);
521 return NULL;
522}
523
524static GSList *hw_dev_list(void)
525{
526 struct drv_context *drvc;
527
528 drvc = di->priv;
529
530 return drvc->instances;
531}
532
533static int upload_firmware(int firmware_idx, struct dev_context *devc)
534{
535 int ret;
536 unsigned char *buf;
537 unsigned char pins;
538 size_t buf_size;
539 unsigned char result[32];
540 char firmware_path[128];
541
542 /* Make sure it's an ASIX SIGMA. */
543 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
544 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
545 sr_err("ftdi_usb_open failed: %s",
546 ftdi_get_error_string(&devc->ftdic));
547 return 0;
548 }
549
550 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
551 sr_err("ftdi_set_bitmode failed: %s",
552 ftdi_get_error_string(&devc->ftdic));
553 return 0;
554 }
555
556 /* Four times the speed of sigmalogan - Works well. */
557 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
558 sr_err("ftdi_set_baudrate failed: %s",
559 ftdi_get_error_string(&devc->ftdic));
560 return 0;
561 }
562
563 /* Force the FPGA to reboot. */
564 sigma_write(suicide, sizeof(suicide), devc);
565 sigma_write(suicide, sizeof(suicide), devc);
566 sigma_write(suicide, sizeof(suicide), devc);
567 sigma_write(suicide, sizeof(suicide), devc);
568
569 /* Prepare to upload firmware (FPGA specific). */
570 sigma_write(init, sizeof(init), devc);
571
572 ftdi_usb_purge_buffers(&devc->ftdic);
573
574 /* Wait until the FPGA asserts INIT_B. */
575 while (1) {
576 ret = sigma_read(result, 1, devc);
577 if (result[0] & 0x20)
578 break;
579 }
580
581 /* Prepare firmware. */
582 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
583 firmware_files[firmware_idx]);
584
585 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
586 sr_err("An error occured while reading the firmware: %s",
587 firmware_path);
588 return ret;
589 }
590
591 /* Upload firmare. */
592 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
593 sigma_write(buf, buf_size, devc);
594
595 g_free(buf);
596
597 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
598 sr_err("ftdi_set_bitmode failed: %s",
599 ftdi_get_error_string(&devc->ftdic));
600 return SR_ERR;
601 }
602
603 ftdi_usb_purge_buffers(&devc->ftdic);
604
605 /* Discard garbage. */
606 while (1 == sigma_read(&pins, 1, devc))
607 ;
608
609 /* Initialize the logic analyzer mode. */
610 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
611
612 /* Expect a 3 byte reply. */
613 ret = sigma_read(result, 3, devc);
614 if (ret != 3 ||
615 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
616 sr_err("Configuration failed. Invalid reply received.");
617 return SR_ERR;
618 }
619
620 devc->cur_firmware = firmware_idx;
621
622 sr_info("Firmware uploaded.");
623
624 return SR_OK;
625}
626
627static int hw_dev_open(struct sr_dev_inst *sdi)
628{
629 struct dev_context *devc;
630 int ret;
631
632 devc = sdi->priv;
633
634 /* Make sure it's an ASIX SIGMA. */
635 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
636 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
637
638 sr_err("ftdi_usb_open failed: %s",
639 ftdi_get_error_string(&devc->ftdic));
640
641 return 0;
642 }
643
644 sdi->status = SR_ST_ACTIVE;
645
646 return SR_OK;
647}
648
649static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
650{
651 int i, ret;
652 struct dev_context *devc = sdi->priv;
653
654 ret = SR_OK;
655
656 for (i = 0; supported_samplerates[i]; i++) {
657 if (supported_samplerates[i] == samplerate)
658 break;
659 }
660 if (supported_samplerates[i] == 0)
661 return SR_ERR_SAMPLERATE;
662
663 if (samplerate <= SR_MHZ(50)) {
664 ret = upload_firmware(0, devc);
665 devc->num_probes = 16;
666 }
667 if (samplerate == SR_MHZ(100)) {
668 ret = upload_firmware(1, devc);
669 devc->num_probes = 8;
670 }
671 else if (samplerate == SR_MHZ(200)) {
672 ret = upload_firmware(2, devc);
673 devc->num_probes = 4;
674 }
675
676 devc->cur_samplerate = samplerate;
677 devc->period_ps = 1000000000000ULL / samplerate;
678 devc->samples_per_event = 16 / devc->num_probes;
679 devc->state.state = SIGMA_IDLE;
680
681 return ret;
682}
683
684/*
685 * In 100 and 200 MHz mode, only a single pin rising/falling can be
686 * set as trigger. In other modes, two rising/falling triggers can be set,
687 * in addition to value/mask trigger for any number of probes.
688 *
689 * The Sigma supports complex triggers using boolean expressions, but this
690 * has not been implemented yet.
691 */
692static int configure_probes(const struct sr_dev_inst *sdi)
693{
694 struct dev_context *devc = sdi->priv;
695 const struct sr_probe *probe;
696 const GSList *l;
697 int trigger_set = 0;
698 int probebit;
699
700 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
701
702 for (l = sdi->probes; l; l = l->next) {
703 probe = (struct sr_probe *)l->data;
704 probebit = 1 << (probe->index);
705
706 if (!probe->enabled || !probe->trigger)
707 continue;
708
709 if (devc->cur_samplerate >= SR_MHZ(100)) {
710 /* Fast trigger support. */
711 if (trigger_set) {
712 sr_err("Only a single pin trigger in 100 and "
713 "200MHz mode is supported.");
714 return SR_ERR;
715 }
716 if (probe->trigger[0] == 'f')
717 devc->trigger.fallingmask |= probebit;
718 else if (probe->trigger[0] == 'r')
719 devc->trigger.risingmask |= probebit;
720 else {
721 sr_err("Only rising/falling trigger in 100 "
722 "and 200MHz mode is supported.");
723 return SR_ERR;
724 }
725
726 ++trigger_set;
727 } else {
728 /* Simple trigger support (event). */
729 if (probe->trigger[0] == '1') {
730 devc->trigger.simplevalue |= probebit;
731 devc->trigger.simplemask |= probebit;
732 }
733 else if (probe->trigger[0] == '0') {
734 devc->trigger.simplevalue &= ~probebit;
735 devc->trigger.simplemask |= probebit;
736 }
737 else if (probe->trigger[0] == 'f') {
738 devc->trigger.fallingmask |= probebit;
739 ++trigger_set;
740 }
741 else if (probe->trigger[0] == 'r') {
742 devc->trigger.risingmask |= probebit;
743 ++trigger_set;
744 }
745
746 /*
747 * Actually, Sigma supports 2 rising/falling triggers,
748 * but they are ORed and the current trigger syntax
749 * does not permit ORed triggers.
750 */
751 if (trigger_set > 1) {
752 sr_err("Only 1 rising/falling trigger "
753 "is supported.");
754 return SR_ERR;
755 }
756 }
757
758 if (trigger_set)
759 devc->use_triggers = 1;
760 }
761
762 return SR_OK;
763}
764
765static int hw_dev_close(struct sr_dev_inst *sdi)
766{
767 struct dev_context *devc;
768
769 if (!(devc = sdi->priv)) {
770 sr_err("%s: sdi->priv was NULL", __func__);
771 return SR_ERR_BUG;
772 }
773
774 /* TODO */
775 if (sdi->status == SR_ST_ACTIVE)
776 ftdi_usb_close(&devc->ftdic);
777
778 sdi->status = SR_ST_INACTIVE;
779
780 return SR_OK;
781}
782
783static int hw_cleanup(void)
784{
785 if (!di->priv)
786 return SR_OK;
787
788 clear_instances();
789
790 return SR_OK;
791}
792
793static int config_get(int id, const void **data, const struct sr_dev_inst *sdi)
794{
795 struct dev_context *devc;
796
797 switch (id) {
798 case SR_CONF_SAMPLERATE:
799 if (sdi) {
800 devc = sdi->priv;
801 *data = &devc->cur_samplerate;
802 } else
803 return SR_ERR;
804 break;
805 default:
806 return SR_ERR_ARG;
807 }
808
809 return SR_OK;
810}
811
812static int config_set(int id, const void *value, const struct sr_dev_inst *sdi)
813{
814 struct dev_context *devc;
815 int ret;
816
817 devc = sdi->priv;
818
819 if (id == SR_CONF_SAMPLERATE) {
820 ret = set_samplerate(sdi, *(const uint64_t *)value);
821 } else if (id == SR_CONF_LIMIT_MSEC) {
822 devc->limit_msec = *(const uint64_t *)value;
823 if (devc->limit_msec > 0)
824 ret = SR_OK;
825 else
826 ret = SR_ERR;
827 } else if (id == SR_CONF_CAPTURE_RATIO) {
828 devc->capture_ratio = *(const uint64_t *)value;
829 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
830 ret = SR_ERR;
831 else
832 ret = SR_OK;
833 } else {
834 ret = SR_ERR;
835 }
836
837 return ret;
838}
839
840static int config_list(int key, const void **data, const struct sr_dev_inst *sdi)
841{
842
843 (void)sdi;
844
845 switch (key) {
846 case SR_CONF_DEVICE_OPTIONS:
847 *data = hwcaps;
848 break;
849 case SR_CONF_SAMPLERATE:
850 *data = &samplerates;
851 break;
852 case SR_CONF_TRIGGER_TYPE:
853 *data = (char *)TRIGGER_TYPE;
854 break;
855 default:
856 return SR_ERR_ARG;
857 }
858
859 return SR_OK;
860}
861
862/* Software trigger to determine exact trigger position. */
863static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
864 struct sigma_trigger *t)
865{
866 int i;
867
868 for (i = 0; i < 8; ++i) {
869 if (i > 0)
870 last_sample = samples[i-1];
871
872 /* Simple triggers. */
873 if ((samples[i] & t->simplemask) != t->simplevalue)
874 continue;
875
876 /* Rising edge. */
877 if ((last_sample & t->risingmask) != 0 || (samples[i] &
878 t->risingmask) != t->risingmask)
879 continue;
880
881 /* Falling edge. */
882 if ((last_sample & t->fallingmask) != t->fallingmask ||
883 (samples[i] & t->fallingmask) != 0)
884 continue;
885
886 break;
887 }
888
889 /* If we did not match, return original trigger pos. */
890 return i & 0x7;
891}
892
893/*
894 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
895 * Each event is 20ns apart, and can contain multiple samples.
896 *
897 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
898 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
899 * For 50 MHz and below, events contain one sample for each channel,
900 * spread 20 ns apart.
901 */
902static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
903 uint16_t *lastsample, int triggerpos,
904 uint16_t limit_chunk, void *cb_data)
905{
906 struct sr_dev_inst *sdi = cb_data;
907 struct dev_context *devc = sdi->priv;
908 uint16_t tsdiff, ts;
909 uint16_t samples[65536 * devc->samples_per_event];
910 struct sr_datafeed_packet packet;
911 struct sr_datafeed_logic logic;
912 int i, j, k, l, numpad, tosend;
913 size_t n = 0, sent = 0;
914 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
915 uint16_t *event;
916 uint16_t cur_sample;
917 int triggerts = -1;
918
919 /* Check if trigger is in this chunk. */
920 if (triggerpos != -1) {
921 if (devc->cur_samplerate <= SR_MHZ(50))
922 triggerpos -= EVENTS_PER_CLUSTER - 1;
923
924 if (triggerpos < 0)
925 triggerpos = 0;
926
927 /* Find in which cluster the trigger occured. */
928 triggerts = triggerpos / 7;
929 }
930
931 /* For each ts. */
932 for (i = 0; i < 64; ++i) {
933 ts = *(uint16_t *) &buf[i * 16];
934 tsdiff = ts - *lastts;
935 *lastts = ts;
936
937 /* Decode partial chunk. */
938 if (limit_chunk && ts > limit_chunk)
939 return SR_OK;
940
941 /* Pad last sample up to current point. */
942 numpad = tsdiff * devc->samples_per_event - clustersize;
943 if (numpad > 0) {
944 for (j = 0; j < numpad; ++j)
945 samples[j] = *lastsample;
946
947 n = numpad;
948 }
949
950 /* Send samples between previous and this timestamp to sigrok. */
951 sent = 0;
952 while (sent < n) {
953 tosend = MIN(2048, n - sent);
954
955 packet.type = SR_DF_LOGIC;
956 packet.payload = &logic;
957 logic.length = tosend * sizeof(uint16_t);
958 logic.unitsize = 2;
959 logic.data = samples + sent;
960 sr_session_send(devc->session_dev_id, &packet);
961
962 sent += tosend;
963 }
964 n = 0;
965
966 event = (uint16_t *) &buf[i * 16 + 2];
967 cur_sample = 0;
968
969 /* For each event in cluster. */
970 for (j = 0; j < 7; ++j) {
971
972 /* For each sample in event. */
973 for (k = 0; k < devc->samples_per_event; ++k) {
974 cur_sample = 0;
975
976 /* For each probe. */
977 for (l = 0; l < devc->num_probes; ++l)
978 cur_sample |= (!!(event[j] & (1 << (l *
979 devc->samples_per_event + k)))) << l;
980
981 samples[n++] = cur_sample;
982 }
983 }
984
985 /* Send data up to trigger point (if triggered). */
986 sent = 0;
987 if (i == triggerts) {
988 /*
989 * Trigger is not always accurate to sample because of
990 * pipeline delay. However, it always triggers before
991 * the actual event. We therefore look at the next
992 * samples to pinpoint the exact position of the trigger.
993 */
994 tosend = get_trigger_offset(samples, *lastsample,
995 &devc->trigger);
996
997 if (tosend > 0) {
998 packet.type = SR_DF_LOGIC;
999 packet.payload = &logic;
1000 logic.length = tosend * sizeof(uint16_t);
1001 logic.unitsize = 2;
1002 logic.data = samples;
1003 sr_session_send(devc->session_dev_id, &packet);
1004
1005 sent += tosend;
1006 }
1007
1008 /* Only send trigger if explicitly enabled. */
1009 if (devc->use_triggers) {
1010 packet.type = SR_DF_TRIGGER;
1011 sr_session_send(devc->session_dev_id, &packet);
1012 }
1013 }
1014
1015 /* Send rest of the chunk to sigrok. */
1016 tosend = n - sent;
1017
1018 if (tosend > 0) {
1019 packet.type = SR_DF_LOGIC;
1020 packet.payload = &logic;
1021 logic.length = tosend * sizeof(uint16_t);
1022 logic.unitsize = 2;
1023 logic.data = samples + sent;
1024 sr_session_send(devc->session_dev_id, &packet);
1025 }
1026
1027 *lastsample = samples[n - 1];
1028 }
1029
1030 return SR_OK;
1031}
1032
1033static int receive_data(int fd, int revents, void *cb_data)
1034{
1035 struct sr_dev_inst *sdi = cb_data;
1036 struct dev_context *devc = sdi->priv;
1037 struct sr_datafeed_packet packet;
1038 const int chunks_per_read = 32;
1039 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1040 int bufsz, numchunks, i, newchunks;
1041 uint64_t running_msec;
1042 struct timeval tv;
1043
1044 (void)fd;
1045 (void)revents;
1046
1047 /* Get the current position. */
1048 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1049
1050 numchunks = (devc->state.stoppos + 511) / 512;
1051
1052 if (devc->state.state == SIGMA_IDLE)
1053 return TRUE;
1054
1055 if (devc->state.state == SIGMA_CAPTURE) {
1056 /* Check if the timer has expired, or memory is full. */
1057 gettimeofday(&tv, 0);
1058 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1059 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1060
1061 if (running_msec < devc->limit_msec && numchunks < 32767)
1062 return TRUE; /* While capturing... */
1063 else
1064 hw_dev_acquisition_stop(sdi, sdi);
1065
1066 }
1067
1068 if (devc->state.state == SIGMA_DOWNLOAD) {
1069 if (devc->state.chunks_downloaded >= numchunks) {
1070 /* End of samples. */
1071 packet.type = SR_DF_END;
1072 sr_session_send(devc->session_dev_id, &packet);
1073
1074 devc->state.state = SIGMA_IDLE;
1075
1076 return TRUE;
1077 }
1078
1079 newchunks = MIN(chunks_per_read,
1080 numchunks - devc->state.chunks_downloaded);
1081
1082 sr_info("Downloading sample data: %.0f %%.",
1083 100.0 * devc->state.chunks_downloaded / numchunks);
1084
1085 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1086 newchunks, buf, devc);
1087 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1088 (void)bufsz;
1089
1090 /* Find first ts. */
1091 if (devc->state.chunks_downloaded == 0) {
1092 devc->state.lastts = *(uint16_t *) buf - 1;
1093 devc->state.lastsample = 0;
1094 }
1095
1096 /* Decode chunks and send them to sigrok. */
1097 for (i = 0; i < newchunks; ++i) {
1098 int limit_chunk = 0;
1099
1100 /* The last chunk may potentially be only in part. */
1101 if (devc->state.chunks_downloaded == numchunks - 1) {
1102 /* Find the last valid timestamp */
1103 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1104 }
1105
1106 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1107 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1108 &devc->state.lastts,
1109 &devc->state.lastsample,
1110 devc->state.triggerpos & 0x1ff,
1111 limit_chunk, sdi);
1112 else
1113 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1114 &devc->state.lastts,
1115 &devc->state.lastsample,
1116 -1, limit_chunk, sdi);
1117
1118 ++devc->state.chunks_downloaded;
1119 }
1120 }
1121
1122 return TRUE;
1123}
1124
1125/* Build a LUT entry used by the trigger functions. */
1126static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1127{
1128 int i, j, k, bit;
1129
1130 /* For each quad probe. */
1131 for (i = 0; i < 4; ++i) {
1132 entry[i] = 0xffff;
1133
1134 /* For each bit in LUT. */
1135 for (j = 0; j < 16; ++j)
1136
1137 /* For each probe in quad. */
1138 for (k = 0; k < 4; ++k) {
1139 bit = 1 << (i * 4 + k);
1140
1141 /* Set bit in entry */
1142 if ((mask & bit) &&
1143 ((!(value & bit)) !=
1144 (!(j & (1 << k)))))
1145 entry[i] &= ~(1 << j);
1146 }
1147 }
1148}
1149
1150/* Add a logical function to LUT mask. */
1151static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1152 int index, int neg, uint16_t *mask)
1153{
1154 int i, j;
1155 int x[2][2], tmp, a, b, aset, bset, rset;
1156
1157 memset(x, 0, 4 * sizeof(int));
1158
1159 /* Trigger detect condition. */
1160 switch (oper) {
1161 case OP_LEVEL:
1162 x[0][1] = 1;
1163 x[1][1] = 1;
1164 break;
1165 case OP_NOT:
1166 x[0][0] = 1;
1167 x[1][0] = 1;
1168 break;
1169 case OP_RISE:
1170 x[0][1] = 1;
1171 break;
1172 case OP_FALL:
1173 x[1][0] = 1;
1174 break;
1175 case OP_RISEFALL:
1176 x[0][1] = 1;
1177 x[1][0] = 1;
1178 break;
1179 case OP_NOTRISE:
1180 x[1][1] = 1;
1181 x[0][0] = 1;
1182 x[1][0] = 1;
1183 break;
1184 case OP_NOTFALL:
1185 x[1][1] = 1;
1186 x[0][0] = 1;
1187 x[0][1] = 1;
1188 break;
1189 case OP_NOTRISEFALL:
1190 x[1][1] = 1;
1191 x[0][0] = 1;
1192 break;
1193 }
1194
1195 /* Transpose if neg is set. */
1196 if (neg) {
1197 for (i = 0; i < 2; ++i) {
1198 for (j = 0; j < 2; ++j) {
1199 tmp = x[i][j];
1200 x[i][j] = x[1-i][1-j];
1201 x[1-i][1-j] = tmp;
1202 }
1203 }
1204 }
1205
1206 /* Update mask with function. */
1207 for (i = 0; i < 16; ++i) {
1208 a = (i >> (2 * index + 0)) & 1;
1209 b = (i >> (2 * index + 1)) & 1;
1210
1211 aset = (*mask >> i) & 1;
1212 bset = x[b][a];
1213
1214 if (func == FUNC_AND || func == FUNC_NAND)
1215 rset = aset & bset;
1216 else if (func == FUNC_OR || func == FUNC_NOR)
1217 rset = aset | bset;
1218 else if (func == FUNC_XOR || func == FUNC_NXOR)
1219 rset = aset ^ bset;
1220
1221 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1222 rset = !rset;
1223
1224 *mask &= ~(1 << i);
1225
1226 if (rset)
1227 *mask |= 1 << i;
1228 }
1229}
1230
1231/*
1232 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1233 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1234 * set at any time, but a full mask and value can be set (0/1).
1235 */
1236static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1237{
1238 int i,j;
1239 uint16_t masks[2] = { 0, 0 };
1240
1241 memset(lut, 0, sizeof(struct triggerlut));
1242
1243 /* Contant for simple triggers. */
1244 lut->m4 = 0xa000;
1245
1246 /* Value/mask trigger support. */
1247 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1248 lut->m2d);
1249
1250 /* Rise/fall trigger support. */
1251 for (i = 0, j = 0; i < 16; ++i) {
1252 if (devc->trigger.risingmask & (1 << i) ||
1253 devc->trigger.fallingmask & (1 << i))
1254 masks[j++] = 1 << i;
1255 }
1256
1257 build_lut_entry(masks[0], masks[0], lut->m0d);
1258 build_lut_entry(masks[1], masks[1], lut->m1d);
1259
1260 /* Add glue logic */
1261 if (masks[0] || masks[1]) {
1262 /* Transition trigger. */
1263 if (masks[0] & devc->trigger.risingmask)
1264 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1265 if (masks[0] & devc->trigger.fallingmask)
1266 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1267 if (masks[1] & devc->trigger.risingmask)
1268 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1269 if (masks[1] & devc->trigger.fallingmask)
1270 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1271 } else {
1272 /* Only value/mask trigger. */
1273 lut->m3 = 0xffff;
1274 }
1275
1276 /* Triggertype: event. */
1277 lut->params.selres = 3;
1278
1279 return SR_OK;
1280}
1281
1282static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1283 void *cb_data)
1284{
1285 struct dev_context *devc;
1286 struct sr_datafeed_packet *packet;
1287 struct sr_datafeed_header *header;
1288 struct clockselect_50 clockselect;
1289 int frac, triggerpin, ret;
1290 uint8_t triggerselect = 0;
1291 struct triggerinout triggerinout_conf;
1292 struct triggerlut lut;
1293
1294 devc = sdi->priv;
1295
1296 if (configure_probes(sdi) != SR_OK) {
1297 sr_err("Failed to configure probes.");
1298 return SR_ERR;
1299 }
1300
1301 /* If the samplerate has not been set, default to 200 kHz. */
1302 if (devc->cur_firmware == -1) {
1303 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1304 return ret;
1305 }
1306
1307 /* Enter trigger programming mode. */
1308 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1309
1310 /* 100 and 200 MHz mode. */
1311 if (devc->cur_samplerate >= SR_MHZ(100)) {
1312 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1313
1314 /* Find which pin to trigger on from mask. */
1315 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1316 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1317 (1 << triggerpin))
1318 break;
1319
1320 /* Set trigger pin and light LED on trigger. */
1321 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1322
1323 /* Default rising edge. */
1324 if (devc->trigger.fallingmask)
1325 triggerselect |= 1 << 3;
1326
1327 /* All other modes. */
1328 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1329 build_basic_trigger(&lut, devc);
1330
1331 sigma_write_trigger_lut(&lut, devc);
1332
1333 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1334 }
1335
1336 /* Setup trigger in and out pins to default values. */
1337 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1338 triggerinout_conf.trgout_bytrigger = 1;
1339 triggerinout_conf.trgout_enable = 1;
1340
1341 sigma_write_register(WRITE_TRIGGER_OPTION,
1342 (uint8_t *) &triggerinout_conf,
1343 sizeof(struct triggerinout), devc);
1344
1345 /* Go back to normal mode. */
1346 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1347
1348 /* Set clock select register. */
1349 if (devc->cur_samplerate == SR_MHZ(200))
1350 /* Enable 4 probes. */
1351 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1352 else if (devc->cur_samplerate == SR_MHZ(100))
1353 /* Enable 8 probes. */
1354 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1355 else {
1356 /*
1357 * 50 MHz mode (or fraction thereof). Any fraction down to
1358 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1359 */
1360 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1361
1362 clockselect.async = 0;
1363 clockselect.fraction = frac;
1364 clockselect.disabled_probes = 0;
1365
1366 sigma_write_register(WRITE_CLOCK_SELECT,
1367 (uint8_t *) &clockselect,
1368 sizeof(clockselect), devc);
1369 }
1370
1371 /* Setup maximum post trigger time. */
1372 sigma_set_register(WRITE_POST_TRIGGER,
1373 (devc->capture_ratio * 255) / 100, devc);
1374
1375 /* Start acqusition. */
1376 gettimeofday(&devc->start_tv, 0);
1377 sigma_set_register(WRITE_MODE, 0x0d, devc);
1378
1379 devc->session_dev_id = cb_data;
1380
1381 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1382 sr_err("%s: packet malloc failed.", __func__);
1383 return SR_ERR_MALLOC;
1384 }
1385
1386 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1387 sr_err("%s: header malloc failed.", __func__);
1388 return SR_ERR_MALLOC;
1389 }
1390
1391 /* Send header packet to the session bus. */
1392 packet->type = SR_DF_HEADER;
1393 packet->payload = header;
1394 header->feed_version = 1;
1395 gettimeofday(&header->starttime, NULL);
1396 sr_session_send(devc->session_dev_id, packet);
1397
1398 /* Add capture source. */
1399 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1400
1401 g_free(header);
1402 g_free(packet);
1403
1404 devc->state.state = SIGMA_CAPTURE;
1405
1406 return SR_OK;
1407}
1408
1409static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1410{
1411 struct dev_context *devc;
1412 uint8_t modestatus;
1413
1414 (void)cb_data;
1415
1416 sr_source_remove(0);
1417
1418 if (!(devc = sdi->priv)) {
1419 sr_err("%s: sdi->priv was NULL", __func__);
1420 return SR_ERR_BUG;
1421 }
1422
1423 /* Stop acquisition. */
1424 sigma_set_register(WRITE_MODE, 0x11, devc);
1425
1426 /* Set SDRAM Read Enable. */
1427 sigma_set_register(WRITE_MODE, 0x02, devc);
1428
1429 /* Get the current position. */
1430 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1431
1432 /* Check if trigger has fired. */
1433 modestatus = sigma_get_register(READ_MODE, devc);
1434 if (modestatus & 0x20)
1435 devc->state.triggerchunk = devc->state.triggerpos / 512;
1436 else
1437 devc->state.triggerchunk = -1;
1438
1439 devc->state.chunks_downloaded = 0;
1440
1441 devc->state.state = SIGMA_DOWNLOAD;
1442
1443 return SR_OK;
1444}
1445
1446SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1447 .name = "asix-sigma",
1448 .longname = "ASIX SIGMA/SIGMA2",
1449 .api_version = 1,
1450 .init = hw_init,
1451 .cleanup = hw_cleanup,
1452 .scan = hw_scan,
1453 .dev_list = hw_dev_list,
1454 .dev_clear = clear_instances,
1455 .config_get = config_get,
1456 .config_set = config_set,
1457 .config_list = config_list,
1458 .dev_open = hw_dev_open,
1459 .dev_close = hw_dev_close,
1460 .dev_acquisition_start = hw_dev_acquisition_start,
1461 .dev_acquisition_stop = hw_dev_acquisition_stop,
1462 .priv = NULL,
1463};
Hardware access and backend lib