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Add a struct sr_context * parameter to sr_driver_init()
[libsigrok.git] / hardware / asix-sigma / asix-sigma.c
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46
47static const uint64_t supported_samplerates[] = {
48 SR_KHZ(200),
49 SR_KHZ(250),
50 SR_KHZ(500),
51 SR_MHZ(1),
52 SR_MHZ(5),
53 SR_MHZ(10),
54 SR_MHZ(25),
55 SR_MHZ(50),
56 SR_MHZ(100),
57 SR_MHZ(200),
58 0,
59};
60
61/*
62 * Probe numbers seem to go from 1-16, according to this image:
63 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
64 * (the cable has two additional GND pins, and a TI and TO pin)
65 */
66static const char *probe_names[NUM_PROBES + 1] = {
67 "1",
68 "2",
69 "3",
70 "4",
71 "5",
72 "6",
73 "7",
74 "8",
75 "9",
76 "10",
77 "11",
78 "12",
79 "13",
80 "14",
81 "15",
82 "16",
83 NULL,
84};
85
86static const struct sr_samplerates samplerates = {
87 0,
88 0,
89 0,
90 supported_samplerates,
91};
92
93static const int hwcaps[] = {
94 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_SAMPLERATE,
96 SR_HWCAP_CAPTURE_RATIO,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int sigma_read(void *buf, size_t size, struct dev_context *devc)
127{
128 int ret;
129
130 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
131 if (ret < 0) {
132 sr_err("ftdi_read_data failed: %s",
133 ftdi_get_error_string(&devc->ftdic));
134 }
135
136 return ret;
137}
138
139static int sigma_write(void *buf, size_t size, struct dev_context *devc)
140{
141 int ret;
142
143 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
144 if (ret < 0) {
145 sr_err("ftdi_write_data failed: %s",
146 ftdi_get_error_string(&devc->ftdic));
147 } else if ((size_t) ret != size) {
148 sr_err("ftdi_write_data did not complete write.");
149 }
150
151 return ret;
152}
153
154static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
155 struct dev_context *devc)
156{
157 size_t i;
158 uint8_t buf[len + 2];
159 int idx = 0;
160
161 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
162 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
163
164 for (i = 0; i < len; ++i) {
165 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
166 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
167 }
168
169 return sigma_write(buf, idx, devc);
170}
171
172static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
173{
174 return sigma_write_register(reg, &value, 1, devc);
175}
176
177static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
178 struct dev_context *devc)
179{
180 uint8_t buf[3];
181
182 buf[0] = REG_ADDR_LOW | (reg & 0xf);
183 buf[1] = REG_ADDR_HIGH | (reg >> 4);
184 buf[2] = REG_READ_ADDR;
185
186 sigma_write(buf, sizeof(buf), devc);
187
188 return sigma_read(data, len, devc);
189}
190
191static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
192{
193 uint8_t value;
194
195 if (1 != sigma_read_register(reg, &value, 1, devc)) {
196 sr_err("sigma_get_register: 1 byte expected");
197 return 0;
198 }
199
200 return value;
201}
202
203static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
204 struct dev_context *devc)
205{
206 uint8_t buf[] = {
207 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
208
209 REG_READ_ADDR | NEXT_REG,
210 REG_READ_ADDR | NEXT_REG,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 };
216 uint8_t result[6];
217
218 sigma_write(buf, sizeof(buf), devc);
219
220 sigma_read(result, sizeof(result), devc);
221
222 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
223 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
224
225 /* Not really sure why this must be done, but according to spec. */
226 if ((--*stoppos & 0x1ff) == 0x1ff)
227 stoppos -= 64;
228
229 if ((*--triggerpos & 0x1ff) == 0x1ff)
230 triggerpos -= 64;
231
232 return 1;
233}
234
235static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
236 uint8_t *data, struct dev_context *devc)
237{
238 size_t i;
239 uint8_t buf[4096];
240 int idx = 0;
241
242 /* Send the startchunk. Index start with 1. */
243 buf[0] = startchunk >> 8;
244 buf[1] = startchunk & 0xff;
245 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
246
247 /* Read the DRAM. */
248 buf[idx++] = REG_DRAM_BLOCK;
249 buf[idx++] = REG_DRAM_WAIT_ACK;
250
251 for (i = 0; i < numchunks; ++i) {
252 /* Alternate bit to copy from DRAM to cache. */
253 if (i != (numchunks - 1))
254 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
255
256 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
257
258 if (i != (numchunks - 1))
259 buf[idx++] = REG_DRAM_WAIT_ACK;
260 }
261
262 sigma_write(buf, idx, devc);
263
264 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
265}
266
267/* Upload trigger look-up tables to Sigma. */
268static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
269{
270 int i;
271 uint8_t tmp[2];
272 uint16_t bit;
273
274 /* Transpose the table and send to Sigma. */
275 for (i = 0; i < 16; ++i) {
276 bit = 1 << i;
277
278 tmp[0] = tmp[1] = 0;
279
280 if (lut->m2d[0] & bit)
281 tmp[0] |= 0x01;
282 if (lut->m2d[1] & bit)
283 tmp[0] |= 0x02;
284 if (lut->m2d[2] & bit)
285 tmp[0] |= 0x04;
286 if (lut->m2d[3] & bit)
287 tmp[0] |= 0x08;
288
289 if (lut->m3 & bit)
290 tmp[0] |= 0x10;
291 if (lut->m3s & bit)
292 tmp[0] |= 0x20;
293 if (lut->m4 & bit)
294 tmp[0] |= 0x40;
295
296 if (lut->m0d[0] & bit)
297 tmp[1] |= 0x01;
298 if (lut->m0d[1] & bit)
299 tmp[1] |= 0x02;
300 if (lut->m0d[2] & bit)
301 tmp[1] |= 0x04;
302 if (lut->m0d[3] & bit)
303 tmp[1] |= 0x08;
304
305 if (lut->m1d[0] & bit)
306 tmp[1] |= 0x10;
307 if (lut->m1d[1] & bit)
308 tmp[1] |= 0x20;
309 if (lut->m1d[2] & bit)
310 tmp[1] |= 0x40;
311 if (lut->m1d[3] & bit)
312 tmp[1] |= 0x80;
313
314 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
315 devc);
316 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
317 }
318
319 /* Send the parameters */
320 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
321 sizeof(lut->params), devc);
322
323 return SR_OK;
324}
325
326/* Generate the bitbang stream for programming the FPGA. */
327static int bin2bitbang(const char *filename,
328 unsigned char **buf, size_t *buf_size)
329{
330 FILE *f;
331 unsigned long file_size;
332 unsigned long offset = 0;
333 unsigned char *p;
334 uint8_t *firmware;
335 unsigned long fwsize = 0;
336 const int buffer_size = 65536;
337 size_t i;
338 int c, bit, v;
339 uint32_t imm = 0x3f6df2ab;
340
341 f = g_fopen(filename, "rb");
342 if (!f) {
343 sr_err("g_fopen(\"%s\", \"rb\")", filename);
344 return SR_ERR;
345 }
346
347 if (-1 == fseek(f, 0, SEEK_END)) {
348 sr_err("fseek on %s failed", filename);
349 fclose(f);
350 return SR_ERR;
351 }
352
353 file_size = ftell(f);
354
355 fseek(f, 0, SEEK_SET);
356
357 if (!(firmware = g_try_malloc(buffer_size))) {
358 sr_err("%s: firmware malloc failed", __func__);
359 fclose(f);
360 return SR_ERR_MALLOC;
361 }
362
363 while ((c = getc(f)) != EOF) {
364 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
365 firmware[fwsize++] = c ^ imm;
366 }
367 fclose(f);
368
369 if(fwsize != file_size) {
370 sr_err("%s: Error reading firmware", filename);
371 fclose(f);
372 g_free(firmware);
373 return SR_ERR;
374 }
375
376 *buf_size = fwsize * 2 * 8;
377
378 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
379 if (!p) {
380 sr_err("%s: buf/p malloc failed", __func__);
381 g_free(firmware);
382 return SR_ERR_MALLOC;
383 }
384
385 for (i = 0; i < fwsize; ++i) {
386 for (bit = 7; bit >= 0; --bit) {
387 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
388 p[offset++] = v | 0x01;
389 p[offset++] = v;
390 }
391 }
392
393 g_free(firmware);
394
395 if (offset != *buf_size) {
396 g_free(*buf);
397 sr_err("Error reading firmware %s "
398 "offset=%ld, file_size=%ld, buf_size=%zd.",
399 filename, offset, file_size, *buf_size);
400
401 return SR_ERR;
402 }
403
404 return SR_OK;
405}
406
407static int clear_instances(void)
408{
409 GSList *l;
410 struct sr_dev_inst *sdi;
411 struct drv_context *drvc;
412 struct dev_context *devc;
413
414 drvc = adi->priv;
415
416 /* Properly close all devices. */
417 for (l = drvc->instances; l; l = l->next) {
418 if (!(sdi = l->data)) {
419 /* Log error, but continue cleaning up the rest. */
420 sr_err("%s: sdi was NULL, continuing", __func__);
421 continue;
422 }
423 if (sdi->priv) {
424 devc = sdi->priv;
425 ftdi_free(&devc->ftdic);
426 }
427 sr_dev_inst_free(sdi);
428 }
429 g_slist_free(drvc->instances);
430 drvc->instances = NULL;
431
432 return SR_OK;
433}
434
435static int hw_init(void)
436{
437 struct drv_context *drvc;
438
439 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
440 sr_err("Driver context malloc failed.");
441 return SR_ERR_MALLOC;
442 }
443 adi->priv = drvc;
444
445 return SR_OK;
446}
447
448static GSList *hw_scan(GSList *options)
449{
450 struct sr_dev_inst *sdi;
451 struct sr_probe *probe;
452 struct drv_context *drvc;
453 struct dev_context *devc;
454 GSList *devices;
455 struct ftdi_device_list *devlist;
456 char serial_txt[10];
457 uint32_t serial;
458 int ret, i;
459
460 (void)options;
461
462 drvc = adi->priv;
463 devices = NULL;
464 clear_instances();
465
466 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
467 sr_err("%s: devc malloc failed", __func__);
468 return NULL;
469 }
470
471 ftdi_init(&devc->ftdic);
472
473 /* Look for SIGMAs. */
474
475 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
476 USB_VENDOR, USB_PRODUCT)) <= 0) {
477 if (ret < 0)
478 sr_err("ftdi_usb_find_all(): %d", ret);
479 goto free;
480 }
481
482 /* Make sure it's a version 1 or 2 SIGMA. */
483 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
484 serial_txt, sizeof(serial_txt));
485 sscanf(serial_txt, "%x", &serial);
486
487 if (serial < 0xa6010000 || serial > 0xa602ffff) {
488 sr_err("Only SIGMA and SIGMA2 are supported "
489 "in this version of libsigrok.");
490 goto free;
491 }
492
493 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
494
495 devc->cur_samplerate = 0;
496 devc->period_ps = 0;
497 devc->limit_msec = 0;
498 devc->cur_firmware = -1;
499 devc->num_probes = 0;
500 devc->samples_per_event = 0;
501 devc->capture_ratio = 50;
502 devc->use_triggers = 0;
503
504 /* Register SIGMA device. */
505 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
506 USB_MODEL_NAME, USB_MODEL_VERSION))) {
507 sr_err("%s: sdi was NULL", __func__);
508 goto free;
509 }
510 sdi->driver = adi;
511
512 for (i = 0; probe_names[i]; i++) {
513 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
514 probe_names[i])))
515 return NULL;
516 sdi->probes = g_slist_append(sdi->probes, probe);
517 }
518
519 devices = g_slist_append(devices, sdi);
520 drvc->instances = g_slist_append(drvc->instances, sdi);
521 sdi->priv = devc;
522
523 /* We will open the device again when we need it. */
524 ftdi_list_free(&devlist);
525
526 return devices;
527
528free:
529 ftdi_deinit(&devc->ftdic);
530 g_free(devc);
531 return NULL;
532}
533
534static GSList *hw_dev_list(void)
535{
536 struct drv_context *drvc;
537
538 drvc = adi->priv;
539
540 return drvc->instances;
541}
542
543static int upload_firmware(int firmware_idx, struct dev_context *devc)
544{
545 int ret;
546 unsigned char *buf;
547 unsigned char pins;
548 size_t buf_size;
549 unsigned char result[32];
550 char firmware_path[128];
551
552 /* Make sure it's an ASIX SIGMA. */
553 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
554 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
555 sr_err("ftdi_usb_open failed: %s",
556 ftdi_get_error_string(&devc->ftdic));
557 return 0;
558 }
559
560 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
561 sr_err("ftdi_set_bitmode failed: %s",
562 ftdi_get_error_string(&devc->ftdic));
563 return 0;
564 }
565
566 /* Four times the speed of sigmalogan - Works well. */
567 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
568 sr_err("ftdi_set_baudrate failed: %s",
569 ftdi_get_error_string(&devc->ftdic));
570 return 0;
571 }
572
573 /* Force the FPGA to reboot. */
574 sigma_write(suicide, sizeof(suicide), devc);
575 sigma_write(suicide, sizeof(suicide), devc);
576 sigma_write(suicide, sizeof(suicide), devc);
577 sigma_write(suicide, sizeof(suicide), devc);
578
579 /* Prepare to upload firmware (FPGA specific). */
580 sigma_write(init, sizeof(init), devc);
581
582 ftdi_usb_purge_buffers(&devc->ftdic);
583
584 /* Wait until the FPGA asserts INIT_B. */
585 while (1) {
586 ret = sigma_read(result, 1, devc);
587 if (result[0] & 0x20)
588 break;
589 }
590
591 /* Prepare firmware. */
592 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
593 firmware_files[firmware_idx]);
594
595 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
596 sr_err("An error occured while reading the firmware: %s",
597 firmware_path);
598 return ret;
599 }
600
601 /* Upload firmare. */
602 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
603 sigma_write(buf, buf_size, devc);
604
605 g_free(buf);
606
607 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
608 sr_err("ftdi_set_bitmode failed: %s",
609 ftdi_get_error_string(&devc->ftdic));
610 return SR_ERR;
611 }
612
613 ftdi_usb_purge_buffers(&devc->ftdic);
614
615 /* Discard garbage. */
616 while (1 == sigma_read(&pins, 1, devc))
617 ;
618
619 /* Initialize the logic analyzer mode. */
620 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
621
622 /* Expect a 3 byte reply. */
623 ret = sigma_read(result, 3, devc);
624 if (ret != 3 ||
625 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
626 sr_err("Configuration failed. Invalid reply received.");
627 return SR_ERR;
628 }
629
630 devc->cur_firmware = firmware_idx;
631
632 sr_info("Firmware uploaded.");
633
634 return SR_OK;
635}
636
637static int hw_dev_open(struct sr_dev_inst *sdi)
638{
639 struct dev_context *devc;
640 int ret;
641
642 devc = sdi->priv;
643
644 /* Make sure it's an ASIX SIGMA. */
645 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
646 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
647
648 sr_err("ftdi_usb_open failed: %s",
649 ftdi_get_error_string(&devc->ftdic));
650
651 return 0;
652 }
653
654 sdi->status = SR_ST_ACTIVE;
655
656 return SR_OK;
657}
658
659static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
660{
661 int i, ret;
662 struct dev_context *devc = sdi->priv;
663
664 for (i = 0; supported_samplerates[i]; i++) {
665 if (supported_samplerates[i] == samplerate)
666 break;
667 }
668 if (supported_samplerates[i] == 0)
669 return SR_ERR_SAMPLERATE;
670
671 if (samplerate <= SR_MHZ(50)) {
672 ret = upload_firmware(0, devc);
673 devc->num_probes = 16;
674 }
675 if (samplerate == SR_MHZ(100)) {
676 ret = upload_firmware(1, devc);
677 devc->num_probes = 8;
678 }
679 else if (samplerate == SR_MHZ(200)) {
680 ret = upload_firmware(2, devc);
681 devc->num_probes = 4;
682 }
683
684 devc->cur_samplerate = samplerate;
685 devc->period_ps = 1000000000000 / samplerate;
686 devc->samples_per_event = 16 / devc->num_probes;
687 devc->state.state = SIGMA_IDLE;
688
689 return ret;
690}
691
692/*
693 * In 100 and 200 MHz mode, only a single pin rising/falling can be
694 * set as trigger. In other modes, two rising/falling triggers can be set,
695 * in addition to value/mask trigger for any number of probes.
696 *
697 * The Sigma supports complex triggers using boolean expressions, but this
698 * has not been implemented yet.
699 */
700static int configure_probes(const struct sr_dev_inst *sdi)
701{
702 struct dev_context *devc = sdi->priv;
703 const struct sr_probe *probe;
704 const GSList *l;
705 int trigger_set = 0;
706 int probebit;
707
708 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
709
710 for (l = sdi->probes; l; l = l->next) {
711 probe = (struct sr_probe *)l->data;
712 probebit = 1 << (probe->index);
713
714 if (!probe->enabled || !probe->trigger)
715 continue;
716
717 if (devc->cur_samplerate >= SR_MHZ(100)) {
718 /* Fast trigger support. */
719 if (trigger_set) {
720 sr_err("Only a single pin trigger in 100 and "
721 "200MHz mode is supported.");
722 return SR_ERR;
723 }
724 if (probe->trigger[0] == 'f')
725 devc->trigger.fallingmask |= probebit;
726 else if (probe->trigger[0] == 'r')
727 devc->trigger.risingmask |= probebit;
728 else {
729 sr_err("Only rising/falling trigger in 100 "
730 "and 200MHz mode is supported.");
731 return SR_ERR;
732 }
733
734 ++trigger_set;
735 } else {
736 /* Simple trigger support (event). */
737 if (probe->trigger[0] == '1') {
738 devc->trigger.simplevalue |= probebit;
739 devc->trigger.simplemask |= probebit;
740 }
741 else if (probe->trigger[0] == '0') {
742 devc->trigger.simplevalue &= ~probebit;
743 devc->trigger.simplemask |= probebit;
744 }
745 else if (probe->trigger[0] == 'f') {
746 devc->trigger.fallingmask |= probebit;
747 ++trigger_set;
748 }
749 else if (probe->trigger[0] == 'r') {
750 devc->trigger.risingmask |= probebit;
751 ++trigger_set;
752 }
753
754 /*
755 * Actually, Sigma supports 2 rising/falling triggers,
756 * but they are ORed and the current trigger syntax
757 * does not permit ORed triggers.
758 */
759 if (trigger_set > 1) {
760 sr_err("Only 1 rising/falling trigger "
761 "is supported.");
762 return SR_ERR;
763 }
764 }
765
766 if (trigger_set)
767 devc->use_triggers = 1;
768 }
769
770 return SR_OK;
771}
772
773static int hw_dev_close(struct sr_dev_inst *sdi)
774{
775 struct dev_context *devc;
776
777 if (!(devc = sdi->priv)) {
778 sr_err("%s: sdi->priv was NULL", __func__);
779 return SR_ERR_BUG;
780 }
781
782 /* TODO */
783 if (sdi->status == SR_ST_ACTIVE)
784 ftdi_usb_close(&devc->ftdic);
785
786 sdi->status = SR_ST_INACTIVE;
787
788 return SR_OK;
789}
790
791static int hw_cleanup(void)
792{
793 if (!adi->priv)
794 return SR_OK;
795
796 clear_instances();
797
798 return SR_OK;
799}
800
801static int hw_info_get(int info_id, const void **data,
802 const struct sr_dev_inst *sdi)
803{
804 struct dev_context *devc;
805
806 switch (info_id) {
807 case SR_DI_HWCAPS:
808 *data = hwcaps;
809 break;
810 case SR_DI_NUM_PROBES:
811 *data = GINT_TO_POINTER(NUM_PROBES);
812 break;
813 case SR_DI_PROBE_NAMES:
814 *data = probe_names;
815 break;
816 case SR_DI_SAMPLERATES:
817 *data = &samplerates;
818 break;
819 case SR_DI_TRIGGER_TYPES:
820 *data = (char *)TRIGGER_TYPES;
821 break;
822 case SR_DI_CUR_SAMPLERATE:
823 if (sdi) {
824 devc = sdi->priv;
825 *data = &devc->cur_samplerate;
826 } else
827 return SR_ERR;
828 break;
829 default:
830 return SR_ERR_ARG;
831 }
832
833 return SR_OK;
834}
835
836static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
837 const void *value)
838{
839 struct dev_context *devc;
840 int ret;
841
842 devc = sdi->priv;
843
844 if (hwcap == SR_HWCAP_SAMPLERATE) {
845 ret = set_samplerate(sdi, *(const uint64_t *)value);
846 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
847 devc->limit_msec = *(const uint64_t *)value;
848 if (devc->limit_msec > 0)
849 ret = SR_OK;
850 else
851 ret = SR_ERR;
852 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
853 devc->capture_ratio = *(const uint64_t *)value;
854 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
855 ret = SR_ERR;
856 else
857 ret = SR_OK;
858 } else {
859 ret = SR_ERR;
860 }
861
862 return ret;
863}
864
865/* Software trigger to determine exact trigger position. */
866static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
867 struct sigma_trigger *t)
868{
869 int i;
870
871 for (i = 0; i < 8; ++i) {
872 if (i > 0)
873 last_sample = samples[i-1];
874
875 /* Simple triggers. */
876 if ((samples[i] & t->simplemask) != t->simplevalue)
877 continue;
878
879 /* Rising edge. */
880 if ((last_sample & t->risingmask) != 0 || (samples[i] &
881 t->risingmask) != t->risingmask)
882 continue;
883
884 /* Falling edge. */
885 if ((last_sample & t->fallingmask) != t->fallingmask ||
886 (samples[i] & t->fallingmask) != 0)
887 continue;
888
889 break;
890 }
891
892 /* If we did not match, return original trigger pos. */
893 return i & 0x7;
894}
895
896/*
897 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
898 * Each event is 20ns apart, and can contain multiple samples.
899 *
900 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
901 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
902 * For 50 MHz and below, events contain one sample for each channel,
903 * spread 20 ns apart.
904 */
905static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
906 uint16_t *lastsample, int triggerpos,
907 uint16_t limit_chunk, void *cb_data)
908{
909 struct sr_dev_inst *sdi = cb_data;
910 struct dev_context *devc = sdi->priv;
911 uint16_t tsdiff, ts;
912 uint16_t samples[65536 * devc->samples_per_event];
913 struct sr_datafeed_packet packet;
914 struct sr_datafeed_logic logic;
915 int i, j, k, l, numpad, tosend;
916 size_t n = 0, sent = 0;
917 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
918 uint16_t *event;
919 uint16_t cur_sample;
920 int triggerts = -1;
921
922 /* Check if trigger is in this chunk. */
923 if (triggerpos != -1) {
924 if (devc->cur_samplerate <= SR_MHZ(50))
925 triggerpos -= EVENTS_PER_CLUSTER - 1;
926
927 if (triggerpos < 0)
928 triggerpos = 0;
929
930 /* Find in which cluster the trigger occured. */
931 triggerts = triggerpos / 7;
932 }
933
934 /* For each ts. */
935 for (i = 0; i < 64; ++i) {
936 ts = *(uint16_t *) &buf[i * 16];
937 tsdiff = ts - *lastts;
938 *lastts = ts;
939
940 /* Decode partial chunk. */
941 if (limit_chunk && ts > limit_chunk)
942 return SR_OK;
943
944 /* Pad last sample up to current point. */
945 numpad = tsdiff * devc->samples_per_event - clustersize;
946 if (numpad > 0) {
947 for (j = 0; j < numpad; ++j)
948 samples[j] = *lastsample;
949
950 n = numpad;
951 }
952
953 /* Send samples between previous and this timestamp to sigrok. */
954 sent = 0;
955 while (sent < n) {
956 tosend = MIN(2048, n - sent);
957
958 packet.type = SR_DF_LOGIC;
959 packet.payload = &logic;
960 logic.length = tosend * sizeof(uint16_t);
961 logic.unitsize = 2;
962 logic.data = samples + sent;
963 sr_session_send(devc->session_dev_id, &packet);
964
965 sent += tosend;
966 }
967 n = 0;
968
969 event = (uint16_t *) &buf[i * 16 + 2];
970 cur_sample = 0;
971
972 /* For each event in cluster. */
973 for (j = 0; j < 7; ++j) {
974
975 /* For each sample in event. */
976 for (k = 0; k < devc->samples_per_event; ++k) {
977 cur_sample = 0;
978
979 /* For each probe. */
980 for (l = 0; l < devc->num_probes; ++l)
981 cur_sample |= (!!(event[j] & (1 << (l *
982 devc->samples_per_event + k)))) << l;
983
984 samples[n++] = cur_sample;
985 }
986 }
987
988 /* Send data up to trigger point (if triggered). */
989 sent = 0;
990 if (i == triggerts) {
991 /*
992 * Trigger is not always accurate to sample because of
993 * pipeline delay. However, it always triggers before
994 * the actual event. We therefore look at the next
995 * samples to pinpoint the exact position of the trigger.
996 */
997 tosend = get_trigger_offset(samples, *lastsample,
998 &devc->trigger);
999
1000 if (tosend > 0) {
1001 packet.type = SR_DF_LOGIC;
1002 packet.payload = &logic;
1003 logic.length = tosend * sizeof(uint16_t);
1004 logic.unitsize = 2;
1005 logic.data = samples;
1006 sr_session_send(devc->session_dev_id, &packet);
1007
1008 sent += tosend;
1009 }
1010
1011 /* Only send trigger if explicitly enabled. */
1012 if (devc->use_triggers) {
1013 packet.type = SR_DF_TRIGGER;
1014 sr_session_send(devc->session_dev_id, &packet);
1015 }
1016 }
1017
1018 /* Send rest of the chunk to sigrok. */
1019 tosend = n - sent;
1020
1021 if (tosend > 0) {
1022 packet.type = SR_DF_LOGIC;
1023 packet.payload = &logic;
1024 logic.length = tosend * sizeof(uint16_t);
1025 logic.unitsize = 2;
1026 logic.data = samples + sent;
1027 sr_session_send(devc->session_dev_id, &packet);
1028 }
1029
1030 *lastsample = samples[n - 1];
1031 }
1032
1033 return SR_OK;
1034}
1035
1036static int receive_data(int fd, int revents, void *cb_data)
1037{
1038 struct sr_dev_inst *sdi = cb_data;
1039 struct dev_context *devc = sdi->priv;
1040 struct sr_datafeed_packet packet;
1041 const int chunks_per_read = 32;
1042 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1043 int bufsz, numchunks, i, newchunks;
1044 uint64_t running_msec;
1045 struct timeval tv;
1046
1047 (void)fd;
1048 (void)revents;
1049
1050 /* Get the current position. */
1051 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1052
1053 numchunks = (devc->state.stoppos + 511) / 512;
1054
1055 if (devc->state.state == SIGMA_IDLE)
1056 return TRUE;
1057
1058 if (devc->state.state == SIGMA_CAPTURE) {
1059 /* Check if the timer has expired, or memory is full. */
1060 gettimeofday(&tv, 0);
1061 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1062 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1063
1064 if (running_msec < devc->limit_msec && numchunks < 32767)
1065 return TRUE; /* While capturing... */
1066 else
1067 hw_dev_acquisition_stop(sdi, sdi);
1068
1069 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1070 if (devc->state.chunks_downloaded >= numchunks) {
1071 /* End of samples. */
1072 packet.type = SR_DF_END;
1073 sr_session_send(devc->session_dev_id, &packet);
1074
1075 devc->state.state = SIGMA_IDLE;
1076
1077 return TRUE;
1078 }
1079
1080 newchunks = MIN(chunks_per_read,
1081 numchunks - devc->state.chunks_downloaded);
1082
1083 sr_info("Downloading sample data: %.0f %%.",
1084 100.0 * devc->state.chunks_downloaded / numchunks);
1085
1086 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1087 newchunks, buf, devc);
1088 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1089 (void)bufsz;
1090
1091 /* Find first ts. */
1092 if (devc->state.chunks_downloaded == 0) {
1093 devc->state.lastts = *(uint16_t *) buf - 1;
1094 devc->state.lastsample = 0;
1095 }
1096
1097 /* Decode chunks and send them to sigrok. */
1098 for (i = 0; i < newchunks; ++i) {
1099 int limit_chunk = 0;
1100
1101 /* The last chunk may potentially be only in part. */
1102 if (devc->state.chunks_downloaded == numchunks - 1) {
1103 /* Find the last valid timestamp */
1104 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1105 }
1106
1107 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1108 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1109 &devc->state.lastts,
1110 &devc->state.lastsample,
1111 devc->state.triggerpos & 0x1ff,
1112 limit_chunk, sdi);
1113 else
1114 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1115 &devc->state.lastts,
1116 &devc->state.lastsample,
1117 -1, limit_chunk, sdi);
1118
1119 ++devc->state.chunks_downloaded;
1120 }
1121 }
1122
1123 return TRUE;
1124}
1125
1126/* Build a LUT entry used by the trigger functions. */
1127static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1128{
1129 int i, j, k, bit;
1130
1131 /* For each quad probe. */
1132 for (i = 0; i < 4; ++i) {
1133 entry[i] = 0xffff;
1134
1135 /* For each bit in LUT. */
1136 for (j = 0; j < 16; ++j)
1137
1138 /* For each probe in quad. */
1139 for (k = 0; k < 4; ++k) {
1140 bit = 1 << (i * 4 + k);
1141
1142 /* Set bit in entry */
1143 if ((mask & bit) &&
1144 ((!(value & bit)) !=
1145 (!(j & (1 << k)))))
1146 entry[i] &= ~(1 << j);
1147 }
1148 }
1149}
1150
1151/* Add a logical function to LUT mask. */
1152static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1153 int index, int neg, uint16_t *mask)
1154{
1155 int i, j;
1156 int x[2][2], tmp, a, b, aset, bset, rset;
1157
1158 memset(x, 0, 4 * sizeof(int));
1159
1160 /* Trigger detect condition. */
1161 switch (oper) {
1162 case OP_LEVEL:
1163 x[0][1] = 1;
1164 x[1][1] = 1;
1165 break;
1166 case OP_NOT:
1167 x[0][0] = 1;
1168 x[1][0] = 1;
1169 break;
1170 case OP_RISE:
1171 x[0][1] = 1;
1172 break;
1173 case OP_FALL:
1174 x[1][0] = 1;
1175 break;
1176 case OP_RISEFALL:
1177 x[0][1] = 1;
1178 x[1][0] = 1;
1179 break;
1180 case OP_NOTRISE:
1181 x[1][1] = 1;
1182 x[0][0] = 1;
1183 x[1][0] = 1;
1184 break;
1185 case OP_NOTFALL:
1186 x[1][1] = 1;
1187 x[0][0] = 1;
1188 x[0][1] = 1;
1189 break;
1190 case OP_NOTRISEFALL:
1191 x[1][1] = 1;
1192 x[0][0] = 1;
1193 break;
1194 }
1195
1196 /* Transpose if neg is set. */
1197 if (neg) {
1198 for (i = 0; i < 2; ++i) {
1199 for (j = 0; j < 2; ++j) {
1200 tmp = x[i][j];
1201 x[i][j] = x[1-i][1-j];
1202 x[1-i][1-j] = tmp;
1203 }
1204 }
1205 }
1206
1207 /* Update mask with function. */
1208 for (i = 0; i < 16; ++i) {
1209 a = (i >> (2 * index + 0)) & 1;
1210 b = (i >> (2 * index + 1)) & 1;
1211
1212 aset = (*mask >> i) & 1;
1213 bset = x[b][a];
1214
1215 if (func == FUNC_AND || func == FUNC_NAND)
1216 rset = aset & bset;
1217 else if (func == FUNC_OR || func == FUNC_NOR)
1218 rset = aset | bset;
1219 else if (func == FUNC_XOR || func == FUNC_NXOR)
1220 rset = aset ^ bset;
1221
1222 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1223 rset = !rset;
1224
1225 *mask &= ~(1 << i);
1226
1227 if (rset)
1228 *mask |= 1 << i;
1229 }
1230}
1231
1232/*
1233 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1234 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1235 * set at any time, but a full mask and value can be set (0/1).
1236 */
1237static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1238{
1239 int i,j;
1240 uint16_t masks[2] = { 0, 0 };
1241
1242 memset(lut, 0, sizeof(struct triggerlut));
1243
1244 /* Contant for simple triggers. */
1245 lut->m4 = 0xa000;
1246
1247 /* Value/mask trigger support. */
1248 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1249 lut->m2d);
1250
1251 /* Rise/fall trigger support. */
1252 for (i = 0, j = 0; i < 16; ++i) {
1253 if (devc->trigger.risingmask & (1 << i) ||
1254 devc->trigger.fallingmask & (1 << i))
1255 masks[j++] = 1 << i;
1256 }
1257
1258 build_lut_entry(masks[0], masks[0], lut->m0d);
1259 build_lut_entry(masks[1], masks[1], lut->m1d);
1260
1261 /* Add glue logic */
1262 if (masks[0] || masks[1]) {
1263 /* Transition trigger. */
1264 if (masks[0] & devc->trigger.risingmask)
1265 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1266 if (masks[0] & devc->trigger.fallingmask)
1267 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1268 if (masks[1] & devc->trigger.risingmask)
1269 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1270 if (masks[1] & devc->trigger.fallingmask)
1271 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1272 } else {
1273 /* Only value/mask trigger. */
1274 lut->m3 = 0xffff;
1275 }
1276
1277 /* Triggertype: event. */
1278 lut->params.selres = 3;
1279
1280 return SR_OK;
1281}
1282
1283static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1284 void *cb_data)
1285{
1286 struct dev_context *devc;
1287 struct sr_datafeed_packet *packet;
1288 struct sr_datafeed_header *header;
1289 struct sr_datafeed_meta_logic meta;
1290 struct clockselect_50 clockselect;
1291 int frac, triggerpin, ret;
1292 uint8_t triggerselect;
1293 struct triggerinout triggerinout_conf;
1294 struct triggerlut lut;
1295
1296 devc = sdi->priv;
1297
1298 if (configure_probes(sdi) != SR_OK) {
1299 sr_err("Failed to configure probes.");
1300 return SR_ERR;
1301 }
1302
1303 /* If the samplerate has not been set, default to 200 kHz. */
1304 if (devc->cur_firmware == -1) {
1305 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1306 return ret;
1307 }
1308
1309 /* Enter trigger programming mode. */
1310 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1311
1312 /* 100 and 200 MHz mode. */
1313 if (devc->cur_samplerate >= SR_MHZ(100)) {
1314 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1315
1316 /* Find which pin to trigger on from mask. */
1317 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1318 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1319 (1 << triggerpin))
1320 break;
1321
1322 /* Set trigger pin and light LED on trigger. */
1323 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1324
1325 /* Default rising edge. */
1326 if (devc->trigger.fallingmask)
1327 triggerselect |= 1 << 3;
1328
1329 /* All other modes. */
1330 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1331 build_basic_trigger(&lut, devc);
1332
1333 sigma_write_trigger_lut(&lut, devc);
1334
1335 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1336 }
1337
1338 /* Setup trigger in and out pins to default values. */
1339 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1340 triggerinout_conf.trgout_bytrigger = 1;
1341 triggerinout_conf.trgout_enable = 1;
1342
1343 sigma_write_register(WRITE_TRIGGER_OPTION,
1344 (uint8_t *) &triggerinout_conf,
1345 sizeof(struct triggerinout), devc);
1346
1347 /* Go back to normal mode. */
1348 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1349
1350 /* Set clock select register. */
1351 if (devc->cur_samplerate == SR_MHZ(200))
1352 /* Enable 4 probes. */
1353 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1354 else if (devc->cur_samplerate == SR_MHZ(100))
1355 /* Enable 8 probes. */
1356 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1357 else {
1358 /*
1359 * 50 MHz mode (or fraction thereof). Any fraction down to
1360 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1361 */
1362 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1363
1364 clockselect.async = 0;
1365 clockselect.fraction = frac;
1366 clockselect.disabled_probes = 0;
1367
1368 sigma_write_register(WRITE_CLOCK_SELECT,
1369 (uint8_t *) &clockselect,
1370 sizeof(clockselect), devc);
1371 }
1372
1373 /* Setup maximum post trigger time. */
1374 sigma_set_register(WRITE_POST_TRIGGER,
1375 (devc->capture_ratio * 255) / 100, devc);
1376
1377 /* Start acqusition. */
1378 gettimeofday(&devc->start_tv, 0);
1379 sigma_set_register(WRITE_MODE, 0x0d, devc);
1380
1381 devc->session_dev_id = cb_data;
1382
1383 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1384 sr_err("%s: packet malloc failed.", __func__);
1385 return SR_ERR_MALLOC;
1386 }
1387
1388 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1389 sr_err("%s: header malloc failed.", __func__);
1390 return SR_ERR_MALLOC;
1391 }
1392
1393 /* Send header packet to the session bus. */
1394 packet->type = SR_DF_HEADER;
1395 packet->payload = header;
1396 header->feed_version = 1;
1397 gettimeofday(&header->starttime, NULL);
1398 sr_session_send(devc->session_dev_id, packet);
1399
1400 /* Send metadata about the SR_DF_LOGIC packets to come. */
1401 packet->type = SR_DF_META_LOGIC;
1402 packet->payload = &meta;
1403 meta.samplerate = devc->cur_samplerate;
1404 meta.num_probes = devc->num_probes;
1405 sr_session_send(devc->session_dev_id, packet);
1406
1407 /* Add capture source. */
1408 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1409
1410 g_free(header);
1411 g_free(packet);
1412
1413 devc->state.state = SIGMA_CAPTURE;
1414
1415 return SR_OK;
1416}
1417
1418static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1419{
1420 struct dev_context *devc;
1421 uint8_t modestatus;
1422
1423 (void)cb_data;
1424
1425 sr_source_remove(0);
1426
1427 if (!(devc = sdi->priv)) {
1428 sr_err("%s: sdi->priv was NULL", __func__);
1429 return SR_ERR_BUG;
1430 }
1431
1432 /* Stop acquisition. */
1433 sigma_set_register(WRITE_MODE, 0x11, devc);
1434
1435 /* Set SDRAM Read Enable. */
1436 sigma_set_register(WRITE_MODE, 0x02, devc);
1437
1438 /* Get the current position. */
1439 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1440
1441 /* Check if trigger has fired. */
1442 modestatus = sigma_get_register(READ_MODE, devc);
1443 if (modestatus & 0x20)
1444 devc->state.triggerchunk = devc->state.triggerpos / 512;
1445 else
1446 devc->state.triggerchunk = -1;
1447
1448 devc->state.chunks_downloaded = 0;
1449
1450 devc->state.state = SIGMA_DOWNLOAD;
1451
1452 return SR_OK;
1453}
1454
1455SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1456 .name = "asix-sigma",
1457 .longname = "ASIX SIGMA/SIGMA2",
1458 .api_version = 1,
1459 .init = hw_init,
1460 .cleanup = hw_cleanup,
1461 .scan = hw_scan,
1462 .dev_list = hw_dev_list,
1463 .dev_clear = clear_instances,
1464 .dev_open = hw_dev_open,
1465 .dev_close = hw_dev_close,
1466 .info_get = hw_info_get,
1467 .dev_config_set = hw_dev_config_set,
1468 .dev_acquisition_start = hw_dev_acquisition_start,
1469 .dev_acquisition_stop = hw_dev_acquisition_stop,
1470 .priv = NULL,
1471};
Hardware access and backend lib