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1 | /* | |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include "sigrok.h" | |
31 | #include "sigrok-internal.h" | |
32 | #include "asix-sigma.h" | |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
40 | #define TRIGGER_TYPES "rf10" | |
41 | #define NUM_PROBES 16 | |
42 | ||
43 | static GSList *dev_insts = NULL; | |
44 | ||
45 | static uint64_t supported_samplerates[] = { | |
46 | SR_KHZ(200), | |
47 | SR_KHZ(250), | |
48 | SR_KHZ(500), | |
49 | SR_MHZ(1), | |
50 | SR_MHZ(5), | |
51 | SR_MHZ(10), | |
52 | SR_MHZ(25), | |
53 | SR_MHZ(50), | |
54 | SR_MHZ(100), | |
55 | SR_MHZ(200), | |
56 | 0, | |
57 | }; | |
58 | ||
59 | /* | |
60 | * Probe numbers seem to go from 1-16, according to this image: | |
61 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
62 | * (the cable has two additional GND pins, and a TI and TO pin) | |
63 | */ | |
64 | static const char *probe_names[NUM_PROBES + 1] = { | |
65 | "1", | |
66 | "2", | |
67 | "3", | |
68 | "4", | |
69 | "5", | |
70 | "6", | |
71 | "7", | |
72 | "8", | |
73 | "9", | |
74 | "10", | |
75 | "11", | |
76 | "12", | |
77 | "13", | |
78 | "14", | |
79 | "15", | |
80 | "16", | |
81 | NULL, | |
82 | }; | |
83 | ||
84 | static struct sr_samplerates samplerates = { | |
85 | 0, | |
86 | 0, | |
87 | 0, | |
88 | supported_samplerates, | |
89 | }; | |
90 | ||
91 | static int hwcaps[] = { | |
92 | SR_HWCAP_LOGIC_ANALYZER, | |
93 | SR_HWCAP_SAMPLERATE, | |
94 | SR_HWCAP_CAPTURE_RATIO, | |
95 | SR_HWCAP_PROBECONFIG, | |
96 | ||
97 | SR_HWCAP_LIMIT_MSEC, | |
98 | 0, | |
99 | }; | |
100 | ||
101 | /* Force the FPGA to reboot. */ | |
102 | static uint8_t suicide[] = { | |
103 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
104 | }; | |
105 | ||
106 | /* Prepare to upload firmware (FPGA specific). */ | |
107 | static uint8_t init[] = { | |
108 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
109 | }; | |
110 | ||
111 | /* Initialize the logic analyzer mode. */ | |
112 | static uint8_t logic_mode_start[] = { | |
113 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
114 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
115 | }; | |
116 | ||
117 | static const char *firmware_files[] = { | |
118 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ | |
119 | "asix-sigma-100.fw", /* 100 MHz */ | |
120 | "asix-sigma-200.fw", /* 200 MHz */ | |
121 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ | |
122 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
123 | }; | |
124 | ||
125 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data); | |
126 | ||
127 | static int sigma_read(void *buf, size_t size, struct context *ctx) | |
128 | { | |
129 | int ret; | |
130 | ||
131 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); | |
132 | if (ret < 0) { | |
133 | sr_err("sigma: ftdi_read_data failed: %s", | |
134 | ftdi_get_error_string(&ctx->ftdic)); | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
140 | static int sigma_write(void *buf, size_t size, struct context *ctx) | |
141 | { | |
142 | int ret; | |
143 | ||
144 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); | |
145 | if (ret < 0) { | |
146 | sr_err("sigma: ftdi_write_data failed: %s", | |
147 | ftdi_get_error_string(&ctx->ftdic)); | |
148 | } else if ((size_t) ret != size) { | |
149 | sr_err("sigma: ftdi_write_data did not complete write."); | |
150 | } | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
155 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
156 | struct context *ctx) | |
157 | { | |
158 | size_t i; | |
159 | uint8_t buf[len + 2]; | |
160 | int idx = 0; | |
161 | ||
162 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
163 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
164 | ||
165 | for (i = 0; i < len; ++i) { | |
166 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
167 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
168 | } | |
169 | ||
170 | return sigma_write(buf, idx, ctx); | |
171 | } | |
172 | ||
173 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) | |
174 | { | |
175 | return sigma_write_register(reg, &value, 1, ctx); | |
176 | } | |
177 | ||
178 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
179 | struct context *ctx) | |
180 | { | |
181 | uint8_t buf[3]; | |
182 | ||
183 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
184 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
185 | buf[2] = REG_READ_ADDR; | |
186 | ||
187 | sigma_write(buf, sizeof(buf), ctx); | |
188 | ||
189 | return sigma_read(data, len, ctx); | |
190 | } | |
191 | ||
192 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) | |
193 | { | |
194 | uint8_t value; | |
195 | ||
196 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { | |
197 | sr_err("sigma: sigma_get_register: 1 byte expected"); | |
198 | return 0; | |
199 | } | |
200 | ||
201 | return value; | |
202 | } | |
203 | ||
204 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
205 | struct context *ctx) | |
206 | { | |
207 | uint8_t buf[] = { | |
208 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
209 | ||
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | }; | |
217 | uint8_t result[6]; | |
218 | ||
219 | sigma_write(buf, sizeof(buf), ctx); | |
220 | ||
221 | sigma_read(result, sizeof(result), ctx); | |
222 | ||
223 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
224 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
225 | ||
226 | /* Not really sure why this must be done, but according to spec. */ | |
227 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
228 | stoppos -= 64; | |
229 | ||
230 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
231 | triggerpos -= 64; | |
232 | ||
233 | return 1; | |
234 | } | |
235 | ||
236 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
237 | uint8_t *data, struct context *ctx) | |
238 | { | |
239 | size_t i; | |
240 | uint8_t buf[4096]; | |
241 | int idx = 0; | |
242 | ||
243 | /* Send the startchunk. Index start with 1. */ | |
244 | buf[0] = startchunk >> 8; | |
245 | buf[1] = startchunk & 0xff; | |
246 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); | |
247 | ||
248 | /* Read the DRAM. */ | |
249 | buf[idx++] = REG_DRAM_BLOCK; | |
250 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
251 | ||
252 | for (i = 0; i < numchunks; ++i) { | |
253 | /* Alternate bit to copy from DRAM to cache. */ | |
254 | if (i != (numchunks - 1)) | |
255 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
256 | ||
257 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
258 | ||
259 | if (i != (numchunks - 1)) | |
260 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
261 | } | |
262 | ||
263 | sigma_write(buf, idx, ctx); | |
264 | ||
265 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); | |
266 | } | |
267 | ||
268 | /* Upload trigger look-up tables to Sigma. */ | |
269 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) | |
270 | { | |
271 | int i; | |
272 | uint8_t tmp[2]; | |
273 | uint16_t bit; | |
274 | ||
275 | /* Transpose the table and send to Sigma. */ | |
276 | for (i = 0; i < 16; ++i) { | |
277 | bit = 1 << i; | |
278 | ||
279 | tmp[0] = tmp[1] = 0; | |
280 | ||
281 | if (lut->m2d[0] & bit) | |
282 | tmp[0] |= 0x01; | |
283 | if (lut->m2d[1] & bit) | |
284 | tmp[0] |= 0x02; | |
285 | if (lut->m2d[2] & bit) | |
286 | tmp[0] |= 0x04; | |
287 | if (lut->m2d[3] & bit) | |
288 | tmp[0] |= 0x08; | |
289 | ||
290 | if (lut->m3 & bit) | |
291 | tmp[0] |= 0x10; | |
292 | if (lut->m3s & bit) | |
293 | tmp[0] |= 0x20; | |
294 | if (lut->m4 & bit) | |
295 | tmp[0] |= 0x40; | |
296 | ||
297 | if (lut->m0d[0] & bit) | |
298 | tmp[1] |= 0x01; | |
299 | if (lut->m0d[1] & bit) | |
300 | tmp[1] |= 0x02; | |
301 | if (lut->m0d[2] & bit) | |
302 | tmp[1] |= 0x04; | |
303 | if (lut->m0d[3] & bit) | |
304 | tmp[1] |= 0x08; | |
305 | ||
306 | if (lut->m1d[0] & bit) | |
307 | tmp[1] |= 0x10; | |
308 | if (lut->m1d[1] & bit) | |
309 | tmp[1] |= 0x20; | |
310 | if (lut->m1d[2] & bit) | |
311 | tmp[1] |= 0x40; | |
312 | if (lut->m1d[3] & bit) | |
313 | tmp[1] |= 0x80; | |
314 | ||
315 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
316 | ctx); | |
317 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
318 | } | |
319 | ||
320 | /* Send the parameters */ | |
321 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
322 | sizeof(lut->params), ctx); | |
323 | ||
324 | return SR_OK; | |
325 | } | |
326 | ||
327 | /* Generate the bitbang stream for programming the FPGA. */ | |
328 | static int bin2bitbang(const char *filename, | |
329 | unsigned char **buf, size_t *buf_size) | |
330 | { | |
331 | FILE *f; | |
332 | unsigned long file_size; | |
333 | unsigned long offset = 0; | |
334 | unsigned char *p; | |
335 | uint8_t *firmware; | |
336 | unsigned long fwsize = 0; | |
337 | const int buffer_size = 65536; | |
338 | size_t i; | |
339 | int c, bit, v; | |
340 | uint32_t imm = 0x3f6df2ab; | |
341 | ||
342 | f = g_fopen(filename, "rb"); | |
343 | if (!f) { | |
344 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); | |
345 | return SR_ERR; | |
346 | } | |
347 | ||
348 | if (-1 == fseek(f, 0, SEEK_END)) { | |
349 | sr_err("sigma: fseek on %s failed", filename); | |
350 | fclose(f); | |
351 | return SR_ERR; | |
352 | } | |
353 | ||
354 | file_size = ftell(f); | |
355 | ||
356 | fseek(f, 0, SEEK_SET); | |
357 | ||
358 | if (!(firmware = g_try_malloc(buffer_size))) { | |
359 | sr_err("sigma: %s: firmware malloc failed", __func__); | |
360 | fclose(f); | |
361 | return SR_ERR_MALLOC; | |
362 | } | |
363 | ||
364 | while ((c = getc(f)) != EOF) { | |
365 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
366 | firmware[fwsize++] = c ^ imm; | |
367 | } | |
368 | fclose(f); | |
369 | ||
370 | if(fwsize != file_size) { | |
371 | sr_err("sigma: %s: Error reading firmware", filename); | |
372 | fclose(f); | |
373 | g_free(firmware); | |
374 | return SR_ERR; | |
375 | } | |
376 | ||
377 | *buf_size = fwsize * 2 * 8; | |
378 | ||
379 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); | |
380 | if (!p) { | |
381 | sr_err("sigma: %s: buf/p malloc failed", __func__); | |
382 | g_free(firmware); | |
383 | return SR_ERR_MALLOC; | |
384 | } | |
385 | ||
386 | for (i = 0; i < fwsize; ++i) { | |
387 | for (bit = 7; bit >= 0; --bit) { | |
388 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; | |
389 | p[offset++] = v | 0x01; | |
390 | p[offset++] = v; | |
391 | } | |
392 | } | |
393 | ||
394 | g_free(firmware); | |
395 | ||
396 | if (offset != *buf_size) { | |
397 | g_free(*buf); | |
398 | sr_err("sigma: Error reading firmware %s " | |
399 | "offset=%ld, file_size=%ld, buf_size=%zd.", | |
400 | filename, offset, file_size, *buf_size); | |
401 | ||
402 | return SR_ERR; | |
403 | } | |
404 | ||
405 | return SR_OK; | |
406 | } | |
407 | ||
408 | static int hw_init(const char *devinfo) | |
409 | { | |
410 | struct sr_dev_inst *sdi; | |
411 | struct context *ctx; | |
412 | struct ftdi_device_list *devlist; | |
413 | char serial_txt[10]; | |
414 | uint32_t serial; | |
415 | ||
416 | /* Avoid compiler warnings. */ | |
417 | (void)devinfo; | |
418 | ||
419 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { | |
420 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
421 | return SR_ERR_MALLOC; | |
422 | } | |
423 | ||
424 | ftdi_init(&ctx->ftdic); | |
425 | ||
426 | /* Look for SIGMAs. */ | |
427 | ||
428 | if (ftdi_usb_find_all(&ctx->ftdic, &devlist, | |
429 | USB_VENDOR, USB_PRODUCT) <= 0) | |
430 | goto free; | |
431 | ||
432 | /* Make sure it's a version 1 or 2 SIGMA. */ | |
433 | ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
434 | serial_txt, sizeof(serial_txt)); | |
435 | sscanf(serial_txt, "%x", &serial); | |
436 | ||
437 | if (serial < 0xa6010000 || serial > 0xa602ffff) { | |
438 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " | |
439 | "in this version of sigrok."); | |
440 | goto free; | |
441 | } | |
442 | ||
443 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
444 | ||
445 | ctx->cur_samplerate = 0; | |
446 | ctx->period_ps = 0; | |
447 | ctx->limit_msec = 0; | |
448 | ctx->cur_firmware = -1; | |
449 | ctx->num_probes = 0; | |
450 | ctx->samples_per_event = 0; | |
451 | ctx->capture_ratio = 50; | |
452 | ctx->use_triggers = 0; | |
453 | ||
454 | /* Register SIGMA device. */ | |
455 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
456 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
457 | sr_err("sigma: %s: sdi was NULL", __func__); | |
458 | goto free; | |
459 | } | |
460 | ||
461 | sdi->priv = ctx; | |
462 | ||
463 | dev_insts = g_slist_append(dev_insts, sdi); | |
464 | ||
465 | /* We will open the device again when we need it. */ | |
466 | ftdi_list_free(&devlist); | |
467 | ||
468 | return 1; | |
469 | ||
470 | free: | |
471 | g_free(ctx); | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static int upload_firmware(int firmware_idx, struct context *ctx) | |
476 | { | |
477 | int ret; | |
478 | unsigned char *buf; | |
479 | unsigned char pins; | |
480 | size_t buf_size; | |
481 | unsigned char result[32]; | |
482 | char firmware_path[128]; | |
483 | ||
484 | /* Make sure it's an ASIX SIGMA. */ | |
485 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, | |
486 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
487 | sr_err("sigma: ftdi_usb_open failed: %s", | |
488 | ftdi_get_error_string(&ctx->ftdic)); | |
489 | return 0; | |
490 | } | |
491 | ||
492 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
493 | sr_err("sigma: ftdi_set_bitmode failed: %s", | |
494 | ftdi_get_error_string(&ctx->ftdic)); | |
495 | return 0; | |
496 | } | |
497 | ||
498 | /* Four times the speed of sigmalogan - Works well. */ | |
499 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { | |
500 | sr_err("sigma: ftdi_set_baudrate failed: %s", | |
501 | ftdi_get_error_string(&ctx->ftdic)); | |
502 | return 0; | |
503 | } | |
504 | ||
505 | /* Force the FPGA to reboot. */ | |
506 | sigma_write(suicide, sizeof(suicide), ctx); | |
507 | sigma_write(suicide, sizeof(suicide), ctx); | |
508 | sigma_write(suicide, sizeof(suicide), ctx); | |
509 | sigma_write(suicide, sizeof(suicide), ctx); | |
510 | ||
511 | /* Prepare to upload firmware (FPGA specific). */ | |
512 | sigma_write(init, sizeof(init), ctx); | |
513 | ||
514 | ftdi_usb_purge_buffers(&ctx->ftdic); | |
515 | ||
516 | /* Wait until the FPGA asserts INIT_B. */ | |
517 | while (1) { | |
518 | ret = sigma_read(result, 1, ctx); | |
519 | if (result[0] & 0x20) | |
520 | break; | |
521 | } | |
522 | ||
523 | /* Prepare firmware. */ | |
524 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, | |
525 | firmware_files[firmware_idx]); | |
526 | ||
527 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { | |
528 | sr_err("sigma: An error occured while reading the firmware: %s", | |
529 | firmware_path); | |
530 | return ret; | |
531 | } | |
532 | ||
533 | /* Upload firmare. */ | |
534 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); | |
535 | sigma_write(buf, buf_size, ctx); | |
536 | ||
537 | g_free(buf); | |
538 | ||
539 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { | |
540 | sr_err("sigma: ftdi_set_bitmode failed: %s", | |
541 | ftdi_get_error_string(&ctx->ftdic)); | |
542 | return SR_ERR; | |
543 | } | |
544 | ||
545 | ftdi_usb_purge_buffers(&ctx->ftdic); | |
546 | ||
547 | /* Discard garbage. */ | |
548 | while (1 == sigma_read(&pins, 1, ctx)) | |
549 | ; | |
550 | ||
551 | /* Initialize the logic analyzer mode. */ | |
552 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); | |
553 | ||
554 | /* Expect a 3 byte reply. */ | |
555 | ret = sigma_read(result, 3, ctx); | |
556 | if (ret != 3 || | |
557 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
558 | sr_err("sigma: Configuration failed. Invalid reply received."); | |
559 | return SR_ERR; | |
560 | } | |
561 | ||
562 | ctx->cur_firmware = firmware_idx; | |
563 | ||
564 | sr_info("sigma: Firmware uploaded"); | |
565 | ||
566 | return SR_OK; | |
567 | } | |
568 | ||
569 | static int hw_dev_open(int dev_index) | |
570 | { | |
571 | struct sr_dev_inst *sdi; | |
572 | struct context *ctx; | |
573 | int ret; | |
574 | ||
575 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) | |
576 | return SR_ERR; | |
577 | ||
578 | ctx = sdi->priv; | |
579 | ||
580 | /* Make sure it's an ASIX SIGMA. */ | |
581 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, | |
582 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
583 | ||
584 | sr_err("sigma: ftdi_usb_open failed: %s", | |
585 | ftdi_get_error_string(&ctx->ftdic)); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | sdi->status = SR_ST_ACTIVE; | |
591 | ||
592 | return SR_OK; | |
593 | } | |
594 | ||
595 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) | |
596 | { | |
597 | int i, ret; | |
598 | struct context *ctx = sdi->priv; | |
599 | ||
600 | for (i = 0; supported_samplerates[i]; i++) { | |
601 | if (supported_samplerates[i] == samplerate) | |
602 | break; | |
603 | } | |
604 | if (supported_samplerates[i] == 0) | |
605 | return SR_ERR_SAMPLERATE; | |
606 | ||
607 | if (samplerate <= SR_MHZ(50)) { | |
608 | ret = upload_firmware(0, ctx); | |
609 | ctx->num_probes = 16; | |
610 | } | |
611 | if (samplerate == SR_MHZ(100)) { | |
612 | ret = upload_firmware(1, ctx); | |
613 | ctx->num_probes = 8; | |
614 | } | |
615 | else if (samplerate == SR_MHZ(200)) { | |
616 | ret = upload_firmware(2, ctx); | |
617 | ctx->num_probes = 4; | |
618 | } | |
619 | ||
620 | ctx->cur_samplerate = samplerate; | |
621 | ctx->period_ps = 1000000000000 / samplerate; | |
622 | ctx->samples_per_event = 16 / ctx->num_probes; | |
623 | ctx->state.state = SIGMA_IDLE; | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
628 | /* | |
629 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
630 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
631 | * in addition to value/mask trigger for any number of probes. | |
632 | * | |
633 | * The Sigma supports complex triggers using boolean expressions, but this | |
634 | * has not been implemented yet. | |
635 | */ | |
636 | static int configure_probes(struct sr_dev_inst *sdi, GSList *probes) | |
637 | { | |
638 | struct context *ctx = sdi->priv; | |
639 | struct sr_probe *probe; | |
640 | GSList *l; | |
641 | int trigger_set = 0; | |
642 | int probebit; | |
643 | ||
644 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); | |
645 | ||
646 | for (l = probes; l; l = l->next) { | |
647 | probe = (struct sr_probe *)l->data; | |
648 | probebit = 1 << (probe->index - 1); | |
649 | ||
650 | if (!probe->enabled || !probe->trigger) | |
651 | continue; | |
652 | ||
653 | if (ctx->cur_samplerate >= SR_MHZ(100)) { | |
654 | /* Fast trigger support. */ | |
655 | if (trigger_set) { | |
656 | sr_err("sigma: ASIX SIGMA only supports a single " | |
657 | "pin trigger in 100 and 200MHz mode."); | |
658 | return SR_ERR; | |
659 | } | |
660 | if (probe->trigger[0] == 'f') | |
661 | ctx->trigger.fallingmask |= probebit; | |
662 | else if (probe->trigger[0] == 'r') | |
663 | ctx->trigger.risingmask |= probebit; | |
664 | else { | |
665 | sr_err("sigma: ASIX SIGMA only supports " | |
666 | "rising/falling trigger in 100 " | |
667 | "and 200MHz mode."); | |
668 | return SR_ERR; | |
669 | } | |
670 | ||
671 | ++trigger_set; | |
672 | } else { | |
673 | /* Simple trigger support (event). */ | |
674 | if (probe->trigger[0] == '1') { | |
675 | ctx->trigger.simplevalue |= probebit; | |
676 | ctx->trigger.simplemask |= probebit; | |
677 | } | |
678 | else if (probe->trigger[0] == '0') { | |
679 | ctx->trigger.simplevalue &= ~probebit; | |
680 | ctx->trigger.simplemask |= probebit; | |
681 | } | |
682 | else if (probe->trigger[0] == 'f') { | |
683 | ctx->trigger.fallingmask |= probebit; | |
684 | ++trigger_set; | |
685 | } | |
686 | else if (probe->trigger[0] == 'r') { | |
687 | ctx->trigger.risingmask |= probebit; | |
688 | ++trigger_set; | |
689 | } | |
690 | ||
691 | /* | |
692 | * Actually, Sigma supports 2 rising/falling triggers, | |
693 | * but they are ORed and the current trigger syntax | |
694 | * does not permit ORed triggers. | |
695 | */ | |
696 | if (trigger_set > 1) { | |
697 | sr_err("sigma: ASIX SIGMA only supports 1 " | |
698 | "rising/falling triggers."); | |
699 | return SR_ERR; | |
700 | } | |
701 | } | |
702 | ||
703 | if (trigger_set) | |
704 | ctx->use_triggers = 1; | |
705 | } | |
706 | ||
707 | return SR_OK; | |
708 | } | |
709 | ||
710 | static int hw_dev_close(int dev_index) | |
711 | { | |
712 | struct sr_dev_inst *sdi; | |
713 | struct context *ctx; | |
714 | ||
715 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { | |
716 | sr_err("sigma: %s: sdi was NULL", __func__); | |
717 | return SR_ERR_BUG; | |
718 | } | |
719 | ||
720 | if (!(ctx = sdi->priv)) { | |
721 | sr_err("sigma: %s: sdi->priv was NULL", __func__); | |
722 | return SR_ERR_BUG; | |
723 | } | |
724 | ||
725 | /* TODO */ | |
726 | if (sdi->status == SR_ST_ACTIVE) | |
727 | ftdi_usb_close(&ctx->ftdic); | |
728 | ||
729 | sdi->status = SR_ST_INACTIVE; | |
730 | ||
731 | return SR_OK; | |
732 | } | |
733 | ||
734 | static int hw_cleanup(void) | |
735 | { | |
736 | GSList *l; | |
737 | struct sr_dev_inst *sdi; | |
738 | int ret = SR_OK; | |
739 | ||
740 | /* Properly close all devices. */ | |
741 | for (l = dev_insts; l; l = l->next) { | |
742 | if (!(sdi = l->data)) { | |
743 | /* Log error, but continue cleaning up the rest. */ | |
744 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); | |
745 | ret = SR_ERR_BUG; | |
746 | continue; | |
747 | } | |
748 | sr_dev_inst_free(sdi); | |
749 | } | |
750 | g_slist_free(dev_insts); | |
751 | dev_insts = NULL; | |
752 | ||
753 | return ret; | |
754 | } | |
755 | ||
756 | static void *hw_dev_info_get(int dev_index, int dev_info_id) | |
757 | { | |
758 | struct sr_dev_inst *sdi; | |
759 | struct context *ctx; | |
760 | void *info = NULL; | |
761 | ||
762 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { | |
763 | sr_err("sigma: %s: sdi was NULL", __func__); | |
764 | return NULL; | |
765 | } | |
766 | ||
767 | ctx = sdi->priv; | |
768 | ||
769 | switch (dev_info_id) { | |
770 | case SR_DI_INST: | |
771 | info = sdi; | |
772 | break; | |
773 | case SR_DI_NUM_PROBES: | |
774 | info = GINT_TO_POINTER(NUM_PROBES); | |
775 | break; | |
776 | case SR_DI_PROBE_NAMES: | |
777 | info = probe_names; | |
778 | break; | |
779 | case SR_DI_SAMPLERATES: | |
780 | info = &samplerates; | |
781 | break; | |
782 | case SR_DI_TRIGGER_TYPES: | |
783 | info = (char *)TRIGGER_TYPES; | |
784 | break; | |
785 | case SR_DI_CUR_SAMPLERATE: | |
786 | info = &ctx->cur_samplerate; | |
787 | break; | |
788 | } | |
789 | ||
790 | return info; | |
791 | } | |
792 | ||
793 | static int hw_dev_status_get(int dev_index) | |
794 | { | |
795 | struct sr_dev_inst *sdi; | |
796 | ||
797 | sdi = sr_dev_inst_get(dev_insts, dev_index); | |
798 | if (sdi) | |
799 | return sdi->status; | |
800 | else | |
801 | return SR_ST_NOT_FOUND; | |
802 | } | |
803 | ||
804 | static int *hw_hwcap_get_all(void) | |
805 | { | |
806 | return hwcaps; | |
807 | } | |
808 | ||
809 | static int hw_dev_config_set(int dev_index, int hwcap, void *value) | |
810 | { | |
811 | struct sr_dev_inst *sdi; | |
812 | struct context *ctx; | |
813 | int ret; | |
814 | ||
815 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) | |
816 | return SR_ERR; | |
817 | ||
818 | ctx = sdi->priv; | |
819 | ||
820 | if (hwcap == SR_HWCAP_SAMPLERATE) { | |
821 | ret = set_samplerate(sdi, *(uint64_t *)value); | |
822 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { | |
823 | ret = configure_probes(sdi, value); | |
824 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { | |
825 | ctx->limit_msec = *(uint64_t *)value; | |
826 | if (ctx->limit_msec > 0) | |
827 | ret = SR_OK; | |
828 | else | |
829 | ret = SR_ERR; | |
830 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { | |
831 | ctx->capture_ratio = *(uint64_t *)value; | |
832 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) | |
833 | ret = SR_ERR; | |
834 | else | |
835 | ret = SR_OK; | |
836 | } else { | |
837 | ret = SR_ERR; | |
838 | } | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
843 | /* Software trigger to determine exact trigger position. */ | |
844 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
845 | struct sigma_trigger *t) | |
846 | { | |
847 | int i; | |
848 | ||
849 | for (i = 0; i < 8; ++i) { | |
850 | if (i > 0) | |
851 | last_sample = samples[i-1]; | |
852 | ||
853 | /* Simple triggers. */ | |
854 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
855 | continue; | |
856 | ||
857 | /* Rising edge. */ | |
858 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
859 | t->risingmask) != t->risingmask) | |
860 | continue; | |
861 | ||
862 | /* Falling edge. */ | |
863 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
864 | (samples[i] & t->fallingmask) != 0) | |
865 | continue; | |
866 | ||
867 | break; | |
868 | } | |
869 | ||
870 | /* If we did not match, return original trigger pos. */ | |
871 | return i & 0x7; | |
872 | } | |
873 | ||
874 | /* | |
875 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
876 | * Each event is 20ns apart, and can contain multiple samples. | |
877 | * | |
878 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
879 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
880 | * For 50 MHz and below, events contain one sample for each channel, | |
881 | * spread 20 ns apart. | |
882 | */ | |
883 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
884 | uint16_t *lastsample, int triggerpos, | |
885 | uint16_t limit_chunk, void *cb_data) | |
886 | { | |
887 | struct sr_dev_inst *sdi = cb_data; | |
888 | struct context *ctx = sdi->priv; | |
889 | uint16_t tsdiff, ts; | |
890 | uint16_t samples[65536 * ctx->samples_per_event]; | |
891 | struct sr_datafeed_packet packet; | |
892 | struct sr_datafeed_logic logic; | |
893 | int i, j, k, l, numpad, tosend; | |
894 | size_t n = 0, sent = 0; | |
895 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; | |
896 | uint16_t *event; | |
897 | uint16_t cur_sample; | |
898 | int triggerts = -1; | |
899 | ||
900 | /* Check if trigger is in this chunk. */ | |
901 | if (triggerpos != -1) { | |
902 | if (ctx->cur_samplerate <= SR_MHZ(50)) | |
903 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
904 | ||
905 | if (triggerpos < 0) | |
906 | triggerpos = 0; | |
907 | ||
908 | /* Find in which cluster the trigger occured. */ | |
909 | triggerts = triggerpos / 7; | |
910 | } | |
911 | ||
912 | /* For each ts. */ | |
913 | for (i = 0; i < 64; ++i) { | |
914 | ts = *(uint16_t *) &buf[i * 16]; | |
915 | tsdiff = ts - *lastts; | |
916 | *lastts = ts; | |
917 | ||
918 | /* Decode partial chunk. */ | |
919 | if (limit_chunk && ts > limit_chunk) | |
920 | return SR_OK; | |
921 | ||
922 | /* Pad last sample up to current point. */ | |
923 | numpad = tsdiff * ctx->samples_per_event - clustersize; | |
924 | if (numpad > 0) { | |
925 | for (j = 0; j < numpad; ++j) | |
926 | samples[j] = *lastsample; | |
927 | ||
928 | n = numpad; | |
929 | } | |
930 | ||
931 | /* Send samples between previous and this timestamp to sigrok. */ | |
932 | sent = 0; | |
933 | while (sent < n) { | |
934 | tosend = MIN(2048, n - sent); | |
935 | ||
936 | packet.type = SR_DF_LOGIC; | |
937 | packet.payload = &logic; | |
938 | logic.length = tosend * sizeof(uint16_t); | |
939 | logic.unitsize = 2; | |
940 | logic.data = samples + sent; | |
941 | sr_session_send(ctx->session_dev_id, &packet); | |
942 | ||
943 | sent += tosend; | |
944 | } | |
945 | n = 0; | |
946 | ||
947 | event = (uint16_t *) &buf[i * 16 + 2]; | |
948 | cur_sample = 0; | |
949 | ||
950 | /* For each event in cluster. */ | |
951 | for (j = 0; j < 7; ++j) { | |
952 | ||
953 | /* For each sample in event. */ | |
954 | for (k = 0; k < ctx->samples_per_event; ++k) { | |
955 | cur_sample = 0; | |
956 | ||
957 | /* For each probe. */ | |
958 | for (l = 0; l < ctx->num_probes; ++l) | |
959 | cur_sample |= (!!(event[j] & (1 << (l * | |
960 | ctx->samples_per_event + k)))) << l; | |
961 | ||
962 | samples[n++] = cur_sample; | |
963 | } | |
964 | } | |
965 | ||
966 | /* Send data up to trigger point (if triggered). */ | |
967 | sent = 0; | |
968 | if (i == triggerts) { | |
969 | /* | |
970 | * Trigger is not always accurate to sample because of | |
971 | * pipeline delay. However, it always triggers before | |
972 | * the actual event. We therefore look at the next | |
973 | * samples to pinpoint the exact position of the trigger. | |
974 | */ | |
975 | tosend = get_trigger_offset(samples, *lastsample, | |
976 | &ctx->trigger); | |
977 | ||
978 | if (tosend > 0) { | |
979 | packet.type = SR_DF_LOGIC; | |
980 | packet.payload = &logic; | |
981 | logic.length = tosend * sizeof(uint16_t); | |
982 | logic.unitsize = 2; | |
983 | logic.data = samples; | |
984 | sr_session_send(ctx->session_dev_id, &packet); | |
985 | ||
986 | sent += tosend; | |
987 | } | |
988 | ||
989 | /* Only send trigger if explicitly enabled. */ | |
990 | if (ctx->use_triggers) { | |
991 | packet.type = SR_DF_TRIGGER; | |
992 | sr_session_send(ctx->session_dev_id, &packet); | |
993 | } | |
994 | } | |
995 | ||
996 | /* Send rest of the chunk to sigrok. */ | |
997 | tosend = n - sent; | |
998 | ||
999 | if (tosend > 0) { | |
1000 | packet.type = SR_DF_LOGIC; | |
1001 | packet.payload = &logic; | |
1002 | logic.length = tosend * sizeof(uint16_t); | |
1003 | logic.unitsize = 2; | |
1004 | logic.data = samples + sent; | |
1005 | sr_session_send(ctx->session_dev_id, &packet); | |
1006 | } | |
1007 | ||
1008 | *lastsample = samples[n - 1]; | |
1009 | } | |
1010 | ||
1011 | return SR_OK; | |
1012 | } | |
1013 | ||
1014 | static int receive_data(int fd, int revents, void *cb_data) | |
1015 | { | |
1016 | struct sr_dev_inst *sdi = cb_data; | |
1017 | struct context *ctx = sdi->priv; | |
1018 | struct sr_datafeed_packet packet; | |
1019 | const int chunks_per_read = 32; | |
1020 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1021 | int bufsz, numchunks, i, newchunks; | |
1022 | uint64_t running_msec; | |
1023 | struct timeval tv; | |
1024 | ||
1025 | /* Avoid compiler warnings. */ | |
1026 | (void)fd; | |
1027 | (void)revents; | |
1028 | ||
1029 | /* Get the current position. */ | |
1030 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1031 | ||
1032 | numchunks = (ctx->state.stoppos + 511) / 512; | |
1033 | ||
1034 | if (ctx->state.state == SIGMA_IDLE) | |
1035 | return TRUE; | |
1036 | ||
1037 | if (ctx->state.state == SIGMA_CAPTURE) { | |
1038 | /* Check if the timer has expired, or memory is full. */ | |
1039 | gettimeofday(&tv, 0); | |
1040 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + | |
1041 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
1042 | ||
1043 | if (running_msec < ctx->limit_msec && numchunks < 32767) | |
1044 | return TRUE; /* While capturing... */ | |
1045 | else | |
1046 | hw_dev_acquisition_stop(sdi->index, sdi); | |
1047 | ||
1048 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { | |
1049 | if (ctx->state.chunks_downloaded >= numchunks) { | |
1050 | /* End of samples. */ | |
1051 | packet.type = SR_DF_END; | |
1052 | sr_session_send(ctx->session_dev_id, &packet); | |
1053 | ||
1054 | ctx->state.state = SIGMA_IDLE; | |
1055 | ||
1056 | return TRUE; | |
1057 | } | |
1058 | ||
1059 | newchunks = MIN(chunks_per_read, | |
1060 | numchunks - ctx->state.chunks_downloaded); | |
1061 | ||
1062 | sr_info("sigma: Downloading sample data: %.0f %%", | |
1063 | 100.0 * ctx->state.chunks_downloaded / numchunks); | |
1064 | ||
1065 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, | |
1066 | newchunks, buf, ctx); | |
1067 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1068 | (void)bufsz; | |
1069 | ||
1070 | /* Find first ts. */ | |
1071 | if (ctx->state.chunks_downloaded == 0) { | |
1072 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1073 | ctx->state.lastsample = 0; | |
1074 | } | |
1075 | ||
1076 | /* Decode chunks and send them to sigrok. */ | |
1077 | for (i = 0; i < newchunks; ++i) { | |
1078 | int limit_chunk = 0; | |
1079 | ||
1080 | /* The last chunk may potentially be only in part. */ | |
1081 | if (ctx->state.chunks_downloaded == numchunks - 1) { | |
1082 | /* Find the last valid timestamp */ | |
1083 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; | |
1084 | } | |
1085 | ||
1086 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) | |
1087 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1088 | &ctx->state.lastts, | |
1089 | &ctx->state.lastsample, | |
1090 | ctx->state.triggerpos & 0x1ff, | |
1091 | limit_chunk, sdi); | |
1092 | else | |
1093 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1094 | &ctx->state.lastts, | |
1095 | &ctx->state.lastsample, | |
1096 | -1, limit_chunk, sdi); | |
1097 | ||
1098 | ++ctx->state.chunks_downloaded; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | return TRUE; | |
1103 | } | |
1104 | ||
1105 | /* Build a LUT entry used by the trigger functions. */ | |
1106 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1107 | { | |
1108 | int i, j, k, bit; | |
1109 | ||
1110 | /* For each quad probe. */ | |
1111 | for (i = 0; i < 4; ++i) { | |
1112 | entry[i] = 0xffff; | |
1113 | ||
1114 | /* For each bit in LUT. */ | |
1115 | for (j = 0; j < 16; ++j) | |
1116 | ||
1117 | /* For each probe in quad. */ | |
1118 | for (k = 0; k < 4; ++k) { | |
1119 | bit = 1 << (i * 4 + k); | |
1120 | ||
1121 | /* Set bit in entry */ | |
1122 | if ((mask & bit) && | |
1123 | ((!(value & bit)) != | |
1124 | (!(j & (1 << k))))) | |
1125 | entry[i] &= ~(1 << j); | |
1126 | } | |
1127 | } | |
1128 | } | |
1129 | ||
1130 | /* Add a logical function to LUT mask. */ | |
1131 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1132 | int index, int neg, uint16_t *mask) | |
1133 | { | |
1134 | int i, j; | |
1135 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1136 | ||
1137 | memset(x, 0, 4 * sizeof(int)); | |
1138 | ||
1139 | /* Trigger detect condition. */ | |
1140 | switch (oper) { | |
1141 | case OP_LEVEL: | |
1142 | x[0][1] = 1; | |
1143 | x[1][1] = 1; | |
1144 | break; | |
1145 | case OP_NOT: | |
1146 | x[0][0] = 1; | |
1147 | x[1][0] = 1; | |
1148 | break; | |
1149 | case OP_RISE: | |
1150 | x[0][1] = 1; | |
1151 | break; | |
1152 | case OP_FALL: | |
1153 | x[1][0] = 1; | |
1154 | break; | |
1155 | case OP_RISEFALL: | |
1156 | x[0][1] = 1; | |
1157 | x[1][0] = 1; | |
1158 | break; | |
1159 | case OP_NOTRISE: | |
1160 | x[1][1] = 1; | |
1161 | x[0][0] = 1; | |
1162 | x[1][0] = 1; | |
1163 | break; | |
1164 | case OP_NOTFALL: | |
1165 | x[1][1] = 1; | |
1166 | x[0][0] = 1; | |
1167 | x[0][1] = 1; | |
1168 | break; | |
1169 | case OP_NOTRISEFALL: | |
1170 | x[1][1] = 1; | |
1171 | x[0][0] = 1; | |
1172 | break; | |
1173 | } | |
1174 | ||
1175 | /* Transpose if neg is set. */ | |
1176 | if (neg) { | |
1177 | for (i = 0; i < 2; ++i) { | |
1178 | for (j = 0; j < 2; ++j) { | |
1179 | tmp = x[i][j]; | |
1180 | x[i][j] = x[1-i][1-j]; | |
1181 | x[1-i][1-j] = tmp; | |
1182 | } | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | /* Update mask with function. */ | |
1187 | for (i = 0; i < 16; ++i) { | |
1188 | a = (i >> (2 * index + 0)) & 1; | |
1189 | b = (i >> (2 * index + 1)) & 1; | |
1190 | ||
1191 | aset = (*mask >> i) & 1; | |
1192 | bset = x[b][a]; | |
1193 | ||
1194 | if (func == FUNC_AND || func == FUNC_NAND) | |
1195 | rset = aset & bset; | |
1196 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1197 | rset = aset | bset; | |
1198 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1199 | rset = aset ^ bset; | |
1200 | ||
1201 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1202 | rset = !rset; | |
1203 | ||
1204 | *mask &= ~(1 << i); | |
1205 | ||
1206 | if (rset) | |
1207 | *mask |= 1 << i; | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1213 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1214 | * set at any time, but a full mask and value can be set (0/1). | |
1215 | */ | |
1216 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) | |
1217 | { | |
1218 | int i,j; | |
1219 | uint16_t masks[2] = { 0, 0 }; | |
1220 | ||
1221 | memset(lut, 0, sizeof(struct triggerlut)); | |
1222 | ||
1223 | /* Contant for simple triggers. */ | |
1224 | lut->m4 = 0xa000; | |
1225 | ||
1226 | /* Value/mask trigger support. */ | |
1227 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, | |
1228 | lut->m2d); | |
1229 | ||
1230 | /* Rise/fall trigger support. */ | |
1231 | for (i = 0, j = 0; i < 16; ++i) { | |
1232 | if (ctx->trigger.risingmask & (1 << i) || | |
1233 | ctx->trigger.fallingmask & (1 << i)) | |
1234 | masks[j++] = 1 << i; | |
1235 | } | |
1236 | ||
1237 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1238 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1239 | ||
1240 | /* Add glue logic */ | |
1241 | if (masks[0] || masks[1]) { | |
1242 | /* Transition trigger. */ | |
1243 | if (masks[0] & ctx->trigger.risingmask) | |
1244 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1245 | if (masks[0] & ctx->trigger.fallingmask) | |
1246 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1247 | if (masks[1] & ctx->trigger.risingmask) | |
1248 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1249 | if (masks[1] & ctx->trigger.fallingmask) | |
1250 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1251 | } else { | |
1252 | /* Only value/mask trigger. */ | |
1253 | lut->m3 = 0xffff; | |
1254 | } | |
1255 | ||
1256 | /* Triggertype: event. */ | |
1257 | lut->params.selres = 3; | |
1258 | ||
1259 | return SR_OK; | |
1260 | } | |
1261 | ||
1262 | static int hw_dev_acquisition_start(int dev_index, void *cb_data) | |
1263 | { | |
1264 | struct sr_dev_inst *sdi; | |
1265 | struct context *ctx; | |
1266 | struct sr_datafeed_packet *packet; | |
1267 | struct sr_datafeed_header *header; | |
1268 | struct sr_datafeed_meta_logic meta; | |
1269 | struct clockselect_50 clockselect; | |
1270 | int frac, triggerpin, ret; | |
1271 | uint8_t triggerselect; | |
1272 | struct triggerinout triggerinout_conf; | |
1273 | struct triggerlut lut; | |
1274 | ||
1275 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) | |
1276 | return SR_ERR; | |
1277 | ||
1278 | ctx = sdi->priv; | |
1279 | ||
1280 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1281 | if (ctx->cur_firmware == -1) { | |
1282 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1283 | return ret; | |
1284 | } | |
1285 | ||
1286 | /* Enter trigger programming mode. */ | |
1287 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); | |
1288 | ||
1289 | /* 100 and 200 MHz mode. */ | |
1290 | if (ctx->cur_samplerate >= SR_MHZ(100)) { | |
1291 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
1292 | ||
1293 | /* Find which pin to trigger on from mask. */ | |
1294 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1295 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & | |
1296 | (1 << triggerpin)) | |
1297 | break; | |
1298 | ||
1299 | /* Set trigger pin and light LED on trigger. */ | |
1300 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1301 | ||
1302 | /* Default rising edge. */ | |
1303 | if (ctx->trigger.fallingmask) | |
1304 | triggerselect |= 1 << 3; | |
1305 | ||
1306 | /* All other modes. */ | |
1307 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { | |
1308 | build_basic_trigger(&lut, ctx); | |
1309 | ||
1310 | sigma_write_trigger_lut(&lut, ctx); | |
1311 | ||
1312 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1313 | } | |
1314 | ||
1315 | /* Setup trigger in and out pins to default values. */ | |
1316 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1317 | triggerinout_conf.trgout_bytrigger = 1; | |
1318 | triggerinout_conf.trgout_enable = 1; | |
1319 | ||
1320 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1321 | (uint8_t *) &triggerinout_conf, | |
1322 | sizeof(struct triggerinout), ctx); | |
1323 | ||
1324 | /* Go back to normal mode. */ | |
1325 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); | |
1326 | ||
1327 | /* Set clock select register. */ | |
1328 | if (ctx->cur_samplerate == SR_MHZ(200)) | |
1329 | /* Enable 4 probes. */ | |
1330 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); | |
1331 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
1332 | /* Enable 8 probes. */ | |
1333 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); | |
1334 | else { | |
1335 | /* | |
1336 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1337 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1338 | */ | |
1339 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; | |
1340 | ||
1341 | clockselect.async = 0; | |
1342 | clockselect.fraction = frac; | |
1343 | clockselect.disabled_probes = 0; | |
1344 | ||
1345 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1346 | (uint8_t *) &clockselect, | |
1347 | sizeof(clockselect), ctx); | |
1348 | } | |
1349 | ||
1350 | /* Setup maximum post trigger time. */ | |
1351 | sigma_set_register(WRITE_POST_TRIGGER, | |
1352 | (ctx->capture_ratio * 255) / 100, ctx); | |
1353 | ||
1354 | /* Start acqusition. */ | |
1355 | gettimeofday(&ctx->start_tv, 0); | |
1356 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
1357 | ||
1358 | ctx->session_dev_id = cb_data; | |
1359 | ||
1360 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { | |
1361 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1362 | return SR_ERR_MALLOC; | |
1363 | } | |
1364 | ||
1365 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1366 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1367 | return SR_ERR_MALLOC; | |
1368 | } | |
1369 | ||
1370 | /* Send header packet to the session bus. */ | |
1371 | packet->type = SR_DF_HEADER; | |
1372 | packet->payload = header; | |
1373 | header->feed_version = 1; | |
1374 | gettimeofday(&header->starttime, NULL); | |
1375 | sr_session_send(ctx->session_dev_id, packet); | |
1376 | ||
1377 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1378 | packet->type = SR_DF_META_LOGIC; | |
1379 | packet->payload = &meta; | |
1380 | meta.samplerate = ctx->cur_samplerate; | |
1381 | meta.num_probes = ctx->num_probes; | |
1382 | sr_session_send(ctx->session_dev_id, packet); | |
1383 | ||
1384 | /* Add capture source. */ | |
1385 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); | |
1386 | ||
1387 | g_free(header); | |
1388 | g_free(packet); | |
1389 | ||
1390 | ctx->state.state = SIGMA_CAPTURE; | |
1391 | ||
1392 | return SR_OK; | |
1393 | } | |
1394 | ||
1395 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data) | |
1396 | { | |
1397 | struct sr_dev_inst *sdi; | |
1398 | struct context *ctx; | |
1399 | uint8_t modestatus; | |
1400 | ||
1401 | /* Avoid compiler warnings. */ | |
1402 | (void)cb_data; | |
1403 | ||
1404 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { | |
1405 | sr_err("sigma: %s: sdi was NULL", __func__); | |
1406 | return SR_ERR_BUG; | |
1407 | } | |
1408 | ||
1409 | if (!(ctx = sdi->priv)) { | |
1410 | sr_err("sigma: %s: sdi->priv was NULL", __func__); | |
1411 | return SR_ERR_BUG; | |
1412 | } | |
1413 | ||
1414 | /* Stop acquisition. */ | |
1415 | sigma_set_register(WRITE_MODE, 0x11, ctx); | |
1416 | ||
1417 | /* Set SDRAM Read Enable. */ | |
1418 | sigma_set_register(WRITE_MODE, 0x02, ctx); | |
1419 | ||
1420 | /* Get the current position. */ | |
1421 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1422 | ||
1423 | /* Check if trigger has fired. */ | |
1424 | modestatus = sigma_get_register(READ_MODE, ctx); | |
1425 | if (modestatus & 0x20) | |
1426 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; | |
1427 | else | |
1428 | ctx->state.triggerchunk = -1; | |
1429 | ||
1430 | ctx->state.chunks_downloaded = 0; | |
1431 | ||
1432 | ctx->state.state = SIGMA_DOWNLOAD; | |
1433 | ||
1434 | return SR_OK; | |
1435 | } | |
1436 | ||
1437 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { | |
1438 | .name = "asix-sigma", | |
1439 | .longname = "ASIX SIGMA/SIGMA2", | |
1440 | .api_version = 1, | |
1441 | .init = hw_init, | |
1442 | .cleanup = hw_cleanup, | |
1443 | .dev_open = hw_dev_open, | |
1444 | .dev_close = hw_dev_close, | |
1445 | .dev_info_get = hw_dev_info_get, | |
1446 | .dev_status_get = hw_dev_status_get, | |
1447 | .hwcap_get_all = hw_hwcap_get_all, | |
1448 | .dev_config_set = hw_dev_config_set, | |
1449 | .dev_acquisition_start = hw_dev_acquisition_start, | |
1450 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
1451 | }; |