]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
26 | #include "config.h" | |
27 | #include <glib.h> | |
28 | #include <glib/gstdio.h> | |
29 | #include <ftdi.h> | |
30 | #include <string.h> | |
31 | #include <zlib.h> | |
32 | #include <sigrok.h> | |
33 | #include <sigrok-internal.h> | |
34 | #include "asix-sigma.h" | |
35 | ||
36 | #define USB_VENDOR 0xa600 | |
37 | #define USB_PRODUCT 0xa000 | |
38 | #define USB_DESCRIPTION "ASIX SIGMA" | |
39 | #define USB_VENDOR_NAME "ASIX" | |
40 | #define USB_MODEL_NAME "SIGMA" | |
41 | #define USB_MODEL_VERSION "" | |
42 | #define TRIGGER_TYPES "rf10" | |
43 | ||
44 | static GSList *device_instances = NULL; | |
45 | ||
46 | static uint64_t supported_samplerates[] = { | |
47 | SR_KHZ(200), | |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
57 | 0, | |
58 | }; | |
59 | ||
60 | static struct sr_samplerates samplerates = { | |
61 | SR_KHZ(200), | |
62 | SR_MHZ(200), | |
63 | SR_HZ(0), | |
64 | supported_samplerates, | |
65 | }; | |
66 | ||
67 | static int capabilities[] = { | |
68 | SR_HWCAP_LOGIC_ANALYZER, | |
69 | SR_HWCAP_SAMPLERATE, | |
70 | SR_HWCAP_CAPTURE_RATIO, | |
71 | SR_HWCAP_PROBECONFIG, | |
72 | ||
73 | SR_HWCAP_LIMIT_MSEC, | |
74 | 0, | |
75 | }; | |
76 | ||
77 | /* Force the FPGA to reboot. */ | |
78 | static uint8_t suicide[] = { | |
79 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
80 | }; | |
81 | ||
82 | /* Prepare to upload firmware (FPGA specific). */ | |
83 | static uint8_t init[] = { | |
84 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
85 | }; | |
86 | ||
87 | /* Initialize the logic analyzer mode. */ | |
88 | static uint8_t logic_mode_start[] = { | |
89 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
90 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
91 | }; | |
92 | ||
93 | static const char *firmware_files[] = { | |
94 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ | |
95 | "asix-sigma-100.fw", /* 100 MHz */ | |
96 | "asix-sigma-200.fw", /* 200 MHz */ | |
97 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ | |
98 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
99 | }; | |
100 | ||
101 | static void hw_stop_acquisition(int device_index, gpointer session_device_id); | |
102 | ||
103 | static int sigma_read(void *buf, size_t size, struct sigma *sigma) | |
104 | { | |
105 | int ret; | |
106 | ||
107 | ret = ftdi_read_data(&sigma->ftdic, (unsigned char *)buf, size); | |
108 | if (ret < 0) { | |
109 | sr_warn("ftdi_read_data failed: %s", | |
110 | ftdi_get_error_string(&sigma->ftdic)); | |
111 | } | |
112 | ||
113 | return ret; | |
114 | } | |
115 | ||
116 | static int sigma_write(void *buf, size_t size, struct sigma *sigma) | |
117 | { | |
118 | int ret; | |
119 | ||
120 | ret = ftdi_write_data(&sigma->ftdic, (unsigned char *)buf, size); | |
121 | if (ret < 0) { | |
122 | sr_warn("ftdi_write_data failed: %s", | |
123 | ftdi_get_error_string(&sigma->ftdic)); | |
124 | } else if ((size_t) ret != size) { | |
125 | sr_warn("ftdi_write_data did not complete write\n"); | |
126 | } | |
127 | ||
128 | return ret; | |
129 | } | |
130 | ||
131 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
132 | struct sigma *sigma) | |
133 | { | |
134 | size_t i; | |
135 | uint8_t buf[len + 2]; | |
136 | int idx = 0; | |
137 | ||
138 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
139 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
140 | ||
141 | for (i = 0; i < len; ++i) { | |
142 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
143 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
144 | } | |
145 | ||
146 | return sigma_write(buf, idx, sigma); | |
147 | } | |
148 | ||
149 | static int sigma_set_register(uint8_t reg, uint8_t value, struct sigma *sigma) | |
150 | { | |
151 | return sigma_write_register(reg, &value, 1, sigma); | |
152 | } | |
153 | ||
154 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
155 | struct sigma *sigma) | |
156 | { | |
157 | uint8_t buf[3]; | |
158 | ||
159 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
160 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
161 | buf[2] = REG_READ_ADDR; | |
162 | ||
163 | sigma_write(buf, sizeof(buf), sigma); | |
164 | ||
165 | return sigma_read(data, len, sigma); | |
166 | } | |
167 | ||
168 | static uint8_t sigma_get_register(uint8_t reg, struct sigma *sigma) | |
169 | { | |
170 | uint8_t value; | |
171 | ||
172 | if (1 != sigma_read_register(reg, &value, 1, sigma)) { | |
173 | sr_warn("sigma_get_register: 1 byte expected"); | |
174 | return 0; | |
175 | } | |
176 | ||
177 | return value; | |
178 | } | |
179 | ||
180 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
181 | struct sigma *sigma) | |
182 | { | |
183 | uint8_t buf[] = { | |
184 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
185 | ||
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | REG_READ_ADDR | NEXT_REG, | |
192 | }; | |
193 | uint8_t result[6]; | |
194 | ||
195 | sigma_write(buf, sizeof(buf), sigma); | |
196 | ||
197 | sigma_read(result, sizeof(result), sigma); | |
198 | ||
199 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
200 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
201 | ||
202 | /* Not really sure why this must be done, but according to spec. */ | |
203 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
204 | stoppos -= 64; | |
205 | ||
206 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
207 | triggerpos -= 64; | |
208 | ||
209 | return 1; | |
210 | } | |
211 | ||
212 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
213 | uint8_t *data, struct sigma *sigma) | |
214 | { | |
215 | size_t i; | |
216 | uint8_t buf[4096]; | |
217 | int idx = 0; | |
218 | ||
219 | /* Send the startchunk. Index start with 1. */ | |
220 | buf[0] = startchunk >> 8; | |
221 | buf[1] = startchunk & 0xff; | |
222 | sigma_write_register(WRITE_MEMROW, buf, 2, sigma); | |
223 | ||
224 | /* Read the DRAM. */ | |
225 | buf[idx++] = REG_DRAM_BLOCK; | |
226 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
227 | ||
228 | for (i = 0; i < numchunks; ++i) { | |
229 | /* Alternate bit to copy from DRAM to cache. */ | |
230 | if (i != (numchunks - 1)) | |
231 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
232 | ||
233 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
234 | ||
235 | if (i != (numchunks - 1)) | |
236 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
237 | } | |
238 | ||
239 | sigma_write(buf, idx, sigma); | |
240 | ||
241 | return sigma_read(data, numchunks * CHUNK_SIZE, sigma); | |
242 | } | |
243 | ||
244 | /* Upload trigger look-up tables to Sigma. */ | |
245 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct sigma *sigma) | |
246 | { | |
247 | int i; | |
248 | uint8_t tmp[2]; | |
249 | uint16_t bit; | |
250 | ||
251 | /* Transpose the table and send to Sigma. */ | |
252 | for (i = 0; i < 16; ++i) { | |
253 | bit = 1 << i; | |
254 | ||
255 | tmp[0] = tmp[1] = 0; | |
256 | ||
257 | if (lut->m2d[0] & bit) | |
258 | tmp[0] |= 0x01; | |
259 | if (lut->m2d[1] & bit) | |
260 | tmp[0] |= 0x02; | |
261 | if (lut->m2d[2] & bit) | |
262 | tmp[0] |= 0x04; | |
263 | if (lut->m2d[3] & bit) | |
264 | tmp[0] |= 0x08; | |
265 | ||
266 | if (lut->m3 & bit) | |
267 | tmp[0] |= 0x10; | |
268 | if (lut->m3s & bit) | |
269 | tmp[0] |= 0x20; | |
270 | if (lut->m4 & bit) | |
271 | tmp[0] |= 0x40; | |
272 | ||
273 | if (lut->m0d[0] & bit) | |
274 | tmp[1] |= 0x01; | |
275 | if (lut->m0d[1] & bit) | |
276 | tmp[1] |= 0x02; | |
277 | if (lut->m0d[2] & bit) | |
278 | tmp[1] |= 0x04; | |
279 | if (lut->m0d[3] & bit) | |
280 | tmp[1] |= 0x08; | |
281 | ||
282 | if (lut->m1d[0] & bit) | |
283 | tmp[1] |= 0x10; | |
284 | if (lut->m1d[1] & bit) | |
285 | tmp[1] |= 0x20; | |
286 | if (lut->m1d[2] & bit) | |
287 | tmp[1] |= 0x40; | |
288 | if (lut->m1d[3] & bit) | |
289 | tmp[1] |= 0x80; | |
290 | ||
291 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
292 | sigma); | |
293 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, sigma); | |
294 | } | |
295 | ||
296 | /* Send the parameters */ | |
297 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
298 | sizeof(lut->params), sigma); | |
299 | ||
300 | return SR_OK; | |
301 | } | |
302 | ||
303 | /* Generate the bitbang stream for programming the FPGA. */ | |
304 | static int bin2bitbang(const char *filename, | |
305 | unsigned char **buf, size_t *buf_size) | |
306 | { | |
307 | FILE *f; | |
308 | long file_size; | |
309 | unsigned long offset = 0; | |
310 | unsigned char *p; | |
311 | uint8_t *compressed_buf, *firmware; | |
312 | uLongf csize, fwsize; | |
313 | const int buffer_size = 65536; | |
314 | size_t i; | |
315 | int c, ret, bit, v; | |
316 | uint32_t imm = 0x3f6df2ab; | |
317 | ||
318 | f = g_fopen(filename, "rb"); | |
319 | if (!f) { | |
320 | sr_warn("g_fopen(\"%s\", \"rb\")", filename); | |
321 | return SR_ERR; | |
322 | } | |
323 | ||
324 | if (-1 == fseek(f, 0, SEEK_END)) { | |
325 | sr_warn("fseek on %s failed", filename); | |
326 | fclose(f); | |
327 | return SR_ERR; | |
328 | } | |
329 | ||
330 | file_size = ftell(f); | |
331 | ||
332 | fseek(f, 0, SEEK_SET); | |
333 | ||
334 | if (!(compressed_buf = g_try_malloc(file_size))) { | |
335 | sr_err("asix: %s: compressed_buf malloc failed", __func__); | |
336 | fclose(f); | |
337 | return SR_ERR_MALLOC; | |
338 | } | |
339 | ||
340 | if (!(firmware = g_try_malloc(buffer_size))) { | |
341 | sr_err("asix: %s: firmware malloc failed", __func__); | |
342 | fclose(f); | |
343 | g_free(compressed_buf); | |
344 | return SR_ERR_MALLOC; | |
345 | } | |
346 | ||
347 | csize = 0; | |
348 | while ((c = getc(f)) != EOF) { | |
349 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
350 | compressed_buf[csize++] = c ^ imm; | |
351 | } | |
352 | fclose(f); | |
353 | ||
354 | fwsize = buffer_size; | |
355 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
356 | if (ret < 0) { | |
357 | g_free(compressed_buf); | |
358 | g_free(firmware); | |
359 | sr_warn("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
360 | return SR_ERR; | |
361 | } | |
362 | ||
363 | g_free(compressed_buf); | |
364 | ||
365 | *buf_size = fwsize * 2 * 8; | |
366 | ||
367 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); | |
368 | if (!p) { | |
369 | sr_err("asix: %s: buf/p malloc failed", __func__); | |
370 | g_free(compressed_buf); | |
371 | g_free(firmware); | |
372 | return SR_ERR_MALLOC; | |
373 | } | |
374 | ||
375 | for (i = 0; i < fwsize; ++i) { | |
376 | for (bit = 7; bit >= 0; --bit) { | |
377 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; | |
378 | p[offset++] = v | 0x01; | |
379 | p[offset++] = v; | |
380 | } | |
381 | } | |
382 | ||
383 | g_free(firmware); | |
384 | ||
385 | if (offset != *buf_size) { | |
386 | g_free(*buf); | |
387 | sr_warn("Error reading firmware %s " | |
388 | "offset=%ld, file_size=%ld, buf_size=%zd\n", | |
389 | filename, offset, file_size, *buf_size); | |
390 | ||
391 | return SR_ERR; | |
392 | } | |
393 | ||
394 | return SR_OK; | |
395 | } | |
396 | ||
397 | static int hw_init(const char *deviceinfo) | |
398 | { | |
399 | struct sr_device_instance *sdi; | |
400 | struct sigma *sigma; | |
401 | ||
402 | /* Avoid compiler warnings. */ | |
403 | deviceinfo = deviceinfo; | |
404 | ||
405 | if (!(sigma = g_try_malloc(sizeof(struct sigma)))) { | |
406 | sr_err("asix: %s: sigma malloc failed", __func__); | |
407 | return 0; /* FIXME: Should be SR_ERR_MALLOC. */ | |
408 | } | |
409 | ||
410 | ftdi_init(&sigma->ftdic); | |
411 | ||
412 | /* Look for SIGMAs. */ | |
413 | if (ftdi_usb_open_desc(&sigma->ftdic, USB_VENDOR, USB_PRODUCT, | |
414 | USB_DESCRIPTION, NULL) < 0) | |
415 | goto free; | |
416 | ||
417 | sigma->cur_samplerate = 0; | |
418 | sigma->limit_msec = 0; | |
419 | sigma->cur_firmware = -1; | |
420 | sigma->num_probes = 0; | |
421 | sigma->samples_per_event = 0; | |
422 | sigma->capture_ratio = 50; | |
423 | sigma->use_triggers = 0; | |
424 | ||
425 | /* Register SIGMA device. */ | |
426 | sdi = sr_device_instance_new(0, SR_ST_INITIALIZING, | |
427 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); | |
428 | if (!sdi) | |
429 | goto free; | |
430 | ||
431 | sdi->priv = sigma; | |
432 | ||
433 | device_instances = g_slist_append(device_instances, sdi); | |
434 | ||
435 | /* We will open the device again when we need it. */ | |
436 | ftdi_usb_close(&sigma->ftdic); | |
437 | ||
438 | return 1; | |
439 | free: | |
440 | g_free(sigma); | |
441 | return 0; | |
442 | } | |
443 | ||
444 | static int upload_firmware(int firmware_idx, struct sigma *sigma) | |
445 | { | |
446 | int ret; | |
447 | unsigned char *buf; | |
448 | unsigned char pins; | |
449 | size_t buf_size; | |
450 | unsigned char result[32]; | |
451 | char firmware_path[128]; | |
452 | ||
453 | /* Make sure it's an ASIX SIGMA. */ | |
454 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, | |
455 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
456 | sr_warn("ftdi_usb_open failed: %s", | |
457 | ftdi_get_error_string(&sigma->ftdic)); | |
458 | return 0; | |
459 | } | |
460 | ||
461 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
462 | sr_warn("ftdi_set_bitmode failed: %s", | |
463 | ftdi_get_error_string(&sigma->ftdic)); | |
464 | return 0; | |
465 | } | |
466 | ||
467 | /* Four times the speed of sigmalogan - Works well. */ | |
468 | if ((ret = ftdi_set_baudrate(&sigma->ftdic, 750000)) < 0) { | |
469 | sr_warn("ftdi_set_baudrate failed: %s", | |
470 | ftdi_get_error_string(&sigma->ftdic)); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | /* Force the FPGA to reboot. */ | |
475 | sigma_write(suicide, sizeof(suicide), sigma); | |
476 | sigma_write(suicide, sizeof(suicide), sigma); | |
477 | sigma_write(suicide, sizeof(suicide), sigma); | |
478 | sigma_write(suicide, sizeof(suicide), sigma); | |
479 | ||
480 | /* Prepare to upload firmware (FPGA specific). */ | |
481 | sigma_write(init, sizeof(init), sigma); | |
482 | ||
483 | ftdi_usb_purge_buffers(&sigma->ftdic); | |
484 | ||
485 | /* Wait until the FPGA asserts INIT_B. */ | |
486 | while (1) { | |
487 | ret = sigma_read(result, 1, sigma); | |
488 | if (result[0] & 0x20) | |
489 | break; | |
490 | } | |
491 | ||
492 | /* Prepare firmware. */ | |
493 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, | |
494 | firmware_files[firmware_idx]); | |
495 | ||
496 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { | |
497 | sr_warn("An error occured while reading the firmware: %s", | |
498 | firmware_path); | |
499 | return ret; | |
500 | } | |
501 | ||
502 | /* Upload firmare. */ | |
503 | sigma_write(buf, buf_size, sigma); | |
504 | ||
505 | g_free(buf); | |
506 | ||
507 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0x00, BITMODE_RESET)) < 0) { | |
508 | sr_warn("ftdi_set_bitmode failed: %s", | |
509 | ftdi_get_error_string(&sigma->ftdic)); | |
510 | return SR_ERR; | |
511 | } | |
512 | ||
513 | ftdi_usb_purge_buffers(&sigma->ftdic); | |
514 | ||
515 | /* Discard garbage. */ | |
516 | while (1 == sigma_read(&pins, 1, sigma)) | |
517 | ; | |
518 | ||
519 | /* Initialize the logic analyzer mode. */ | |
520 | sigma_write(logic_mode_start, sizeof(logic_mode_start), sigma); | |
521 | ||
522 | /* Expect a 3 byte reply. */ | |
523 | ret = sigma_read(result, 3, sigma); | |
524 | if (ret != 3 || | |
525 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
526 | sr_warn("Configuration failed. Invalid reply received."); | |
527 | return SR_ERR; | |
528 | } | |
529 | ||
530 | sigma->cur_firmware = firmware_idx; | |
531 | ||
532 | return SR_OK; | |
533 | } | |
534 | ||
535 | static int hw_opendev(int device_index) | |
536 | { | |
537 | struct sr_device_instance *sdi; | |
538 | struct sigma *sigma; | |
539 | int ret; | |
540 | ||
541 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) | |
542 | return SR_ERR; | |
543 | ||
544 | sigma = sdi->priv; | |
545 | ||
546 | /* Make sure it's an ASIX SIGMA. */ | |
547 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, | |
548 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
549 | ||
550 | sr_warn("ftdi_usb_open failed: %s", | |
551 | ftdi_get_error_string(&sigma->ftdic)); | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | sdi->status = SR_ST_ACTIVE; | |
557 | ||
558 | return SR_OK; | |
559 | } | |
560 | ||
561 | static int set_samplerate(struct sr_device_instance *sdi, | |
562 | uint64_t samplerate) | |
563 | { | |
564 | int i, ret; | |
565 | struct sigma *sigma = sdi->priv; | |
566 | ||
567 | for (i = 0; supported_samplerates[i]; i++) { | |
568 | if (supported_samplerates[i] == samplerate) | |
569 | break; | |
570 | } | |
571 | if (supported_samplerates[i] == 0) | |
572 | return SR_ERR_SAMPLERATE; | |
573 | ||
574 | if (samplerate <= SR_MHZ(50)) { | |
575 | ret = upload_firmware(0, sigma); | |
576 | sigma->num_probes = 16; | |
577 | } | |
578 | if (samplerate == SR_MHZ(100)) { | |
579 | ret = upload_firmware(1, sigma); | |
580 | sigma->num_probes = 8; | |
581 | } | |
582 | else if (samplerate == SR_MHZ(200)) { | |
583 | ret = upload_firmware(2, sigma); | |
584 | sigma->num_probes = 4; | |
585 | } | |
586 | ||
587 | sigma->cur_samplerate = samplerate; | |
588 | sigma->samples_per_event = 16 / sigma->num_probes; | |
589 | sigma->state.state = SIGMA_IDLE; | |
590 | ||
591 | sr_info("Firmware uploaded"); | |
592 | ||
593 | return ret; | |
594 | } | |
595 | ||
596 | /* | |
597 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
598 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
599 | * in addition to value/mask trigger for any number of probes. | |
600 | * | |
601 | * The Sigma supports complex triggers using boolean expressions, but this | |
602 | * has not been implemented yet. | |
603 | */ | |
604 | static int configure_probes(struct sr_device_instance *sdi, GSList *probes) | |
605 | { | |
606 | struct sigma *sigma = sdi->priv; | |
607 | struct sr_probe *probe; | |
608 | GSList *l; | |
609 | int trigger_set = 0; | |
610 | int probebit; | |
611 | ||
612 | memset(&sigma->trigger, 0, sizeof(struct sigma_trigger)); | |
613 | ||
614 | for (l = probes; l; l = l->next) { | |
615 | probe = (struct sr_probe *)l->data; | |
616 | probebit = 1 << (probe->index - 1); | |
617 | ||
618 | if (!probe->enabled || !probe->trigger) | |
619 | continue; | |
620 | ||
621 | if (sigma->cur_samplerate >= SR_MHZ(100)) { | |
622 | /* Fast trigger support. */ | |
623 | if (trigger_set) { | |
624 | sr_warn("Asix Sigma only supports a single " | |
625 | "pin trigger in 100 and 200MHz mode."); | |
626 | return SR_ERR; | |
627 | } | |
628 | if (probe->trigger[0] == 'f') | |
629 | sigma->trigger.fallingmask |= probebit; | |
630 | else if (probe->trigger[0] == 'r') | |
631 | sigma->trigger.risingmask |= probebit; | |
632 | else { | |
633 | sr_warn("Asix Sigma only supports " | |
634 | "rising/falling trigger in 100 " | |
635 | "and 200MHz mode."); | |
636 | return SR_ERR; | |
637 | } | |
638 | ||
639 | ++trigger_set; | |
640 | } else { | |
641 | /* Simple trigger support (event). */ | |
642 | if (probe->trigger[0] == '1') { | |
643 | sigma->trigger.simplevalue |= probebit; | |
644 | sigma->trigger.simplemask |= probebit; | |
645 | } | |
646 | else if (probe->trigger[0] == '0') { | |
647 | sigma->trigger.simplevalue &= ~probebit; | |
648 | sigma->trigger.simplemask |= probebit; | |
649 | } | |
650 | else if (probe->trigger[0] == 'f') { | |
651 | sigma->trigger.fallingmask |= probebit; | |
652 | ++trigger_set; | |
653 | } | |
654 | else if (probe->trigger[0] == 'r') { | |
655 | sigma->trigger.risingmask |= probebit; | |
656 | ++trigger_set; | |
657 | } | |
658 | ||
659 | /* | |
660 | * Actually, Sigma supports 2 rising/falling triggers, | |
661 | * but they are ORed and the current trigger syntax | |
662 | * does not permit ORed triggers. | |
663 | */ | |
664 | if (trigger_set > 1) { | |
665 | sr_warn("Asix Sigma only supports 1 rising/" | |
666 | "falling triggers."); | |
667 | return SR_ERR; | |
668 | } | |
669 | } | |
670 | ||
671 | if (trigger_set) | |
672 | sigma->use_triggers = 1; | |
673 | } | |
674 | ||
675 | return SR_OK; | |
676 | } | |
677 | ||
678 | static void hw_closedev(int device_index) | |
679 | { | |
680 | struct sr_device_instance *sdi; | |
681 | struct sigma *sigma; | |
682 | ||
683 | if ((sdi = sr_get_device_instance(device_instances, device_index))) | |
684 | { | |
685 | sigma = sdi->priv; | |
686 | if (sdi->status == SR_ST_ACTIVE) | |
687 | ftdi_usb_close(&sigma->ftdic); | |
688 | ||
689 | sdi->status = SR_ST_INACTIVE; | |
690 | } | |
691 | } | |
692 | ||
693 | static void hw_cleanup(void) | |
694 | { | |
695 | GSList *l; | |
696 | struct sr_device_instance *sdi; | |
697 | ||
698 | /* Properly close all devices. */ | |
699 | for (l = device_instances; l; l = l->next) { | |
700 | sdi = l->data; | |
701 | if (sdi->priv != NULL) | |
702 | free(sdi->priv); | |
703 | sr_device_instance_free(sdi); | |
704 | } | |
705 | g_slist_free(device_instances); | |
706 | device_instances = NULL; | |
707 | } | |
708 | ||
709 | static void *hw_get_device_info(int device_index, int device_info_id) | |
710 | { | |
711 | struct sr_device_instance *sdi; | |
712 | struct sigma *sigma; | |
713 | void *info = NULL; | |
714 | ||
715 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) { | |
716 | fprintf(stderr, "It's NULL.\n"); | |
717 | return NULL; | |
718 | } | |
719 | ||
720 | sigma = sdi->priv; | |
721 | ||
722 | switch (device_info_id) { | |
723 | case SR_DI_INSTANCE: | |
724 | info = sdi; | |
725 | break; | |
726 | case SR_DI_NUM_PROBES: | |
727 | info = GINT_TO_POINTER(16); | |
728 | break; | |
729 | case SR_DI_SAMPLERATES: | |
730 | info = &samplerates; | |
731 | break; | |
732 | case SR_DI_TRIGGER_TYPES: | |
733 | info = (char *)TRIGGER_TYPES; | |
734 | break; | |
735 | case SR_DI_CUR_SAMPLERATE: | |
736 | info = &sigma->cur_samplerate; | |
737 | break; | |
738 | } | |
739 | ||
740 | return info; | |
741 | } | |
742 | ||
743 | static int hw_get_status(int device_index) | |
744 | { | |
745 | struct sr_device_instance *sdi; | |
746 | ||
747 | sdi = sr_get_device_instance(device_instances, device_index); | |
748 | if (sdi) | |
749 | return sdi->status; | |
750 | else | |
751 | return SR_ST_NOT_FOUND; | |
752 | } | |
753 | ||
754 | static int *hw_get_capabilities(void) | |
755 | { | |
756 | return capabilities; | |
757 | } | |
758 | ||
759 | static int hw_set_configuration(int device_index, int capability, void *value) | |
760 | { | |
761 | struct sr_device_instance *sdi; | |
762 | struct sigma *sigma; | |
763 | int ret; | |
764 | ||
765 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) | |
766 | return SR_ERR; | |
767 | ||
768 | sigma = sdi->priv; | |
769 | ||
770 | if (capability == SR_HWCAP_SAMPLERATE) { | |
771 | ret = set_samplerate(sdi, *(uint64_t*) value); | |
772 | } else if (capability == SR_HWCAP_PROBECONFIG) { | |
773 | ret = configure_probes(sdi, value); | |
774 | } else if (capability == SR_HWCAP_LIMIT_MSEC) { | |
775 | sigma->limit_msec = *(uint64_t*) value; | |
776 | if (sigma->limit_msec > 0) | |
777 | ret = SR_OK; | |
778 | else | |
779 | ret = SR_ERR; | |
780 | } else if (capability == SR_HWCAP_CAPTURE_RATIO) { | |
781 | sigma->capture_ratio = *(uint64_t*) value; | |
782 | if (sigma->capture_ratio < 0 || sigma->capture_ratio > 100) | |
783 | ret = SR_ERR; | |
784 | else | |
785 | ret = SR_OK; | |
786 | } else { | |
787 | ret = SR_ERR; | |
788 | } | |
789 | ||
790 | return ret; | |
791 | } | |
792 | ||
793 | /* Software trigger to determine exact trigger position. */ | |
794 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
795 | struct sigma_trigger *t) | |
796 | { | |
797 | int i; | |
798 | ||
799 | for (i = 0; i < 8; ++i) { | |
800 | if (i > 0) | |
801 | last_sample = samples[i-1]; | |
802 | ||
803 | /* Simple triggers. */ | |
804 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
805 | continue; | |
806 | ||
807 | /* Rising edge. */ | |
808 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
809 | t->risingmask) != t->risingmask) | |
810 | continue; | |
811 | ||
812 | /* Falling edge. */ | |
813 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
814 | (samples[i] & t->fallingmask) != 0) | |
815 | continue; | |
816 | ||
817 | break; | |
818 | } | |
819 | ||
820 | /* If we did not match, return original trigger pos. */ | |
821 | return i & 0x7; | |
822 | } | |
823 | ||
824 | /* | |
825 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
826 | * Each event is 20ns apart, and can contain multiple samples. | |
827 | * | |
828 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
829 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
830 | * For 50 MHz and below, events contain one sample for each channel, | |
831 | * spread 20 ns apart. | |
832 | */ | |
833 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
834 | uint16_t *lastsample, int triggerpos, | |
835 | uint16_t limit_chunk, void *user_data) | |
836 | { | |
837 | struct sr_device_instance *sdi = user_data; | |
838 | struct sigma *sigma = sdi->priv; | |
839 | uint16_t tsdiff, ts; | |
840 | uint16_t samples[65536 * sigma->samples_per_event]; | |
841 | struct sr_datafeed_packet packet; | |
842 | int i, j, k, l, numpad, tosend; | |
843 | size_t n = 0, sent = 0; | |
844 | int clustersize = EVENTS_PER_CLUSTER * sigma->samples_per_event; | |
845 | uint16_t *event; | |
846 | uint16_t cur_sample; | |
847 | int triggerts = -1; | |
848 | ||
849 | /* Check if trigger is in this chunk. */ | |
850 | if (triggerpos != -1) { | |
851 | if (sigma->cur_samplerate <= SR_MHZ(50)) | |
852 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
853 | ||
854 | if (triggerpos < 0) | |
855 | triggerpos = 0; | |
856 | ||
857 | /* Find in which cluster the trigger occured. */ | |
858 | triggerts = triggerpos / 7; | |
859 | } | |
860 | ||
861 | /* For each ts. */ | |
862 | for (i = 0; i < 64; ++i) { | |
863 | ts = *(uint16_t *) &buf[i * 16]; | |
864 | tsdiff = ts - *lastts; | |
865 | *lastts = ts; | |
866 | ||
867 | /* Decode partial chunk. */ | |
868 | if (limit_chunk && ts > limit_chunk) | |
869 | return SR_OK; | |
870 | ||
871 | /* Pad last sample up to current point. */ | |
872 | numpad = tsdiff * sigma->samples_per_event - clustersize; | |
873 | if (numpad > 0) { | |
874 | for (j = 0; j < numpad; ++j) | |
875 | samples[j] = *lastsample; | |
876 | ||
877 | n = numpad; | |
878 | } | |
879 | ||
880 | /* Send samples between previous and this timestamp to sigrok. */ | |
881 | sent = 0; | |
882 | while (sent < n) { | |
883 | tosend = MIN(2048, n - sent); | |
884 | ||
885 | packet.type = SR_DF_LOGIC; | |
886 | packet.length = tosend * sizeof(uint16_t); | |
887 | packet.unitsize = 2; | |
888 | packet.payload = samples + sent; | |
889 | sr_session_bus(sigma->session_id, &packet); | |
890 | ||
891 | sent += tosend; | |
892 | } | |
893 | n = 0; | |
894 | ||
895 | event = (uint16_t *) &buf[i * 16 + 2]; | |
896 | cur_sample = 0; | |
897 | ||
898 | /* For each event in cluster. */ | |
899 | for (j = 0; j < 7; ++j) { | |
900 | ||
901 | /* For each sample in event. */ | |
902 | for (k = 0; k < sigma->samples_per_event; ++k) { | |
903 | cur_sample = 0; | |
904 | ||
905 | /* For each probe. */ | |
906 | for (l = 0; l < sigma->num_probes; ++l) | |
907 | cur_sample |= (!!(event[j] & (1 << (l * | |
908 | sigma->samples_per_event | |
909 | + k)))) | |
910 | << l; | |
911 | ||
912 | samples[n++] = cur_sample; | |
913 | } | |
914 | } | |
915 | ||
916 | /* Send data up to trigger point (if triggered). */ | |
917 | sent = 0; | |
918 | if (i == triggerts) { | |
919 | /* | |
920 | * Trigger is not always accurate to sample because of | |
921 | * pipeline delay. However, it always triggers before | |
922 | * the actual event. We therefore look at the next | |
923 | * samples to pinpoint the exact position of the trigger. | |
924 | */ | |
925 | tosend = get_trigger_offset(samples, *lastsample, | |
926 | &sigma->trigger); | |
927 | ||
928 | if (tosend > 0) { | |
929 | packet.type = SR_DF_LOGIC; | |
930 | packet.length = tosend * sizeof(uint16_t); | |
931 | packet.unitsize = 2; | |
932 | packet.payload = samples; | |
933 | sr_session_bus(sigma->session_id, &packet); | |
934 | ||
935 | sent += tosend; | |
936 | } | |
937 | ||
938 | /* Only send trigger if explicitly enabled. */ | |
939 | if (sigma->use_triggers) { | |
940 | packet.type = SR_DF_TRIGGER; | |
941 | packet.length = 0; | |
942 | packet.payload = 0; | |
943 | sr_session_bus(sigma->session_id, &packet); | |
944 | } | |
945 | } | |
946 | ||
947 | /* Send rest of the chunk to sigrok. */ | |
948 | tosend = n - sent; | |
949 | ||
950 | if (tosend > 0) { | |
951 | packet.type = SR_DF_LOGIC; | |
952 | packet.length = tosend * sizeof(uint16_t); | |
953 | packet.unitsize = 2; | |
954 | packet.payload = samples + sent; | |
955 | sr_session_bus(sigma->session_id, &packet); | |
956 | } | |
957 | ||
958 | *lastsample = samples[n - 1]; | |
959 | } | |
960 | ||
961 | return SR_OK; | |
962 | } | |
963 | ||
964 | static int receive_data(int fd, int revents, void *user_data) | |
965 | { | |
966 | struct sr_device_instance *sdi = user_data; | |
967 | struct sigma *sigma = sdi->priv; | |
968 | struct sr_datafeed_packet packet; | |
969 | const int chunks_per_read = 32; | |
970 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
971 | int bufsz, numchunks, i, newchunks; | |
972 | uint64_t running_msec; | |
973 | struct timeval tv; | |
974 | ||
975 | fd = fd; | |
976 | revents = revents; | |
977 | ||
978 | numchunks = (sigma->state.stoppos + 511) / 512; | |
979 | ||
980 | if (sigma->state.state == SIGMA_IDLE) | |
981 | return FALSE; | |
982 | ||
983 | if (sigma->state.state == SIGMA_CAPTURE) { | |
984 | ||
985 | /* Check if the timer has expired, or memory is full. */ | |
986 | gettimeofday(&tv, 0); | |
987 | running_msec = (tv.tv_sec - sigma->start_tv.tv_sec) * 1000 + | |
988 | (tv.tv_usec - sigma->start_tv.tv_usec) / 1000; | |
989 | ||
990 | if (running_msec < sigma->limit_msec && numchunks < 32767) | |
991 | return FALSE; | |
992 | ||
993 | hw_stop_acquisition(sdi->index, user_data); | |
994 | ||
995 | return FALSE; | |
996 | ||
997 | } else if (sigma->state.state == SIGMA_DOWNLOAD) { | |
998 | if (sigma->state.chunks_downloaded >= numchunks) { | |
999 | /* End of samples. */ | |
1000 | packet.type = SR_DF_END; | |
1001 | packet.length = 0; | |
1002 | sr_session_bus(sigma->session_id, &packet); | |
1003 | ||
1004 | sigma->state.state = SIGMA_IDLE; | |
1005 | ||
1006 | return TRUE; | |
1007 | } | |
1008 | ||
1009 | newchunks = MIN(chunks_per_read, | |
1010 | numchunks - sigma->state.chunks_downloaded); | |
1011 | ||
1012 | sr_info("Downloading sample data: %.0f %%", | |
1013 | 100.0 * sigma->state.chunks_downloaded / numchunks); | |
1014 | ||
1015 | bufsz = sigma_read_dram(sigma->state.chunks_downloaded, | |
1016 | newchunks, buf, sigma); | |
1017 | ||
1018 | /* Find first ts. */ | |
1019 | if (sigma->state.chunks_downloaded == 0) { | |
1020 | sigma->state.lastts = *(uint16_t *) buf - 1; | |
1021 | sigma->state.lastsample = 0; | |
1022 | } | |
1023 | ||
1024 | /* Decode chunks and send them to sigrok. */ | |
1025 | for (i = 0; i < newchunks; ++i) { | |
1026 | int limit_chunk = 0; | |
1027 | ||
1028 | /* The last chunk may potentially be only in part. */ | |
1029 | if (sigma->state.chunks_downloaded == numchunks - 1) | |
1030 | { | |
1031 | /* Find the last valid timestamp */ | |
1032 | limit_chunk = sigma->state.stoppos % 512 + sigma->state.lastts; | |
1033 | } | |
1034 | ||
1035 | if (sigma->state.chunks_downloaded + i == sigma->state.triggerchunk) | |
1036 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1037 | &sigma->state.lastts, | |
1038 | &sigma->state.lastsample, | |
1039 | sigma->state.triggerpos & 0x1ff, | |
1040 | limit_chunk, user_data); | |
1041 | else | |
1042 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1043 | &sigma->state.lastts, | |
1044 | &sigma->state.lastsample, | |
1045 | -1, limit_chunk, user_data); | |
1046 | ||
1047 | ++sigma->state.chunks_downloaded; | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | return TRUE; | |
1052 | } | |
1053 | ||
1054 | /* Build a LUT entry used by the trigger functions. */ | |
1055 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1056 | { | |
1057 | int i, j, k, bit; | |
1058 | ||
1059 | /* For each quad probe. */ | |
1060 | for (i = 0; i < 4; ++i) { | |
1061 | entry[i] = 0xffff; | |
1062 | ||
1063 | /* For each bit in LUT. */ | |
1064 | for (j = 0; j < 16; ++j) | |
1065 | ||
1066 | /* For each probe in quad. */ | |
1067 | for (k = 0; k < 4; ++k) { | |
1068 | bit = 1 << (i * 4 + k); | |
1069 | ||
1070 | /* Set bit in entry */ | |
1071 | if ((mask & bit) && | |
1072 | ((!(value & bit)) != | |
1073 | (!(j & (1 << k))))) | |
1074 | entry[i] &= ~(1 << j); | |
1075 | } | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | /* Add a logical function to LUT mask. */ | |
1080 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1081 | int index, int neg, uint16_t *mask) | |
1082 | { | |
1083 | int i, j; | |
1084 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1085 | ||
1086 | memset(x, 0, 4 * sizeof(int)); | |
1087 | ||
1088 | /* Trigger detect condition. */ | |
1089 | switch (oper) { | |
1090 | case OP_LEVEL: | |
1091 | x[0][1] = 1; | |
1092 | x[1][1] = 1; | |
1093 | break; | |
1094 | case OP_NOT: | |
1095 | x[0][0] = 1; | |
1096 | x[1][0] = 1; | |
1097 | break; | |
1098 | case OP_RISE: | |
1099 | x[0][1] = 1; | |
1100 | break; | |
1101 | case OP_FALL: | |
1102 | x[1][0] = 1; | |
1103 | break; | |
1104 | case OP_RISEFALL: | |
1105 | x[0][1] = 1; | |
1106 | x[1][0] = 1; | |
1107 | break; | |
1108 | case OP_NOTRISE: | |
1109 | x[1][1] = 1; | |
1110 | x[0][0] = 1; | |
1111 | x[1][0] = 1; | |
1112 | break; | |
1113 | case OP_NOTFALL: | |
1114 | x[1][1] = 1; | |
1115 | x[0][0] = 1; | |
1116 | x[0][1] = 1; | |
1117 | break; | |
1118 | case OP_NOTRISEFALL: | |
1119 | x[1][1] = 1; | |
1120 | x[0][0] = 1; | |
1121 | break; | |
1122 | } | |
1123 | ||
1124 | /* Transpose if neg is set. */ | |
1125 | if (neg) { | |
1126 | for (i = 0; i < 2; ++i) | |
1127 | for (j = 0; j < 2; ++j) { | |
1128 | tmp = x[i][j]; | |
1129 | x[i][j] = x[1-i][1-j]; | |
1130 | x[1-i][1-j] = tmp; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | /* Update mask with function. */ | |
1135 | for (i = 0; i < 16; ++i) { | |
1136 | a = (i >> (2 * index + 0)) & 1; | |
1137 | b = (i >> (2 * index + 1)) & 1; | |
1138 | ||
1139 | aset = (*mask >> i) & 1; | |
1140 | bset = x[b][a]; | |
1141 | ||
1142 | if (func == FUNC_AND || func == FUNC_NAND) | |
1143 | rset = aset & bset; | |
1144 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1145 | rset = aset | bset; | |
1146 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1147 | rset = aset ^ bset; | |
1148 | ||
1149 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1150 | rset = !rset; | |
1151 | ||
1152 | *mask &= ~(1 << i); | |
1153 | ||
1154 | if (rset) | |
1155 | *mask |= 1 << i; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | /* | |
1160 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1161 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1162 | * set at any time, but a full mask and value can be set (0/1). | |
1163 | */ | |
1164 | static int build_basic_trigger(struct triggerlut *lut, struct sigma *sigma) | |
1165 | { | |
1166 | int i,j; | |
1167 | uint16_t masks[2] = { 0, 0 }; | |
1168 | ||
1169 | memset(lut, 0, sizeof(struct triggerlut)); | |
1170 | ||
1171 | /* Contant for simple triggers. */ | |
1172 | lut->m4 = 0xa000; | |
1173 | ||
1174 | /* Value/mask trigger support. */ | |
1175 | build_lut_entry(sigma->trigger.simplevalue, sigma->trigger.simplemask, | |
1176 | lut->m2d); | |
1177 | ||
1178 | /* Rise/fall trigger support. */ | |
1179 | for (i = 0, j = 0; i < 16; ++i) { | |
1180 | if (sigma->trigger.risingmask & (1 << i) || | |
1181 | sigma->trigger.fallingmask & (1 << i)) | |
1182 | masks[j++] = 1 << i; | |
1183 | } | |
1184 | ||
1185 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1186 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1187 | ||
1188 | /* Add glue logic */ | |
1189 | if (masks[0] || masks[1]) { | |
1190 | /* Transition trigger. */ | |
1191 | if (masks[0] & sigma->trigger.risingmask) | |
1192 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1193 | if (masks[0] & sigma->trigger.fallingmask) | |
1194 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1195 | if (masks[1] & sigma->trigger.risingmask) | |
1196 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1197 | if (masks[1] & sigma->trigger.fallingmask) | |
1198 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1199 | } else { | |
1200 | /* Only value/mask trigger. */ | |
1201 | lut->m3 = 0xffff; | |
1202 | } | |
1203 | ||
1204 | /* Triggertype: event. */ | |
1205 | lut->params.selres = 3; | |
1206 | ||
1207 | return SR_OK; | |
1208 | } | |
1209 | ||
1210 | static int hw_start_acquisition(int device_index, gpointer session_device_id) | |
1211 | { | |
1212 | struct sr_device_instance *sdi; | |
1213 | struct sigma *sigma; | |
1214 | struct sr_datafeed_packet packet; | |
1215 | struct sr_datafeed_header header; | |
1216 | struct clockselect_50 clockselect; | |
1217 | int frac, triggerpin, ret; | |
1218 | uint8_t triggerselect; | |
1219 | struct triggerinout triggerinout_conf; | |
1220 | struct triggerlut lut; | |
1221 | ||
1222 | session_device_id = session_device_id; | |
1223 | ||
1224 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) | |
1225 | return SR_ERR; | |
1226 | ||
1227 | sigma = sdi->priv; | |
1228 | ||
1229 | /* If the samplerate has not been set, default to 200 KHz. */ | |
1230 | if (sigma->cur_firmware == -1) { | |
1231 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1232 | return ret; | |
1233 | } | |
1234 | ||
1235 | /* Enter trigger programming mode. */ | |
1236 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, sigma); | |
1237 | ||
1238 | /* 100 and 200 MHz mode. */ | |
1239 | if (sigma->cur_samplerate >= SR_MHZ(100)) { | |
1240 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, sigma); | |
1241 | ||
1242 | /* Find which pin to trigger on from mask. */ | |
1243 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1244 | if ((sigma->trigger.risingmask | sigma->trigger.fallingmask) & | |
1245 | (1 << triggerpin)) | |
1246 | break; | |
1247 | ||
1248 | /* Set trigger pin and light LED on trigger. */ | |
1249 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1250 | ||
1251 | /* Default rising edge. */ | |
1252 | if (sigma->trigger.fallingmask) | |
1253 | triggerselect |= 1 << 3; | |
1254 | ||
1255 | /* All other modes. */ | |
1256 | } else if (sigma->cur_samplerate <= SR_MHZ(50)) { | |
1257 | build_basic_trigger(&lut, sigma); | |
1258 | ||
1259 | sigma_write_trigger_lut(&lut, sigma); | |
1260 | ||
1261 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1262 | } | |
1263 | ||
1264 | /* Setup trigger in and out pins to default values. */ | |
1265 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1266 | triggerinout_conf.trgout_bytrigger = 1; | |
1267 | triggerinout_conf.trgout_enable = 1; | |
1268 | ||
1269 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1270 | (uint8_t *) &triggerinout_conf, | |
1271 | sizeof(struct triggerinout), sigma); | |
1272 | ||
1273 | /* Go back to normal mode. */ | |
1274 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, sigma); | |
1275 | ||
1276 | /* Set clock select register. */ | |
1277 | if (sigma->cur_samplerate == SR_MHZ(200)) | |
1278 | /* Enable 4 probes. */ | |
1279 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, sigma); | |
1280 | else if (sigma->cur_samplerate == SR_MHZ(100)) | |
1281 | /* Enable 8 probes. */ | |
1282 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, sigma); | |
1283 | else { | |
1284 | /* | |
1285 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1286 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1287 | */ | |
1288 | frac = SR_MHZ(50) / sigma->cur_samplerate - 1; | |
1289 | ||
1290 | clockselect.async = 0; | |
1291 | clockselect.fraction = frac; | |
1292 | clockselect.disabled_probes = 0; | |
1293 | ||
1294 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1295 | (uint8_t *) &clockselect, | |
1296 | sizeof(clockselect), sigma); | |
1297 | } | |
1298 | ||
1299 | /* Setup maximum post trigger time. */ | |
1300 | sigma_set_register(WRITE_POST_TRIGGER, | |
1301 | (sigma->capture_ratio * 255) / 100, sigma); | |
1302 | ||
1303 | /* Start acqusition. */ | |
1304 | gettimeofday(&sigma->start_tv, 0); | |
1305 | sigma_set_register(WRITE_MODE, 0x0d, sigma); | |
1306 | ||
1307 | sigma->session_id = session_device_id; | |
1308 | ||
1309 | /* Send header packet to the session bus. */ | |
1310 | packet.type = SR_DF_HEADER; | |
1311 | packet.length = sizeof(struct sr_datafeed_header); | |
1312 | packet.payload = &header; | |
1313 | header.feed_version = 1; | |
1314 | gettimeofday(&header.starttime, NULL); | |
1315 | header.samplerate = sigma->cur_samplerate; | |
1316 | header.protocol_id = SR_PROTO_RAW; | |
1317 | header.num_logic_probes = sigma->num_probes; | |
1318 | header.num_analog_probes = 0; | |
1319 | sr_session_bus(session_device_id, &packet); | |
1320 | ||
1321 | /* Add capture source. */ | |
1322 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); | |
1323 | ||
1324 | sigma->state.state = SIGMA_CAPTURE; | |
1325 | ||
1326 | return SR_OK; | |
1327 | } | |
1328 | ||
1329 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) | |
1330 | { | |
1331 | struct sr_device_instance *sdi; | |
1332 | struct sigma *sigma; | |
1333 | uint8_t modestatus; | |
1334 | ||
1335 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) | |
1336 | return; | |
1337 | ||
1338 | sigma = sdi->priv; | |
1339 | ||
1340 | session_device_id = session_device_id; | |
1341 | ||
1342 | /* Stop acquisition. */ | |
1343 | sigma_set_register(WRITE_MODE, 0x11, sigma); | |
1344 | ||
1345 | /* Set SDRAM Read Enable. */ | |
1346 | sigma_set_register(WRITE_MODE, 0x02, sigma); | |
1347 | ||
1348 | /* Get the current position. */ | |
1349 | sigma_read_pos(&sigma->state.stoppos, &sigma->state.triggerpos, sigma); | |
1350 | ||
1351 | /* Check if trigger has fired. */ | |
1352 | modestatus = sigma_get_register(READ_MODE, sigma); | |
1353 | if (modestatus & 0x20) { | |
1354 | sigma->state.triggerchunk = sigma->state.triggerpos / 512; | |
1355 | ||
1356 | } else | |
1357 | sigma->state.triggerchunk = -1; | |
1358 | ||
1359 | sigma->state.chunks_downloaded = 0; | |
1360 | ||
1361 | sigma->state.state = SIGMA_DOWNLOAD; | |
1362 | } | |
1363 | ||
1364 | struct sr_device_plugin asix_sigma_plugin_info = { | |
1365 | "asix-sigma", | |
1366 | "ASIX SIGMA", | |
1367 | 1, | |
1368 | hw_init, | |
1369 | hw_cleanup, | |
1370 | hw_opendev, | |
1371 | hw_closedev, | |
1372 | hw_get_device_info, | |
1373 | hw_get_status, | |
1374 | hw_get_capabilities, | |
1375 | hw_set_configuration, | |
1376 | hw_start_acquisition, | |
1377 | hw_stop_acquisition, | |
1378 | }; |