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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include "libsigrok.h" | |
31 | #include "libsigrok-internal.h" | |
32 | #include "asix-sigma.h" | |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define TRIGGER_TYPE "rf10" | |
40 | ||
41 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; | |
42 | static struct sr_dev_driver *di = &asix_sigma_driver_info; | |
43 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); | |
44 | ||
45 | /* | |
46 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
47 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
48 | * very precise sampling rate selection. This driver supports only | |
49 | * a subset of the sampling rates. | |
50 | */ | |
51 | static const uint64_t samplerates[] = { | |
52 | SR_KHZ(200), /* div=250 */ | |
53 | SR_KHZ(250), /* div=200 */ | |
54 | SR_KHZ(500), /* div=100 */ | |
55 | SR_MHZ(1), /* div=50 */ | |
56 | SR_MHZ(5), /* div=10 */ | |
57 | SR_MHZ(10), /* div=5 */ | |
58 | SR_MHZ(25), /* div=2 */ | |
59 | SR_MHZ(50), /* div=1 */ | |
60 | SR_MHZ(100), /* Special FW needed */ | |
61 | SR_MHZ(200), /* Special FW needed */ | |
62 | }; | |
63 | ||
64 | /* | |
65 | * Channel numbers seem to go from 1-16, according to this image: | |
66 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
67 | * (the cable has two additional GND pins, and a TI and TO pin) | |
68 | */ | |
69 | static const char *channel_names[] = { | |
70 | "1", "2", "3", "4", "5", "6", "7", "8", | |
71 | "9", "10", "11", "12", "13", "14", "15", "16", | |
72 | }; | |
73 | ||
74 | static const int32_t hwcaps[] = { | |
75 | SR_CONF_LOGIC_ANALYZER, | |
76 | SR_CONF_SAMPLERATE, | |
77 | SR_CONF_TRIGGER_TYPE, | |
78 | SR_CONF_CAPTURE_RATIO, | |
79 | SR_CONF_LIMIT_MSEC, | |
80 | SR_CONF_LIMIT_SAMPLES, | |
81 | }; | |
82 | ||
83 | static const char *sigma_firmware_files[] = { | |
84 | /* 50 MHz, supports 8 bit fractions */ | |
85 | FIRMWARE_DIR "/asix-sigma-50.fw", | |
86 | /* 100 MHz */ | |
87 | FIRMWARE_DIR "/asix-sigma-100.fw", | |
88 | /* 200 MHz */ | |
89 | FIRMWARE_DIR "/asix-sigma-200.fw", | |
90 | /* Synchronous clock from pin */ | |
91 | FIRMWARE_DIR "/asix-sigma-50sync.fw", | |
92 | /* Frequency counter */ | |
93 | FIRMWARE_DIR "/asix-sigma-phasor.fw", | |
94 | }; | |
95 | ||
96 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
97 | { | |
98 | int ret; | |
99 | ||
100 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
101 | if (ret < 0) { | |
102 | sr_err("ftdi_read_data failed: %s", | |
103 | ftdi_get_error_string(&devc->ftdic)); | |
104 | } | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
109 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
110 | { | |
111 | int ret; | |
112 | ||
113 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
114 | if (ret < 0) { | |
115 | sr_err("ftdi_write_data failed: %s", | |
116 | ftdi_get_error_string(&devc->ftdic)); | |
117 | } else if ((size_t) ret != size) { | |
118 | sr_err("ftdi_write_data did not complete write."); | |
119 | } | |
120 | ||
121 | return ret; | |
122 | } | |
123 | ||
124 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
125 | struct dev_context *devc) | |
126 | { | |
127 | size_t i; | |
128 | uint8_t buf[len + 2]; | |
129 | int idx = 0; | |
130 | ||
131 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
132 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
133 | ||
134 | for (i = 0; i < len; ++i) { | |
135 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
136 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
137 | } | |
138 | ||
139 | return sigma_write(buf, idx, devc); | |
140 | } | |
141 | ||
142 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
143 | { | |
144 | return sigma_write_register(reg, &value, 1, devc); | |
145 | } | |
146 | ||
147 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
148 | struct dev_context *devc) | |
149 | { | |
150 | uint8_t buf[3]; | |
151 | ||
152 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
153 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
154 | buf[2] = REG_READ_ADDR; | |
155 | ||
156 | sigma_write(buf, sizeof(buf), devc); | |
157 | ||
158 | return sigma_read(data, len, devc); | |
159 | } | |
160 | ||
161 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
162 | { | |
163 | uint8_t value; | |
164 | ||
165 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
166 | sr_err("sigma_get_register: 1 byte expected"); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | return value; | |
171 | } | |
172 | ||
173 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
174 | struct dev_context *devc) | |
175 | { | |
176 | uint8_t buf[] = { | |
177 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
178 | ||
179 | REG_READ_ADDR | NEXT_REG, | |
180 | REG_READ_ADDR | NEXT_REG, | |
181 | REG_READ_ADDR | NEXT_REG, | |
182 | REG_READ_ADDR | NEXT_REG, | |
183 | REG_READ_ADDR | NEXT_REG, | |
184 | REG_READ_ADDR | NEXT_REG, | |
185 | }; | |
186 | uint8_t result[6]; | |
187 | ||
188 | sigma_write(buf, sizeof(buf), devc); | |
189 | ||
190 | sigma_read(result, sizeof(result), devc); | |
191 | ||
192 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
193 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
194 | ||
195 | /* Not really sure why this must be done, but according to spec. */ | |
196 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
197 | stoppos -= 64; | |
198 | ||
199 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
200 | triggerpos -= 64; | |
201 | ||
202 | return 1; | |
203 | } | |
204 | ||
205 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
206 | uint8_t *data, struct dev_context *devc) | |
207 | { | |
208 | size_t i; | |
209 | uint8_t buf[4096]; | |
210 | int idx = 0; | |
211 | ||
212 | /* Send the startchunk. Index start with 1. */ | |
213 | buf[0] = startchunk >> 8; | |
214 | buf[1] = startchunk & 0xff; | |
215 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
216 | ||
217 | /* Read the DRAM. */ | |
218 | buf[idx++] = REG_DRAM_BLOCK; | |
219 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
220 | ||
221 | for (i = 0; i < numchunks; ++i) { | |
222 | /* Alternate bit to copy from DRAM to cache. */ | |
223 | if (i != (numchunks - 1)) | |
224 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
225 | ||
226 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
227 | ||
228 | if (i != (numchunks - 1)) | |
229 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
230 | } | |
231 | ||
232 | sigma_write(buf, idx, devc); | |
233 | ||
234 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
235 | } | |
236 | ||
237 | /* Upload trigger look-up tables to Sigma. */ | |
238 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
239 | { | |
240 | int i; | |
241 | uint8_t tmp[2]; | |
242 | uint16_t bit; | |
243 | ||
244 | /* Transpose the table and send to Sigma. */ | |
245 | for (i = 0; i < 16; ++i) { | |
246 | bit = 1 << i; | |
247 | ||
248 | tmp[0] = tmp[1] = 0; | |
249 | ||
250 | if (lut->m2d[0] & bit) | |
251 | tmp[0] |= 0x01; | |
252 | if (lut->m2d[1] & bit) | |
253 | tmp[0] |= 0x02; | |
254 | if (lut->m2d[2] & bit) | |
255 | tmp[0] |= 0x04; | |
256 | if (lut->m2d[3] & bit) | |
257 | tmp[0] |= 0x08; | |
258 | ||
259 | if (lut->m3 & bit) | |
260 | tmp[0] |= 0x10; | |
261 | if (lut->m3s & bit) | |
262 | tmp[0] |= 0x20; | |
263 | if (lut->m4 & bit) | |
264 | tmp[0] |= 0x40; | |
265 | ||
266 | if (lut->m0d[0] & bit) | |
267 | tmp[1] |= 0x01; | |
268 | if (lut->m0d[1] & bit) | |
269 | tmp[1] |= 0x02; | |
270 | if (lut->m0d[2] & bit) | |
271 | tmp[1] |= 0x04; | |
272 | if (lut->m0d[3] & bit) | |
273 | tmp[1] |= 0x08; | |
274 | ||
275 | if (lut->m1d[0] & bit) | |
276 | tmp[1] |= 0x10; | |
277 | if (lut->m1d[1] & bit) | |
278 | tmp[1] |= 0x20; | |
279 | if (lut->m1d[2] & bit) | |
280 | tmp[1] |= 0x40; | |
281 | if (lut->m1d[3] & bit) | |
282 | tmp[1] |= 0x80; | |
283 | ||
284 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
285 | devc); | |
286 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
287 | } | |
288 | ||
289 | /* Send the parameters */ | |
290 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
291 | sizeof(lut->params), devc); | |
292 | ||
293 | return SR_OK; | |
294 | } | |
295 | ||
296 | static void clear_helper(void *priv) | |
297 | { | |
298 | struct dev_context *devc; | |
299 | ||
300 | devc = priv; | |
301 | ||
302 | ftdi_deinit(&devc->ftdic); | |
303 | } | |
304 | ||
305 | static int dev_clear(void) | |
306 | { | |
307 | return std_dev_clear(di, clear_helper); | |
308 | } | |
309 | ||
310 | static int init(struct sr_context *sr_ctx) | |
311 | { | |
312 | return std_init(sr_ctx, di, LOG_PREFIX); | |
313 | } | |
314 | ||
315 | static GSList *scan(GSList *options) | |
316 | { | |
317 | struct sr_dev_inst *sdi; | |
318 | struct sr_channel *ch; | |
319 | struct drv_context *drvc; | |
320 | struct dev_context *devc; | |
321 | GSList *devices; | |
322 | struct ftdi_device_list *devlist; | |
323 | char serial_txt[10]; | |
324 | uint32_t serial; | |
325 | int ret; | |
326 | unsigned int i; | |
327 | ||
328 | (void)options; | |
329 | ||
330 | drvc = di->priv; | |
331 | ||
332 | devices = NULL; | |
333 | ||
334 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { | |
335 | sr_err("%s: devc malloc failed", __func__); | |
336 | return NULL; | |
337 | } | |
338 | ||
339 | ftdi_init(&devc->ftdic); | |
340 | ||
341 | /* Look for SIGMAs. */ | |
342 | ||
343 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, | |
344 | USB_VENDOR, USB_PRODUCT)) <= 0) { | |
345 | if (ret < 0) | |
346 | sr_err("ftdi_usb_find_all(): %d", ret); | |
347 | goto free; | |
348 | } | |
349 | ||
350 | /* Make sure it's a version 1 or 2 SIGMA. */ | |
351 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
352 | serial_txt, sizeof(serial_txt)); | |
353 | sscanf(serial_txt, "%x", &serial); | |
354 | ||
355 | if (serial < 0xa6010000 || serial > 0xa602ffff) { | |
356 | sr_err("Only SIGMA and SIGMA2 are supported " | |
357 | "in this version of libsigrok."); | |
358 | goto free; | |
359 | } | |
360 | ||
361 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
362 | ||
363 | devc->cur_samplerate = 0; | |
364 | devc->period_ps = 0; | |
365 | devc->limit_msec = 0; | |
366 | devc->cur_firmware = -1; | |
367 | devc->num_channels = 0; | |
368 | devc->samples_per_event = 0; | |
369 | devc->capture_ratio = 50; | |
370 | devc->use_triggers = 0; | |
371 | ||
372 | /* Register SIGMA device. */ | |
373 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
374 | USB_MODEL_NAME, NULL))) { | |
375 | sr_err("%s: sdi was NULL", __func__); | |
376 | goto free; | |
377 | } | |
378 | sdi->driver = di; | |
379 | ||
380 | for (i = 0; i < ARRAY_SIZE(channel_names); i++) { | |
381 | ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, | |
382 | channel_names[i]); | |
383 | if (!ch) | |
384 | return NULL; | |
385 | sdi->channels = g_slist_append(sdi->channels, ch); | |
386 | } | |
387 | ||
388 | devices = g_slist_append(devices, sdi); | |
389 | drvc->instances = g_slist_append(drvc->instances, sdi); | |
390 | sdi->priv = devc; | |
391 | ||
392 | /* We will open the device again when we need it. */ | |
393 | ftdi_list_free(&devlist); | |
394 | ||
395 | return devices; | |
396 | ||
397 | free: | |
398 | ftdi_deinit(&devc->ftdic); | |
399 | g_free(devc); | |
400 | return NULL; | |
401 | } | |
402 | ||
403 | static GSList *dev_list(void) | |
404 | { | |
405 | return ((struct drv_context *)(di->priv))->instances; | |
406 | } | |
407 | ||
408 | /* | |
409 | * Configure the FPGA for bitbang mode. | |
410 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
411 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
412 | * into Bitbang mode, in which it can be programmed with the firmware. | |
413 | */ | |
414 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
415 | { | |
416 | uint8_t suicide[] = { | |
417 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
418 | }; | |
419 | uint8_t init_array[] = { | |
420 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
421 | 0x01, 0x01, | |
422 | }; | |
423 | int i, ret, timeout = 10000; | |
424 | uint8_t data; | |
425 | ||
426 | /* Section 2. part 1), do the FPGA suicide. */ | |
427 | sigma_write(suicide, sizeof(suicide), devc); | |
428 | sigma_write(suicide, sizeof(suicide), devc); | |
429 | sigma_write(suicide, sizeof(suicide), devc); | |
430 | sigma_write(suicide, sizeof(suicide), devc); | |
431 | ||
432 | /* Section 2. part 2), do pulse on D1. */ | |
433 | sigma_write(init_array, sizeof(init_array), devc); | |
434 | ftdi_usb_purge_buffers(&devc->ftdic); | |
435 | ||
436 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
437 | for (i = 0; i < timeout; i++) { | |
438 | ret = sigma_read(&data, 1, devc); | |
439 | if (ret < 0) | |
440 | return ret; | |
441 | /* Test if pin D6 got asserted. */ | |
442 | if (data & (1 << 5)) | |
443 | return 0; | |
444 | /* The D6 was not asserted yet, wait a bit. */ | |
445 | usleep(10000); | |
446 | } | |
447 | ||
448 | return SR_ERR_TIMEOUT; | |
449 | } | |
450 | ||
451 | /* | |
452 | * Configure the FPGA for logic-analyzer mode. | |
453 | */ | |
454 | static int sigma_fpga_init_la(struct dev_context *devc) | |
455 | { | |
456 | /* Initialize the logic analyzer mode. */ | |
457 | uint8_t logic_mode_start[] = { | |
458 | REG_ADDR_LOW | (READ_ID & 0xf), | |
459 | REG_ADDR_HIGH | (READ_ID >> 8), | |
460 | REG_READ_ADDR, /* Read ID register. */ | |
461 | ||
462 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
463 | REG_DATA_LOW | 0x5, | |
464 | REG_DATA_HIGH_WRITE | 0x5, | |
465 | REG_READ_ADDR, /* Read scratch register. */ | |
466 | ||
467 | REG_DATA_LOW | 0xa, | |
468 | REG_DATA_HIGH_WRITE | 0xa, | |
469 | REG_READ_ADDR, /* Read scratch register. */ | |
470 | ||
471 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
472 | REG_DATA_LOW | 0x0, | |
473 | REG_DATA_HIGH_WRITE | 0x8, | |
474 | }; | |
475 | ||
476 | uint8_t result[3]; | |
477 | int ret; | |
478 | ||
479 | /* Initialize the logic analyzer mode. */ | |
480 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
481 | ||
482 | /* Expect a 3 byte reply since we issued three READ requests. */ | |
483 | ret = sigma_read(result, 3, devc); | |
484 | if (ret != 3) | |
485 | goto err; | |
486 | ||
487 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
488 | goto err; | |
489 | ||
490 | return SR_OK; | |
491 | err: | |
492 | sr_err("Configuration failed. Invalid reply received."); | |
493 | return SR_ERR; | |
494 | } | |
495 | ||
496 | /* | |
497 | * Read the firmware from a file and transform it into a series of bitbang | |
498 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
499 | * by the caller of this function. | |
500 | */ | |
501 | static int sigma_fw_2_bitbang(const char *filename, | |
502 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
503 | { | |
504 | GMappedFile *file; | |
505 | GError *error; | |
506 | gsize i, file_size, bb_size; | |
507 | gchar *firmware; | |
508 | uint8_t *bb_stream, *bbs; | |
509 | uint32_t imm; | |
510 | int bit, v; | |
511 | int ret = SR_OK; | |
512 | ||
513 | /* | |
514 | * Map the file and make the mapped buffer writable. | |
515 | * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped | |
516 | * will be modified. It will not be modified until someone uses | |
517 | * g_file_set_contents() on it. | |
518 | */ | |
519 | error = NULL; | |
520 | file = g_mapped_file_new(filename, TRUE, &error); | |
521 | g_assert_no_error(error); | |
522 | ||
523 | file_size = g_mapped_file_get_length(file); | |
524 | firmware = g_mapped_file_get_contents(file); | |
525 | g_assert(firmware); | |
526 | ||
527 | /* Weird magic transformation below, I have no idea what it does. */ | |
528 | imm = 0x3f6df2ab; | |
529 | for (i = 0; i < file_size; i++) { | |
530 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
531 | firmware[i] ^= imm & 0xff; | |
532 | } | |
533 | ||
534 | /* | |
535 | * Now that the firmware is "transformed", we will transcribe the | |
536 | * firmware blob into a sequence of toggles of the Dx wires. This | |
537 | * sequence will be fed directly into the Sigma, which must be in | |
538 | * the FPGA bitbang programming mode. | |
539 | */ | |
540 | ||
541 | /* Each bit of firmware is transcribed as two toggles of Dx wires. */ | |
542 | bb_size = file_size * 8 * 2; | |
543 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
544 | if (!bb_stream) { | |
545 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
546 | ret = SR_ERR_MALLOC; | |
547 | goto exit; | |
548 | } | |
549 | ||
550 | bbs = bb_stream; | |
551 | for (i = 0; i < file_size; i++) { | |
552 | for (bit = 7; bit >= 0; bit--) { | |
553 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
554 | *bbs++ = v | 0x01; | |
555 | *bbs++ = v; | |
556 | } | |
557 | } | |
558 | ||
559 | /* The transformation completed successfully, return the result. */ | |
560 | *bb_cmd = bb_stream; | |
561 | *bb_cmd_size = bb_size; | |
562 | ||
563 | exit: | |
564 | g_mapped_file_unref(file); | |
565 | return ret; | |
566 | } | |
567 | ||
568 | static int upload_firmware(int firmware_idx, struct dev_context *devc) | |
569 | { | |
570 | int ret; | |
571 | unsigned char *buf; | |
572 | unsigned char pins; | |
573 | size_t buf_size; | |
574 | const char *firmware = sigma_firmware_files[firmware_idx]; | |
575 | struct ftdi_context *ftdic = &devc->ftdic; | |
576 | ||
577 | /* Make sure it's an ASIX SIGMA. */ | |
578 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, | |
579 | USB_DESCRIPTION, NULL); | |
580 | if (ret < 0) { | |
581 | sr_err("ftdi_usb_open failed: %s", | |
582 | ftdi_get_error_string(ftdic)); | |
583 | return 0; | |
584 | } | |
585 | ||
586 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); | |
587 | if (ret < 0) { | |
588 | sr_err("ftdi_set_bitmode failed: %s", | |
589 | ftdi_get_error_string(ftdic)); | |
590 | return 0; | |
591 | } | |
592 | ||
593 | /* Four times the speed of sigmalogan - Works well. */ | |
594 | ret = ftdi_set_baudrate(ftdic, 750000); | |
595 | if (ret < 0) { | |
596 | sr_err("ftdi_set_baudrate failed: %s", | |
597 | ftdi_get_error_string(ftdic)); | |
598 | return 0; | |
599 | } | |
600 | ||
601 | /* Initialize the FPGA for firmware upload. */ | |
602 | ret = sigma_fpga_init_bitbang(devc); | |
603 | if (ret) | |
604 | return ret; | |
605 | ||
606 | /* Prepare firmware. */ | |
607 | ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size); | |
608 | if (ret != SR_OK) { | |
609 | sr_err("An error occured while reading the firmware: %s", | |
610 | firmware); | |
611 | return ret; | |
612 | } | |
613 | ||
614 | /* Upload firmare. */ | |
615 | sr_info("Uploading firmware file '%s'.", firmware); | |
616 | sigma_write(buf, buf_size, devc); | |
617 | ||
618 | g_free(buf); | |
619 | ||
620 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); | |
621 | if (ret < 0) { | |
622 | sr_err("ftdi_set_bitmode failed: %s", | |
623 | ftdi_get_error_string(ftdic)); | |
624 | return SR_ERR; | |
625 | } | |
626 | ||
627 | ftdi_usb_purge_buffers(ftdic); | |
628 | ||
629 | /* Discard garbage. */ | |
630 | while (sigma_read(&pins, 1, devc) == 1) | |
631 | ; | |
632 | ||
633 | /* Initialize the FPGA for logic-analyzer mode. */ | |
634 | ret = sigma_fpga_init_la(devc); | |
635 | if (ret != SR_OK) | |
636 | return ret; | |
637 | ||
638 | devc->cur_firmware = firmware_idx; | |
639 | ||
640 | sr_info("Firmware uploaded."); | |
641 | ||
642 | return SR_OK; | |
643 | } | |
644 | ||
645 | static int dev_open(struct sr_dev_inst *sdi) | |
646 | { | |
647 | struct dev_context *devc; | |
648 | int ret; | |
649 | ||
650 | devc = sdi->priv; | |
651 | ||
652 | /* Make sure it's an ASIX SIGMA. */ | |
653 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
654 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
655 | ||
656 | sr_err("ftdi_usb_open failed: %s", | |
657 | ftdi_get_error_string(&devc->ftdic)); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | sdi->status = SR_ST_ACTIVE; | |
663 | ||
664 | return SR_OK; | |
665 | } | |
666 | ||
667 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
668 | { | |
669 | struct dev_context *devc; | |
670 | unsigned int i; | |
671 | int ret; | |
672 | ||
673 | devc = sdi->priv; | |
674 | ret = SR_OK; | |
675 | ||
676 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { | |
677 | if (samplerates[i] == samplerate) | |
678 | break; | |
679 | } | |
680 | if (samplerates[i] == 0) | |
681 | return SR_ERR_SAMPLERATE; | |
682 | ||
683 | if (samplerate <= SR_MHZ(50)) { | |
684 | ret = upload_firmware(0, devc); | |
685 | devc->num_channels = 16; | |
686 | } | |
687 | if (samplerate == SR_MHZ(100)) { | |
688 | ret = upload_firmware(1, devc); | |
689 | devc->num_channels = 8; | |
690 | } | |
691 | else if (samplerate == SR_MHZ(200)) { | |
692 | ret = upload_firmware(2, devc); | |
693 | devc->num_channels = 4; | |
694 | } | |
695 | ||
696 | devc->cur_samplerate = samplerate; | |
697 | devc->period_ps = 1000000000000ULL / samplerate; | |
698 | devc->samples_per_event = 16 / devc->num_channels; | |
699 | devc->state.state = SIGMA_IDLE; | |
700 | ||
701 | return ret; | |
702 | } | |
703 | ||
704 | /* | |
705 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
706 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
707 | * in addition to value/mask trigger for any number of channels. | |
708 | * | |
709 | * The Sigma supports complex triggers using boolean expressions, but this | |
710 | * has not been implemented yet. | |
711 | */ | |
712 | static int configure_channels(const struct sr_dev_inst *sdi) | |
713 | { | |
714 | struct dev_context *devc = sdi->priv; | |
715 | const struct sr_channel *ch; | |
716 | const GSList *l; | |
717 | int trigger_set = 0; | |
718 | int channelbit; | |
719 | ||
720 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
721 | ||
722 | for (l = sdi->channels; l; l = l->next) { | |
723 | ch = (struct sr_channel *)l->data; | |
724 | channelbit = 1 << (ch->index); | |
725 | ||
726 | if (!ch->enabled || !ch->trigger) | |
727 | continue; | |
728 | ||
729 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
730 | /* Fast trigger support. */ | |
731 | if (trigger_set) { | |
732 | sr_err("Only a single pin trigger in 100 and " | |
733 | "200MHz mode is supported."); | |
734 | return SR_ERR; | |
735 | } | |
736 | if (ch->trigger[0] == 'f') | |
737 | devc->trigger.fallingmask |= channelbit; | |
738 | else if (ch->trigger[0] == 'r') | |
739 | devc->trigger.risingmask |= channelbit; | |
740 | else { | |
741 | sr_err("Only rising/falling trigger in 100 " | |
742 | "and 200MHz mode is supported."); | |
743 | return SR_ERR; | |
744 | } | |
745 | ||
746 | ++trigger_set; | |
747 | } else { | |
748 | /* Simple trigger support (event). */ | |
749 | if (ch->trigger[0] == '1') { | |
750 | devc->trigger.simplevalue |= channelbit; | |
751 | devc->trigger.simplemask |= channelbit; | |
752 | } | |
753 | else if (ch->trigger[0] == '0') { | |
754 | devc->trigger.simplevalue &= ~channelbit; | |
755 | devc->trigger.simplemask |= channelbit; | |
756 | } | |
757 | else if (ch->trigger[0] == 'f') { | |
758 | devc->trigger.fallingmask |= channelbit; | |
759 | ++trigger_set; | |
760 | } | |
761 | else if (ch->trigger[0] == 'r') { | |
762 | devc->trigger.risingmask |= channelbit; | |
763 | ++trigger_set; | |
764 | } | |
765 | ||
766 | /* | |
767 | * Actually, Sigma supports 2 rising/falling triggers, | |
768 | * but they are ORed and the current trigger syntax | |
769 | * does not permit ORed triggers. | |
770 | */ | |
771 | if (trigger_set > 1) { | |
772 | sr_err("Only 1 rising/falling trigger " | |
773 | "is supported."); | |
774 | return SR_ERR; | |
775 | } | |
776 | } | |
777 | ||
778 | if (trigger_set) | |
779 | devc->use_triggers = 1; | |
780 | } | |
781 | ||
782 | return SR_OK; | |
783 | } | |
784 | ||
785 | static int dev_close(struct sr_dev_inst *sdi) | |
786 | { | |
787 | struct dev_context *devc; | |
788 | ||
789 | devc = sdi->priv; | |
790 | ||
791 | /* TODO */ | |
792 | if (sdi->status == SR_ST_ACTIVE) | |
793 | ftdi_usb_close(&devc->ftdic); | |
794 | ||
795 | sdi->status = SR_ST_INACTIVE; | |
796 | ||
797 | return SR_OK; | |
798 | } | |
799 | ||
800 | static int cleanup(void) | |
801 | { | |
802 | return dev_clear(); | |
803 | } | |
804 | ||
805 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, | |
806 | const struct sr_channel_group *cg) | |
807 | { | |
808 | struct dev_context *devc; | |
809 | ||
810 | (void)cg; | |
811 | ||
812 | switch (id) { | |
813 | case SR_CONF_SAMPLERATE: | |
814 | if (sdi) { | |
815 | devc = sdi->priv; | |
816 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
817 | } else | |
818 | return SR_ERR; | |
819 | break; | |
820 | default: | |
821 | return SR_ERR_NA; | |
822 | } | |
823 | ||
824 | return SR_OK; | |
825 | } | |
826 | ||
827 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, | |
828 | const struct sr_channel_group *cg) | |
829 | { | |
830 | struct dev_context *devc; | |
831 | uint64_t num_samples; | |
832 | int ret; | |
833 | ||
834 | (void)cg; | |
835 | ||
836 | if (sdi->status != SR_ST_ACTIVE) | |
837 | return SR_ERR_DEV_CLOSED; | |
838 | ||
839 | devc = sdi->priv; | |
840 | ||
841 | switch (id) { | |
842 | case SR_CONF_SAMPLERATE: | |
843 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); | |
844 | break; | |
845 | case SR_CONF_LIMIT_MSEC: | |
846 | devc->limit_msec = g_variant_get_uint64(data); | |
847 | if (devc->limit_msec > 0) | |
848 | ret = SR_OK; | |
849 | else | |
850 | ret = SR_ERR; | |
851 | break; | |
852 | case SR_CONF_LIMIT_SAMPLES: | |
853 | num_samples = g_variant_get_uint64(data); | |
854 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
855 | break; | |
856 | case SR_CONF_CAPTURE_RATIO: | |
857 | devc->capture_ratio = g_variant_get_uint64(data); | |
858 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
859 | ret = SR_ERR; | |
860 | else | |
861 | ret = SR_OK; | |
862 | break; | |
863 | default: | |
864 | ret = SR_ERR_NA; | |
865 | } | |
866 | ||
867 | return ret; | |
868 | } | |
869 | ||
870 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, | |
871 | const struct sr_channel_group *cg) | |
872 | { | |
873 | GVariant *gvar; | |
874 | GVariantBuilder gvb; | |
875 | ||
876 | (void)sdi; | |
877 | (void)cg; | |
878 | ||
879 | switch (key) { | |
880 | case SR_CONF_DEVICE_OPTIONS: | |
881 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, | |
882 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
883 | break; | |
884 | case SR_CONF_SAMPLERATE: | |
885 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); | |
886 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
887 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
888 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
889 | *data = g_variant_builder_end(&gvb); | |
890 | break; | |
891 | case SR_CONF_TRIGGER_TYPE: | |
892 | *data = g_variant_new_string(TRIGGER_TYPE); | |
893 | break; | |
894 | default: | |
895 | return SR_ERR_NA; | |
896 | } | |
897 | ||
898 | return SR_OK; | |
899 | } | |
900 | ||
901 | /* Software trigger to determine exact trigger position. */ | |
902 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
903 | struct sigma_trigger *t) | |
904 | { | |
905 | int i; | |
906 | ||
907 | for (i = 0; i < 8; ++i) { | |
908 | if (i > 0) | |
909 | last_sample = samples[i-1]; | |
910 | ||
911 | /* Simple triggers. */ | |
912 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
913 | continue; | |
914 | ||
915 | /* Rising edge. */ | |
916 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
917 | t->risingmask) != t->risingmask) | |
918 | continue; | |
919 | ||
920 | /* Falling edge. */ | |
921 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
922 | (samples[i] & t->fallingmask) != 0) | |
923 | continue; | |
924 | ||
925 | break; | |
926 | } | |
927 | ||
928 | /* If we did not match, return original trigger pos. */ | |
929 | return i & 0x7; | |
930 | } | |
931 | ||
932 | /* | |
933 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
934 | * Each event is 20ns apart, and can contain multiple samples. | |
935 | * | |
936 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
937 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
938 | * For 50 MHz and below, events contain one sample for each channel, | |
939 | * spread 20 ns apart. | |
940 | */ | |
941 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
942 | uint16_t *lastsample, int triggerpos, | |
943 | uint16_t limit_chunk, void *cb_data) | |
944 | { | |
945 | struct sr_dev_inst *sdi = cb_data; | |
946 | struct dev_context *devc = sdi->priv; | |
947 | uint16_t tsdiff, ts; | |
948 | uint16_t samples[65536 * devc->samples_per_event]; | |
949 | struct sr_datafeed_packet packet; | |
950 | struct sr_datafeed_logic logic; | |
951 | int i, j, k, l, numpad, tosend; | |
952 | size_t n = 0, sent = 0; | |
953 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; | |
954 | uint16_t *event; | |
955 | uint16_t cur_sample; | |
956 | int triggerts = -1; | |
957 | ||
958 | /* Check if trigger is in this chunk. */ | |
959 | if (triggerpos != -1) { | |
960 | if (devc->cur_samplerate <= SR_MHZ(50)) | |
961 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
962 | ||
963 | if (triggerpos < 0) | |
964 | triggerpos = 0; | |
965 | ||
966 | /* Find in which cluster the trigger occured. */ | |
967 | triggerts = triggerpos / 7; | |
968 | } | |
969 | ||
970 | /* For each ts. */ | |
971 | for (i = 0; i < 64; ++i) { | |
972 | ts = *(uint16_t *) &buf[i * 16]; | |
973 | tsdiff = ts - *lastts; | |
974 | *lastts = ts; | |
975 | ||
976 | /* Decode partial chunk. */ | |
977 | if (limit_chunk && ts > limit_chunk) | |
978 | return SR_OK; | |
979 | ||
980 | /* Pad last sample up to current point. */ | |
981 | numpad = tsdiff * devc->samples_per_event - clustersize; | |
982 | if (numpad > 0) { | |
983 | for (j = 0; j < numpad; ++j) | |
984 | samples[j] = *lastsample; | |
985 | ||
986 | n = numpad; | |
987 | } | |
988 | ||
989 | /* Send samples between previous and this timestamp to sigrok. */ | |
990 | sent = 0; | |
991 | while (sent < n) { | |
992 | tosend = MIN(2048, n - sent); | |
993 | ||
994 | packet.type = SR_DF_LOGIC; | |
995 | packet.payload = &logic; | |
996 | logic.length = tosend * sizeof(uint16_t); | |
997 | logic.unitsize = 2; | |
998 | logic.data = samples + sent; | |
999 | sr_session_send(devc->cb_data, &packet); | |
1000 | ||
1001 | sent += tosend; | |
1002 | } | |
1003 | n = 0; | |
1004 | ||
1005 | event = (uint16_t *) &buf[i * 16 + 2]; | |
1006 | cur_sample = 0; | |
1007 | ||
1008 | /* For each event in cluster. */ | |
1009 | for (j = 0; j < 7; ++j) { | |
1010 | ||
1011 | /* For each sample in event. */ | |
1012 | for (k = 0; k < devc->samples_per_event; ++k) { | |
1013 | cur_sample = 0; | |
1014 | ||
1015 | /* For each channel. */ | |
1016 | for (l = 0; l < devc->num_channels; ++l) | |
1017 | cur_sample |= (!!(event[j] & (1 << (l * | |
1018 | devc->samples_per_event + k)))) << l; | |
1019 | ||
1020 | samples[n++] = cur_sample; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | /* Send data up to trigger point (if triggered). */ | |
1025 | sent = 0; | |
1026 | if (i == triggerts) { | |
1027 | /* | |
1028 | * Trigger is not always accurate to sample because of | |
1029 | * pipeline delay. However, it always triggers before | |
1030 | * the actual event. We therefore look at the next | |
1031 | * samples to pinpoint the exact position of the trigger. | |
1032 | */ | |
1033 | tosend = get_trigger_offset(samples, *lastsample, | |
1034 | &devc->trigger); | |
1035 | ||
1036 | if (tosend > 0) { | |
1037 | packet.type = SR_DF_LOGIC; | |
1038 | packet.payload = &logic; | |
1039 | logic.length = tosend * sizeof(uint16_t); | |
1040 | logic.unitsize = 2; | |
1041 | logic.data = samples; | |
1042 | sr_session_send(devc->cb_data, &packet); | |
1043 | ||
1044 | sent += tosend; | |
1045 | } | |
1046 | ||
1047 | /* Only send trigger if explicitly enabled. */ | |
1048 | if (devc->use_triggers) { | |
1049 | packet.type = SR_DF_TRIGGER; | |
1050 | sr_session_send(devc->cb_data, &packet); | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | /* Send rest of the chunk to sigrok. */ | |
1055 | tosend = n - sent; | |
1056 | ||
1057 | if (tosend > 0) { | |
1058 | packet.type = SR_DF_LOGIC; | |
1059 | packet.payload = &logic; | |
1060 | logic.length = tosend * sizeof(uint16_t); | |
1061 | logic.unitsize = 2; | |
1062 | logic.data = samples + sent; | |
1063 | sr_session_send(devc->cb_data, &packet); | |
1064 | } | |
1065 | ||
1066 | *lastsample = samples[n - 1]; | |
1067 | } | |
1068 | ||
1069 | return SR_OK; | |
1070 | } | |
1071 | ||
1072 | static void download_capture(struct sr_dev_inst *sdi) | |
1073 | { | |
1074 | struct dev_context *devc; | |
1075 | const int chunks_per_read = 32; | |
1076 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1077 | int bufsz, i, numchunks, newchunks; | |
1078 | ||
1079 | sr_info("Downloading sample data."); | |
1080 | ||
1081 | devc = sdi->priv; | |
1082 | devc->state.chunks_downloaded = 0; | |
1083 | numchunks = (devc->state.stoppos + 511) / 512; | |
1084 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1085 | ||
1086 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1087 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1088 | (void)bufsz; | |
1089 | ||
1090 | /* Find first ts. */ | |
1091 | if (devc->state.chunks_downloaded == 0) { | |
1092 | devc->state.lastts = RL16(buf) - 1; | |
1093 | devc->state.lastsample = 0; | |
1094 | } | |
1095 | ||
1096 | /* Decode chunks and send them to sigrok. */ | |
1097 | for (i = 0; i < newchunks; ++i) { | |
1098 | int limit_chunk = 0; | |
1099 | ||
1100 | /* The last chunk may potentially be only in part. */ | |
1101 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1102 | /* Find the last valid timestamp */ | |
1103 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1104 | } | |
1105 | ||
1106 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1107 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1108 | &devc->state.lastts, | |
1109 | &devc->state.lastsample, | |
1110 | devc->state.triggerpos & 0x1ff, | |
1111 | limit_chunk, sdi); | |
1112 | else | |
1113 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1114 | &devc->state.lastts, | |
1115 | &devc->state.lastsample, | |
1116 | -1, limit_chunk, sdi); | |
1117 | ||
1118 | ++devc->state.chunks_downloaded; | |
1119 | } | |
1120 | ||
1121 | } | |
1122 | ||
1123 | static int receive_data(int fd, int revents, void *cb_data) | |
1124 | { | |
1125 | struct sr_dev_inst *sdi; | |
1126 | struct dev_context *devc; | |
1127 | struct sr_datafeed_packet packet; | |
1128 | uint64_t running_msec; | |
1129 | struct timeval tv; | |
1130 | int numchunks; | |
1131 | uint8_t modestatus; | |
1132 | ||
1133 | (void)fd; | |
1134 | (void)revents; | |
1135 | ||
1136 | sdi = cb_data; | |
1137 | devc = sdi->priv; | |
1138 | ||
1139 | /* Get the current position. */ | |
1140 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1141 | ||
1142 | if (devc->state.state == SIGMA_IDLE) | |
1143 | return TRUE; | |
1144 | ||
1145 | if (devc->state.state == SIGMA_CAPTURE) { | |
1146 | numchunks = (devc->state.stoppos + 511) / 512; | |
1147 | ||
1148 | /* Check if the timer has expired, or memory is full. */ | |
1149 | gettimeofday(&tv, 0); | |
1150 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
1151 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
1152 | ||
1153 | if (running_msec < devc->limit_msec && numchunks < 32767) | |
1154 | /* Still capturing. */ | |
1155 | return TRUE; | |
1156 | ||
1157 | /* Stop acquisition. */ | |
1158 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1159 | ||
1160 | /* Set SDRAM Read Enable. */ | |
1161 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1162 | ||
1163 | /* Get the current position. */ | |
1164 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1165 | ||
1166 | /* Check if trigger has fired. */ | |
1167 | modestatus = sigma_get_register(READ_MODE, devc); | |
1168 | if (modestatus & 0x20) | |
1169 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1170 | else | |
1171 | devc->state.triggerchunk = -1; | |
1172 | ||
1173 | /* Transfer captured data from device. */ | |
1174 | download_capture(sdi); | |
1175 | ||
1176 | /* All done. */ | |
1177 | packet.type = SR_DF_END; | |
1178 | sr_session_send(sdi, &packet); | |
1179 | ||
1180 | dev_acquisition_stop(sdi, sdi); | |
1181 | } | |
1182 | ||
1183 | return TRUE; | |
1184 | } | |
1185 | ||
1186 | /* Build a LUT entry used by the trigger functions. */ | |
1187 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1188 | { | |
1189 | int i, j, k, bit; | |
1190 | ||
1191 | /* For each quad channel. */ | |
1192 | for (i = 0; i < 4; ++i) { | |
1193 | entry[i] = 0xffff; | |
1194 | ||
1195 | /* For each bit in LUT. */ | |
1196 | for (j = 0; j < 16; ++j) | |
1197 | ||
1198 | /* For each channel in quad. */ | |
1199 | for (k = 0; k < 4; ++k) { | |
1200 | bit = 1 << (i * 4 + k); | |
1201 | ||
1202 | /* Set bit in entry */ | |
1203 | if ((mask & bit) && | |
1204 | ((!(value & bit)) != | |
1205 | (!(j & (1 << k))))) | |
1206 | entry[i] &= ~(1 << j); | |
1207 | } | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* Add a logical function to LUT mask. */ | |
1212 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1213 | int index, int neg, uint16_t *mask) | |
1214 | { | |
1215 | int i, j; | |
1216 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1217 | ||
1218 | memset(x, 0, 4 * sizeof(int)); | |
1219 | ||
1220 | /* Trigger detect condition. */ | |
1221 | switch (oper) { | |
1222 | case OP_LEVEL: | |
1223 | x[0][1] = 1; | |
1224 | x[1][1] = 1; | |
1225 | break; | |
1226 | case OP_NOT: | |
1227 | x[0][0] = 1; | |
1228 | x[1][0] = 1; | |
1229 | break; | |
1230 | case OP_RISE: | |
1231 | x[0][1] = 1; | |
1232 | break; | |
1233 | case OP_FALL: | |
1234 | x[1][0] = 1; | |
1235 | break; | |
1236 | case OP_RISEFALL: | |
1237 | x[0][1] = 1; | |
1238 | x[1][0] = 1; | |
1239 | break; | |
1240 | case OP_NOTRISE: | |
1241 | x[1][1] = 1; | |
1242 | x[0][0] = 1; | |
1243 | x[1][0] = 1; | |
1244 | break; | |
1245 | case OP_NOTFALL: | |
1246 | x[1][1] = 1; | |
1247 | x[0][0] = 1; | |
1248 | x[0][1] = 1; | |
1249 | break; | |
1250 | case OP_NOTRISEFALL: | |
1251 | x[1][1] = 1; | |
1252 | x[0][0] = 1; | |
1253 | break; | |
1254 | } | |
1255 | ||
1256 | /* Transpose if neg is set. */ | |
1257 | if (neg) { | |
1258 | for (i = 0; i < 2; ++i) { | |
1259 | for (j = 0; j < 2; ++j) { | |
1260 | tmp = x[i][j]; | |
1261 | x[i][j] = x[1-i][1-j]; | |
1262 | x[1-i][1-j] = tmp; | |
1263 | } | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | /* Update mask with function. */ | |
1268 | for (i = 0; i < 16; ++i) { | |
1269 | a = (i >> (2 * index + 0)) & 1; | |
1270 | b = (i >> (2 * index + 1)) & 1; | |
1271 | ||
1272 | aset = (*mask >> i) & 1; | |
1273 | bset = x[b][a]; | |
1274 | ||
1275 | if (func == FUNC_AND || func == FUNC_NAND) | |
1276 | rset = aset & bset; | |
1277 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1278 | rset = aset | bset; | |
1279 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1280 | rset = aset ^ bset; | |
1281 | ||
1282 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1283 | rset = !rset; | |
1284 | ||
1285 | *mask &= ~(1 << i); | |
1286 | ||
1287 | if (rset) | |
1288 | *mask |= 1 << i; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | /* | |
1293 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1294 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1295 | * set at any time, but a full mask and value can be set (0/1). | |
1296 | */ | |
1297 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1298 | { | |
1299 | int i,j; | |
1300 | uint16_t masks[2] = { 0, 0 }; | |
1301 | ||
1302 | memset(lut, 0, sizeof(struct triggerlut)); | |
1303 | ||
1304 | /* Contant for simple triggers. */ | |
1305 | lut->m4 = 0xa000; | |
1306 | ||
1307 | /* Value/mask trigger support. */ | |
1308 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1309 | lut->m2d); | |
1310 | ||
1311 | /* Rise/fall trigger support. */ | |
1312 | for (i = 0, j = 0; i < 16; ++i) { | |
1313 | if (devc->trigger.risingmask & (1 << i) || | |
1314 | devc->trigger.fallingmask & (1 << i)) | |
1315 | masks[j++] = 1 << i; | |
1316 | } | |
1317 | ||
1318 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1319 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1320 | ||
1321 | /* Add glue logic */ | |
1322 | if (masks[0] || masks[1]) { | |
1323 | /* Transition trigger. */ | |
1324 | if (masks[0] & devc->trigger.risingmask) | |
1325 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1326 | if (masks[0] & devc->trigger.fallingmask) | |
1327 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1328 | if (masks[1] & devc->trigger.risingmask) | |
1329 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1330 | if (masks[1] & devc->trigger.fallingmask) | |
1331 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1332 | } else { | |
1333 | /* Only value/mask trigger. */ | |
1334 | lut->m3 = 0xffff; | |
1335 | } | |
1336 | ||
1337 | /* Triggertype: event. */ | |
1338 | lut->params.selres = 3; | |
1339 | ||
1340 | return SR_OK; | |
1341 | } | |
1342 | ||
1343 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) | |
1344 | { | |
1345 | struct dev_context *devc; | |
1346 | struct clockselect_50 clockselect; | |
1347 | int frac, triggerpin, ret; | |
1348 | uint8_t triggerselect = 0; | |
1349 | struct triggerinout triggerinout_conf; | |
1350 | struct triggerlut lut; | |
1351 | ||
1352 | if (sdi->status != SR_ST_ACTIVE) | |
1353 | return SR_ERR_DEV_CLOSED; | |
1354 | ||
1355 | devc = sdi->priv; | |
1356 | ||
1357 | if (configure_channels(sdi) != SR_OK) { | |
1358 | sr_err("Failed to configure channels."); | |
1359 | return SR_ERR; | |
1360 | } | |
1361 | ||
1362 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1363 | if (devc->cur_firmware == -1) { | |
1364 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1365 | return ret; | |
1366 | } | |
1367 | ||
1368 | /* Enter trigger programming mode. */ | |
1369 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); | |
1370 | ||
1371 | /* 100 and 200 MHz mode. */ | |
1372 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
1373 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
1374 | ||
1375 | /* Find which pin to trigger on from mask. */ | |
1376 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1377 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & | |
1378 | (1 << triggerpin)) | |
1379 | break; | |
1380 | ||
1381 | /* Set trigger pin and light LED on trigger. */ | |
1382 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1383 | ||
1384 | /* Default rising edge. */ | |
1385 | if (devc->trigger.fallingmask) | |
1386 | triggerselect |= 1 << 3; | |
1387 | ||
1388 | /* All other modes. */ | |
1389 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1390 | build_basic_trigger(&lut, devc); | |
1391 | ||
1392 | sigma_write_trigger_lut(&lut, devc); | |
1393 | ||
1394 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1395 | } | |
1396 | ||
1397 | /* Setup trigger in and out pins to default values. */ | |
1398 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1399 | triggerinout_conf.trgout_bytrigger = 1; | |
1400 | triggerinout_conf.trgout_enable = 1; | |
1401 | ||
1402 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1403 | (uint8_t *) &triggerinout_conf, | |
1404 | sizeof(struct triggerinout), devc); | |
1405 | ||
1406 | /* Go back to normal mode. */ | |
1407 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); | |
1408 | ||
1409 | /* Set clock select register. */ | |
1410 | if (devc->cur_samplerate == SR_MHZ(200)) | |
1411 | /* Enable 4 channels. */ | |
1412 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); | |
1413 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
1414 | /* Enable 8 channels. */ | |
1415 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); | |
1416 | else { | |
1417 | /* | |
1418 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1419 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1420 | */ | |
1421 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; | |
1422 | ||
1423 | clockselect.async = 0; | |
1424 | clockselect.fraction = frac; | |
1425 | clockselect.disabled_channels = 0; | |
1426 | ||
1427 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1428 | (uint8_t *) &clockselect, | |
1429 | sizeof(clockselect), devc); | |
1430 | } | |
1431 | ||
1432 | /* Setup maximum post trigger time. */ | |
1433 | sigma_set_register(WRITE_POST_TRIGGER, | |
1434 | (devc->capture_ratio * 255) / 100, devc); | |
1435 | ||
1436 | /* Start acqusition. */ | |
1437 | gettimeofday(&devc->start_tv, 0); | |
1438 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
1439 | ||
1440 | devc->cb_data = cb_data; | |
1441 | ||
1442 | /* Send header packet to the session bus. */ | |
1443 | std_session_send_df_header(cb_data, LOG_PREFIX); | |
1444 | ||
1445 | /* Add capture source. */ | |
1446 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); | |
1447 | ||
1448 | devc->state.state = SIGMA_CAPTURE; | |
1449 | ||
1450 | return SR_OK; | |
1451 | } | |
1452 | ||
1453 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) | |
1454 | { | |
1455 | struct dev_context *devc; | |
1456 | ||
1457 | (void)cb_data; | |
1458 | ||
1459 | devc = sdi->priv; | |
1460 | devc->state.state = SIGMA_IDLE; | |
1461 | ||
1462 | sr_source_remove(0); | |
1463 | ||
1464 | return SR_OK; | |
1465 | } | |
1466 | ||
1467 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { | |
1468 | .name = "asix-sigma", | |
1469 | .longname = "ASIX SIGMA/SIGMA2", | |
1470 | .api_version = 1, | |
1471 | .init = init, | |
1472 | .cleanup = cleanup, | |
1473 | .scan = scan, | |
1474 | .dev_list = dev_list, | |
1475 | .dev_clear = dev_clear, | |
1476 | .config_get = config_get, | |
1477 | .config_set = config_set, | |
1478 | .config_list = config_list, | |
1479 | .dev_open = dev_open, | |
1480 | .dev_close = dev_close, | |
1481 | .dev_acquisition_start = dev_acquisition_start, | |
1482 | .dev_acquisition_stop = dev_acquisition_stop, | |
1483 | .priv = NULL, | |
1484 | }; |