[libsigrokdecode.git] / decoders / usb_signalling / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

'''
OUTPUT_PYTHON format:

Packet:
[<ptype>, <pdata>]

<ptype>, <pdata>:
 - 'SOP', None
 - 'SYM', <sym>
 - 'BIT', <bit>
 - 'STUFF BIT', None
 - 'EOP', None
 - 'ERR', None

<sym>:
 - 'J', 'K', 'SE0', or 'SE1'

<bit>:
 - '0' or '1'
 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
'''

# Low-/full-speed symbols.
# Note: Low-speed J and K are inverted compared to the full-speed J and K!
symbols = {
    'low-speed': {
        # (<dp>, <dm>): <symbol/state>
        (0, 0): 'SE0',
        (1, 0): 'K',
        (0, 1): 'J',
        (1, 1): 'SE1',
    },
    'full-speed': {
        # (<dp>, <dm>): <symbol/state>
        (0, 0): 'SE0',
        (1, 0): 'J',
        (0, 1): 'K',
        (1, 1): 'SE1',
    },
}

bitrates = {
    'low-speed': 1500000,   # 1.5Mb/s (+/- 1.5%)
    'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
}

sym_annotation = {
    'J': [0, ['J']],
    'K': [1, ['K']],
    'SE0': [2, ['SE0', '0']],
    'SE1': [3, ['SE1', '1']],
}

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 2
    id = 'usb_signalling'
    name = 'USB signalling'
    longname = 'Universal Serial Bus (LS/FS) signalling'
    desc = 'USB (low-speed and full-speed) signalling protocol.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['usb_signalling']
    channels = (
        {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
        {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
    )
    options = (
        {'id': 'signalling', 'desc': 'Signalling',
            'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
    )
    annotations = (
        ('sym-j', 'J symbol'),
        ('sym-k', 'K symbol'),
        ('sym-se0', 'SE0 symbol'),
        ('sym-se1', 'SE1 symbol'),
        ('sop', 'Start of packet (SOP)'),
        ('eop', 'End of packet (EOP)'),
        ('bit', 'Bit'),
        ('stuffbit', 'Stuff bit'),
        ('error', 'Error'),
    )
    annotation_rows = (
        ('bits', 'Bits', (4, 5, 6, 7, 8)),
        ('symbols', 'Symbols', (0, 1, 2, 3)),
    )

    def __init__(self):
        self.samplerate = None
        self.oldsym = 'J' # The "idle" state is J.
        self.ss_block = None
        self.samplenum = 0
        self.bitrate = None
        self.bitwidth = None
        self.samplepos = None
        self.samplenum_target = None
        self.samplenum_edge = None
        self.samplenum_lastedge = 0
        self.oldpins = None
        self.edgepins = None
        self.consecutive_ones = 0
        self.state = 'IDLE'

    def start(self):
        self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value
            self.bitrate = bitrates[self.options['signalling']]
            self.bitwidth = float(self.samplerate) / float(self.bitrate)

    def putpx(self, data):
        s = self.samplenum_edge
        self.put(s, s, self.out_python, data)

    def putx(self, data):
        s = self.samplenum_edge
        self.put(s, s, self.out_ann, data)

    def putpm(self, data):
        e = self.samplenum_edge
        self.put(self.ss_block, e, self.out_python, data)

    def putm(self, data):
        e = self.samplenum_edge
        self.put(self.ss_block, e, self.out_ann, data)

    def putpb(self, data):
        s, e = self.samplenum_lastedge, self.samplenum_edge
        self.put(s, e, self.out_python, data)

    def putb(self, data):
        s, e = self.samplenum_lastedge, self.samplenum_edge
        self.put(s, e, self.out_ann, data)

    def set_new_target_samplenum(self):
        self.samplepos += self.bitwidth;
        self.samplenum_target = int(self.samplepos)
        self.samplenum_lastedge = self.samplenum_edge
        self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))

    def wait_for_sop(self, sym):
        # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
        if sym != 'K':
            self.oldsym = sym
            return
        self.consecutive_ones = 0
        self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
        self.set_new_target_samplenum()
        self.putpx(['SOP', None])
        self.putx([4, ['SOP', 'S']])
        self.state = 'GET BIT'

    def handle_bit(self, b):
        if self.consecutive_ones == 6:
            if b == '0':
                # Stuff bit.
                self.putpb(['STUFF BIT', None])
                self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
                self.consecutive_ones = 0
            else:
                self.putpb(['ERR', None])
                self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
                self.state = 'IDLE'
        else:
            # Normal bit (not a stuff bit).
            self.putpb(['BIT', b])
            self.putb([6, ['%s' % b]])
            if b == '1':
                self.consecutive_ones += 1
            else:
                self.consecutive_ones = 0

    def get_eop(self, sym):
        # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
        self.set_new_target_samplenum()
        self.putpb(['SYM', sym])
        self.putb(sym_annotation[sym])
        self.oldsym = sym
        if sym == 'SE0':
            pass
        elif sym == 'J':
            # Got an EOP.
            self.putpm(['EOP', None])
            self.putm([5, ['EOP', 'E']])
            self.state = 'IDLE'
            self.bitwidth = float(self.samplerate) / float(self.bitrate)
        else:
            self.putpm(['ERR', None])
            self.putm([8, ['EOP Error', 'EErr', 'E']])
            self.state = 'IDLE'

    def get_bit(self, sym):
        self.set_new_target_samplenum()
        if sym == 'SE0':
            # Start of an EOP. Change state, save edge
            self.state = 'GET EOP'
            self.ss_block = self.samplenum_lastedge
        else:
            b = '0' if self.oldsym != sym else '1'
            self.handle_bit(b)
        self.putpb(['SYM', sym])
        self.putb(sym_annotation[sym])
        if self.oldsym != sym:
            edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
            if edgesym not in ('SE0', 'SE1'):
                if edgesym == sym:
                    self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
                    self.samplepos = self.samplepos - (0.01 * self.bitwidth)
                else:
                    self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
                    self.samplepos = self.samplepos + (0.01 * self.bitwidth)
        self.oldsym = sym

    def decode(self, ss, es, data):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')
        for (self.samplenum, pins) in data:
            # State machine.
            if self.state == 'IDLE':
                # Ignore identical samples early on (for performance reasons).
                if self.oldpins == pins:
                    continue
                self.oldpins = pins
                sym = symbols[self.options['signalling']][tuple(pins)]
                self.wait_for_sop(sym)
                self.edgepins = pins
            elif self.state in ('GET BIT', 'GET EOP'):
                # Wait until we're in the middle of the desired bit.
                if self.samplenum == self.samplenum_edge:
                    self.edgepins = pins
                if self.samplenum < self.samplenum_target:
                    continue
                sym = symbols[self.options['signalling']][tuple(pins)]
                if self.state == 'GET BIT':
                    self.get_bit(sym)
                elif self.state == 'GET EOP':
                    self.get_eop(sym)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	import sigrokdecode as srd
	23
	24	'''
	25	OUTPUT_PYTHON format:
	26
	27	Packet:
	28	[<ptype>, <pdata>]
	29
	30	<ptype>, <pdata>:
	31	- 'SOP', None
	32	- 'SYM', <sym>
	33	- 'BIT', <bit>
	34	- 'STUFF BIT', None
	35	- 'EOP', None
	36	- 'ERR', None
	37
	38	<sym>:
	39	- 'J', 'K', 'SE0', or 'SE1'
	40
	41	<bit>:
	42	- '0' or '1'
	43	- Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
	44	'''
	45
	46	# Low-/full-speed symbols.
	47	# Note: Low-speed J and K are inverted compared to the full-speed J and K!
	48	symbols = {
	49	'low-speed': {
	50	# (<dp>, <dm>): <symbol/state>
	51	(0, 0): 'SE0',
	52	(1, 0): 'K',
	53	(0, 1): 'J',
	54	(1, 1): 'SE1',
	55	},
	56	'full-speed': {
	57	# (<dp>, <dm>): <symbol/state>
	58	(0, 0): 'SE0',
	59	(1, 0): 'J',
	60	(0, 1): 'K',
	61	(1, 1): 'SE1',
	62	},
	63	}
	64
	65	bitrates = {
	66	'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
	67	'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
	68	}
	69
	70	sym_annotation = {
	71	'J': [0, ['J']],
	72	'K': [1, ['K']],
	73	'SE0': [2, ['SE0', '0']],
	74	'SE1': [3, ['SE1', '1']],
	75	}
	76
	77	class SamplerateError(Exception):
	78	pass
	79
	80	class Decoder(srd.Decoder):
	81	api_version = 2
	82	id = 'usb_signalling'
	83	name = 'USB signalling'
	84	longname = 'Universal Serial Bus (LS/FS) signalling'
	85	desc = 'USB (low-speed and full-speed) signalling protocol.'
	86	license = 'gplv2+'
	87	inputs = ['logic']
	88	outputs = ['usb_signalling']
	89	channels = (
	90	{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
	91	{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
	92	)
	93	options = (
	94	{'id': 'signalling', 'desc': 'Signalling',
	95	'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
	96	)
	97	annotations = (
	98	('sym-j', 'J symbol'),
	99	('sym-k', 'K symbol'),
	100	('sym-se0', 'SE0 symbol'),
	101	('sym-se1', 'SE1 symbol'),
	102	('sop', 'Start of packet (SOP)'),
	103	('eop', 'End of packet (EOP)'),
	104	('bit', 'Bit'),
	105	('stuffbit', 'Stuff bit'),
	106	('error', 'Error'),
	107	)
	108	annotation_rows = (
	109	('bits', 'Bits', (4, 5, 6, 7, 8)),
	110	('symbols', 'Symbols', (0, 1, 2, 3)),
	111	)
	112
	113	def __init__(self):
	114	self.samplerate = None
	115	self.oldsym = 'J' # The "idle" state is J.
	116	self.ss_block = None
	117	self.samplenum = 0
	118	self.bitrate = None
	119	self.bitwidth = None
	120	self.samplepos = None
	121	self.samplenum_target = None
	122	self.samplenum_edge = None
	123	self.samplenum_lastedge = 0
	124	self.oldpins = None
	125	self.edgepins = None
	126	self.consecutive_ones = 0
	127	self.state = 'IDLE'
	128
	129	def start(self):
	130	self.out_python = self.register(srd.OUTPUT_PYTHON)
	131	self.out_ann = self.register(srd.OUTPUT_ANN)
	132
	133	def metadata(self, key, value):
	134	if key == srd.SRD_CONF_SAMPLERATE:
	135	self.samplerate = value
	136	self.bitrate = bitrates[self.options['signalling']]
	137	self.bitwidth = float(self.samplerate) / float(self.bitrate)
	138
	139	def putpx(self, data):
	140	s = self.samplenum_edge
	141	self.put(s, s, self.out_python, data)
	142
	143	def putx(self, data):
	144	s = self.samplenum_edge
	145	self.put(s, s, self.out_ann, data)
	146
	147	def putpm(self, data):
	148	e = self.samplenum_edge
	149	self.put(self.ss_block, e, self.out_python, data)
	150
	151	def putm(self, data):
	152	e = self.samplenum_edge
	153	self.put(self.ss_block, e, self.out_ann, data)
	154
	155	def putpb(self, data):
	156	s, e = self.samplenum_lastedge, self.samplenum_edge
	157	self.put(s, e, self.out_python, data)
	158
	159	def putb(self, data):
	160	s, e = self.samplenum_lastedge, self.samplenum_edge
	161	self.put(s, e, self.out_ann, data)
	162
	163	def set_new_target_samplenum(self):
	164	self.samplepos += self.bitwidth;
	165	self.samplenum_target = int(self.samplepos)
	166	self.samplenum_lastedge = self.samplenum_edge
	167	self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
	168
	169	def wait_for_sop(self, sym):
	170	# Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
	171	if sym != 'K':
	172	self.oldsym = sym
	173	return
	174	self.consecutive_ones = 0
	175	self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
	176	self.set_new_target_samplenum()
	177	self.putpx(['SOP', None])
	178	self.putx([4, ['SOP', 'S']])
	179	self.state = 'GET BIT'
	180
	181	def handle_bit(self, b):
	182	if self.consecutive_ones == 6:
	183	if b == '0':
	184	# Stuff bit.
	185	self.putpb(['STUFF BIT', None])
	186	self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
	187	self.consecutive_ones = 0
	188	else:
	189	self.putpb(['ERR', None])
	190	self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
	191	self.state = 'IDLE'
	192	else:
	193	# Normal bit (not a stuff bit).
	194	self.putpb(['BIT', b])
	195	self.putb([6, ['%s' % b]])
	196	if b == '1':
	197	self.consecutive_ones += 1
	198	else:
	199	self.consecutive_ones = 0
	200
	201	def get_eop(self, sym):
	202	# EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
	203	self.set_new_target_samplenum()
	204	self.putpb(['SYM', sym])
	205	self.putb(sym_annotation[sym])
	206	self.oldsym = sym
	207	if sym == 'SE0':
	208	pass
	209	elif sym == 'J':
	210	# Got an EOP.
	211	self.putpm(['EOP', None])
	212	self.putm([5, ['EOP', 'E']])
	213	self.state = 'IDLE'
	214	self.bitwidth = float(self.samplerate) / float(self.bitrate)
	215	else:
	216	self.putpm(['ERR', None])
	217	self.putm([8, ['EOP Error', 'EErr', 'E']])
	218	self.state = 'IDLE'
	219
	220	def get_bit(self, sym):
	221	self.set_new_target_samplenum()
	222	if sym == 'SE0':
	223	# Start of an EOP. Change state, save edge
	224	self.state = 'GET EOP'
	225	self.ss_block = self.samplenum_lastedge
	226	else:
	227	b = '0' if self.oldsym != sym else '1'
	228	self.handle_bit(b)
	229	self.putpb(['SYM', sym])
	230	self.putb(sym_annotation[sym])
	231	if self.oldsym != sym:
	232	edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
	233	if edgesym not in ('SE0', 'SE1'):
	234	if edgesym == sym:
	235	self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
	236	self.samplepos = self.samplepos - (0.01 * self.bitwidth)
	237	else:
	238	self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
	239	self.samplepos = self.samplepos + (0.01 * self.bitwidth)
	240	self.oldsym = sym
	241
	242	def decode(self, ss, es, data):
	243	if not self.samplerate:
	244	raise SamplerateError('Cannot decode without samplerate.')
	245	for (self.samplenum, pins) in data:
	246	# State machine.
	247	if self.state == 'IDLE':
	248	# Ignore identical samples early on (for performance reasons).
	249	if self.oldpins == pins:
	250	continue
	251	self.oldpins = pins
	252	sym = symbols[self.options['signalling']][tuple(pins)]
	253	self.wait_for_sop(sym)
	254	self.edgepins = pins
	255	elif self.state in ('GET BIT', 'GET EOP'):
	256	# Wait until we're in the middle of the desired bit.
	257	if self.samplenum == self.samplenum_edge:
	258	self.edgepins = pins
	259	if self.samplenum < self.samplenum_target:
	260	continue
	261	sym = symbols[self.options['signalling']][tuple(pins)]
	262	if self.state == 'GET BIT':
	263	self.get_bit(sym)
	264	elif self.state == 'GET EOP':
	265	self.get_eop(sym)