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1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # USB Full-speed protocol decoder | |
23 | # | |
24 | # Full-speed USB signalling consists of two signal lines, both driven at 3.3V | |
25 | # logic levels. The signals are DP (D+) and DM (D-), and normally operate in | |
26 | # differential mode. | |
27 | # The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K. | |
28 | # A state SE0 is defined where DP=DM=0. This common mode signal is used to | |
29 | # signal a reset or end of packet. | |
30 | # | |
31 | # Data transmitted on the USB is encoded with NRZI. A transition from J to K | |
32 | # or vice-versa indicates a logic 0, while no transition indicates a logic 1. | |
33 | # If 6 ones are transmitted consecutively, a zero is inserted to force a | |
34 | # transition. This is known as bit stuffing. Data is transferred at a rate | |
35 | # of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit | |
36 | # intervals long. | |
37 | # | |
38 | # Details: | |
39 | # https://en.wikipedia.org/wiki/USB | |
40 | # http://www.usb.org/developers/docs/ | |
41 | # | |
42 | ||
43 | import sigrokdecode | |
44 | ||
45 | # States | |
46 | SE0, J, K, SE1 = 0, 1, 2, 3 | |
47 | syms = { | |
48 | (0, 0): SE0, | |
49 | (1, 0): J, | |
50 | (0, 1): K, | |
51 | (1, 1): SE1, | |
52 | } | |
53 | ||
54 | def bitstr_to_num(bitstr): | |
55 | if not bitstr: return 0 | |
56 | l = list(bitstr) | |
57 | l.reverse() | |
58 | return int(''.join(l), 2) | |
59 | ||
60 | def packet_decode(packet): | |
61 | pids = { | |
62 | '10000111':'OUT', # Tokens | |
63 | '10010110':'IN', | |
64 | '10100101':'SOF', | |
65 | '10110100':'SETUP', | |
66 | '11000011':'DATA0', # Data | |
67 | '11010010':'DATA1', | |
68 | '01001011':'ACK', # Handshake | |
69 | '01011010':'NAK', | |
70 | '01111000':'STALL', | |
71 | '01101001':'NYET', | |
72 | } | |
73 | ||
74 | sync = packet[:8] | |
75 | pid = packet[8:16] | |
76 | pid = pids.get(pid, pid) | |
77 | # Remove CRC. | |
78 | if pid in ('OUT', 'IN', 'SOF', 'SETUP'): | |
79 | data = packet[16:-5] | |
80 | if pid == 'SOF': | |
81 | data = str(bitstr_to_num(data)) | |
82 | else: | |
83 | dev = bitstr_to_num(data[:7]) | |
84 | ep = bitstr_to_num(data[7:]) | |
85 | data = "DEV %d EP %d" % (dev, ep) | |
86 | ||
87 | elif pid in ('DATA0', 'DATA1'): | |
88 | data = packet[16:-16] | |
89 | tmp = "" | |
90 | while data: | |
91 | tmp += "%02X " % bitstr_to_num(data[:8]) | |
92 | data = data[8:] | |
93 | data = tmp | |
94 | else: | |
95 | data = packet[16:] | |
96 | ||
97 | if sync != "00000001": | |
98 | return "SYNC INVALID!" | |
99 | ||
100 | return pid + ' ' + data | |
101 | ||
102 | class Decoder(sigrokdecode.Decoder): | |
103 | id = 'usb' | |
104 | name = 'USB' | |
105 | desc = 'Universal Serial Bus' | |
106 | longname = '...longname...' | |
107 | longdesc = '...longdesc...' | |
108 | author = 'Gareth McMullin' | |
109 | email = 'gareth@blacksphere.co.nz' | |
110 | license = 'gplv2+' | |
111 | inputs = ['logic'] | |
112 | outputs = ['usb'] | |
113 | # Probe names with a set of defaults | |
114 | probes = [ | |
115 | {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, | |
116 | {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, | |
117 | ] | |
118 | options = {} | |
119 | ||
120 | def __init__(self): | |
121 | self.out_proto = None | |
122 | self.out_ann = None | |
123 | ||
124 | def start(self, metadata): | |
125 | self.rate = metadata['samplerate'] | |
126 | # self.out_proto = self.add(sigrokdecode.SRD_OUTPUT_PROTOCOL, 'usb') | |
127 | self.out_ann = self.add(sigrokdecode.SRD_OUTPUT_ANNOTATION, 'usb') | |
128 | if self.rate < 48000000: | |
129 | raise Exception("Sample rate not sufficient for USB decoding") | |
130 | # Initialise decoder state. | |
131 | self.sym = J | |
132 | self.scount = 0 | |
133 | self.packet = '' | |
134 | ||
135 | def decode(self, timeoffset, duration, data): | |
136 | out = [] | |
137 | ||
138 | # FIXME | |
139 | for (samplenum, (dp, dm, x, y, z, a)) in data: | |
140 | ||
141 | self.scount += 1 | |
142 | ||
143 | sym = syms[dp, dm] | |
144 | if sym == self.sym: | |
145 | continue | |
146 | ||
147 | if self.scount == 1: | |
148 | # We ignore single sample width pulses. | |
149 | # I sometimes get these with the OLS. | |
150 | self.sym = sym | |
151 | self.scount = 0 | |
152 | continue | |
153 | ||
154 | # How many bits since the last transition? | |
155 | if self.packet or self.sym != J: | |
156 | bitcount = int((self.scount - 1) * 12000000 / self.rate) | |
157 | else: | |
158 | bitcount = 0 | |
159 | ||
160 | if self.sym == SE0: | |
161 | if bitcount == 1: | |
162 | # End-Of-Packet (EOP) | |
163 | out += [{"type":"usb", "data":self.packet, | |
164 | "display":packet_decode(self.packet)}] | |
165 | else: | |
166 | # Longer than EOP, assume reset. | |
167 | out += [{"type":"usb", "display":"RESET"}] | |
168 | self.scount = 0 | |
169 | self.sym = sym | |
170 | self.packet = '' | |
171 | continue | |
172 | ||
173 | # Add bits to the packet string. | |
174 | self.packet += '1' * bitcount | |
175 | # Handle bit stuffing. | |
176 | if bitcount < 6 and sym != SE0: | |
177 | self.packet += '0' | |
178 | elif bitcount > 6: | |
179 | out += [{"type":"usb", "display":"BIT STUFF ERROR"}] | |
180 | ||
181 | self.scount = 0 | |
182 | self.sym = sym | |
183 | ||
184 | if out != []: | |
185 | # self.put(0, 0, self.out_proto, out_proto) | |
186 | self.put(0, 0, self.out_ann, out) | |
187 |