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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | from collections import namedtuple | |
23 | ||
24 | Data = namedtuple('Data', ['ss', 'es', 'val']) | |
25 | ||
26 | ''' | |
27 | OUTPUT_PYTHON format: | |
28 | ||
29 | Packet: | |
30 | [<ptype>, <data1>, <data2>] | |
31 | ||
32 | <ptype>: | |
33 | - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data. | |
34 | The data is _usually_ 8 bits (but can also be fewer or more bits). | |
35 | Both data items are Python numbers (not strings), or None if the respective | |
36 | channel was not supplied. | |
37 | - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data | |
38 | item, and for each of those also their respective start-/endsample numbers. | |
39 | - 'CS-CHANGE': <data1> is the old CS# pin value, <data2> is the new value. | |
40 | Both data items are Python numbers (0/1), not strings. At the beginning of | |
41 | the decoding a packet is generated with <data1> = None and <data2> being the | |
42 | initial state of the CS# pin or None if the chip select pin is not supplied. | |
43 | - 'TRANSFER': <data1>/<data2> contain a list of Data() namedtuples for each | |
44 | byte transferred during this block of CS# asserted time. Each Data() has | |
45 | fields ss, es, and val. | |
46 | ||
47 | Examples: | |
48 | ['CS-CHANGE', None, 1] | |
49 | ['CS-CHANGE', 1, 0] | |
50 | ['DATA', 0xff, 0x3a] | |
51 | ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], | |
52 | [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], | |
53 | [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88], | |
54 | [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]] | |
55 | ['DATA', 0x65, 0x00] | |
56 | ['DATA', 0xa8, None] | |
57 | ['DATA', None, 0x55] | |
58 | ['CS-CHANGE', 0, 1] | |
59 | ['TRANSFER', [Data(ss=80, es=96, val=0xff), ...], | |
60 | [Data(ss=80, es=96, val=0x3a), ...]] | |
61 | ''' | |
62 | ||
63 | # Key: (CPOL, CPHA). Value: SPI mode. | |
64 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. | |
65 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
66 | spi_mode = { | |
67 | (0, 0): 0, # Mode 0 | |
68 | (0, 1): 1, # Mode 1 | |
69 | (1, 0): 2, # Mode 2 | |
70 | (1, 1): 3, # Mode 3 | |
71 | } | |
72 | ||
73 | class ChannelError(Exception): | |
74 | pass | |
75 | ||
76 | class Decoder(srd.Decoder): | |
77 | api_version = 3 | |
78 | id = 'spi' | |
79 | name = 'SPI' | |
80 | longname = 'Serial Peripheral Interface' | |
81 | desc = 'Full-duplex, synchronous, serial bus.' | |
82 | license = 'gplv2+' | |
83 | inputs = ['logic'] | |
84 | outputs = ['spi'] | |
85 | tags = ['Embedded/industrial'] | |
86 | channels = ( | |
87 | {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, | |
88 | ) | |
89 | optional_channels = ( | |
90 | {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, | |
91 | {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, | |
92 | {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, | |
93 | ) | |
94 | options = ( | |
95 | {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low', | |
96 | 'values': ('active-low', 'active-high')}, | |
97 | {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0, | |
98 | 'values': (0, 1)}, | |
99 | {'id': 'cpha', 'desc': 'Clock phase', 'default': 0, | |
100 | 'values': (0, 1)}, | |
101 | {'id': 'bitorder', 'desc': 'Bit order', | |
102 | 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')}, | |
103 | {'id': 'wordsize', 'desc': 'Word size', 'default': 8}, | |
104 | ) | |
105 | annotations = ( | |
106 | ('miso-data', 'MISO data'), | |
107 | ('mosi-data', 'MOSI data'), | |
108 | ('miso-bit', 'MISO bit'), | |
109 | ('mosi-bit', 'MOSI bit'), | |
110 | ('warning', 'Warning'), | |
111 | ('miso-transfer', 'MISO transfer'), | |
112 | ('mosi-transfer', 'MOSI transfer'), | |
113 | ) | |
114 | annotation_rows = ( | |
115 | ('miso-bits', 'MISO bits', (2,)), | |
116 | ('miso-data-vals', 'MISO data', (0,)), | |
117 | ('miso-transfers', 'MISO transfers', (5,)), | |
118 | ('mosi-bits', 'MOSI bits', (3,)), | |
119 | ('mosi-data-vals', 'MOSI data', (1,)), | |
120 | ('mosi-transfers', 'MOSI transfers', (6,)), | |
121 | ('other', 'Other', (4,)), | |
122 | ) | |
123 | binary = ( | |
124 | ('miso', 'MISO'), | |
125 | ('mosi', 'MOSI'), | |
126 | ) | |
127 | ||
128 | def __init__(self): | |
129 | self.reset() | |
130 | ||
131 | def reset(self): | |
132 | self.samplerate = None | |
133 | self.bitcount = 0 | |
134 | self.misodata = self.mosidata = 0 | |
135 | self.misobits = [] | |
136 | self.mosibits = [] | |
137 | self.misobytes = [] | |
138 | self.mosibytes = [] | |
139 | self.ss_block = -1 | |
140 | self.ss_transfer = -1 | |
141 | self.cs_was_deasserted = False | |
142 | self.have_cs = self.have_miso = self.have_mosi = None | |
143 | ||
144 | def start(self): | |
145 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
146 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
147 | self.out_binary = self.register(srd.OUTPUT_BINARY) | |
148 | self.out_bitrate = self.register(srd.OUTPUT_META, | |
149 | meta=(int, 'Bitrate', 'Bitrate during transfers')) | |
150 | self.bw = (self.options['wordsize'] + 7) // 8 | |
151 | ||
152 | def metadata(self, key, value): | |
153 | if key == srd.SRD_CONF_SAMPLERATE: | |
154 | self.samplerate = value | |
155 | ||
156 | def putw(self, data): | |
157 | self.put(self.ss_block, self.samplenum, self.out_ann, data) | |
158 | ||
159 | def putdata(self): | |
160 | # Pass MISO and MOSI bits and then data to the next PD up the stack. | |
161 | so = self.misodata if self.have_miso else None | |
162 | si = self.mosidata if self.have_mosi else None | |
163 | so_bits = self.misobits if self.have_miso else None | |
164 | si_bits = self.mosibits if self.have_mosi else None | |
165 | ||
166 | if self.have_miso: | |
167 | ss, es = self.misobits[-1][1], self.misobits[0][2] | |
168 | bdata = so.to_bytes(self.bw, byteorder='big') | |
169 | self.put(ss, es, self.out_binary, [0, bdata]) | |
170 | if self.have_mosi: | |
171 | ss, es = self.mosibits[-1][1], self.mosibits[0][2] | |
172 | bdata = si.to_bytes(self.bw, byteorder='big') | |
173 | self.put(ss, es, self.out_binary, [1, bdata]) | |
174 | ||
175 | self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits]) | |
176 | self.put(ss, es, self.out_python, ['DATA', si, so]) | |
177 | ||
178 | if self.have_miso: | |
179 | self.misobytes.append(Data(ss=ss, es=es, val=so)) | |
180 | if self.have_mosi: | |
181 | self.mosibytes.append(Data(ss=ss, es=es, val=si)) | |
182 | ||
183 | # Bit annotations. | |
184 | if self.have_miso: | |
185 | for bit in self.misobits: | |
186 | self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]]) | |
187 | if self.have_mosi: | |
188 | for bit in self.mosibits: | |
189 | self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]]) | |
190 | ||
191 | # Dataword annotations. | |
192 | if self.have_miso: | |
193 | self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]]) | |
194 | if self.have_mosi: | |
195 | self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]]) | |
196 | ||
197 | def reset_decoder_state(self): | |
198 | self.misodata = 0 if self.have_miso else None | |
199 | self.mosidata = 0 if self.have_mosi else None | |
200 | self.misobits = [] if self.have_miso else None | |
201 | self.mosibits = [] if self.have_mosi else None | |
202 | self.bitcount = 0 | |
203 | ||
204 | def cs_asserted(self, cs): | |
205 | active_low = (self.options['cs_polarity'] == 'active-low') | |
206 | return (cs == 0) if active_low else (cs == 1) | |
207 | ||
208 | def handle_bit(self, miso, mosi, clk, cs): | |
209 | # If this is the first bit of a dataword, save its sample number. | |
210 | if self.bitcount == 0: | |
211 | self.ss_block = self.samplenum | |
212 | self.cs_was_deasserted = \ | |
213 | not self.cs_asserted(cs) if self.have_cs else False | |
214 | ||
215 | ws = self.options['wordsize'] | |
216 | bo = self.options['bitorder'] | |
217 | ||
218 | # Receive MISO bit into our shift register. | |
219 | if self.have_miso: | |
220 | if bo == 'msb-first': | |
221 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
222 | else: | |
223 | self.misodata |= miso << self.bitcount | |
224 | ||
225 | # Receive MOSI bit into our shift register. | |
226 | if self.have_mosi: | |
227 | if bo == 'msb-first': | |
228 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
229 | else: | |
230 | self.mosidata |= mosi << self.bitcount | |
231 | ||
232 | # Guesstimate the endsample for this bit (can be overridden below). | |
233 | es = self.samplenum | |
234 | if self.bitcount > 0: | |
235 | if self.have_miso: | |
236 | es += self.samplenum - self.misobits[0][1] | |
237 | elif self.have_mosi: | |
238 | es += self.samplenum - self.mosibits[0][1] | |
239 | ||
240 | if self.have_miso: | |
241 | self.misobits.insert(0, [miso, self.samplenum, es]) | |
242 | if self.have_mosi: | |
243 | self.mosibits.insert(0, [mosi, self.samplenum, es]) | |
244 | ||
245 | if self.bitcount > 0 and self.have_miso: | |
246 | self.misobits[1][2] = self.samplenum | |
247 | if self.bitcount > 0 and self.have_mosi: | |
248 | self.mosibits[1][2] = self.samplenum | |
249 | ||
250 | self.bitcount += 1 | |
251 | ||
252 | # Continue to receive if not enough bits were received, yet. | |
253 | if self.bitcount != ws: | |
254 | return | |
255 | ||
256 | self.putdata() | |
257 | ||
258 | # Meta bitrate. | |
259 | if self.samplerate: | |
260 | elapsed = 1 / float(self.samplerate) | |
261 | elapsed *= (self.samplenum - self.ss_block + 1) | |
262 | bitrate = int(1 / elapsed * ws) | |
263 | self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate) | |
264 | ||
265 | if self.have_cs and self.cs_was_deasserted: | |
266 | self.putw([4, ['CS# was deasserted during this data word!']]) | |
267 | ||
268 | self.reset_decoder_state() | |
269 | ||
270 | def find_clk_edge(self, miso, mosi, clk, cs, first): | |
271 | if self.have_cs and (first or self.matched[self.have_cs]): | |
272 | # Send all CS# pin value changes. | |
273 | oldcs = None if first else 1 - cs | |
274 | self.put(self.samplenum, self.samplenum, self.out_python, | |
275 | ['CS-CHANGE', oldcs, cs]) | |
276 | ||
277 | if self.cs_asserted(cs): | |
278 | self.ss_transfer = self.samplenum | |
279 | self.misobytes = [] | |
280 | self.mosibytes = [] | |
281 | elif self.ss_transfer != -1: | |
282 | if self.have_miso: | |
283 | self.put(self.ss_transfer, self.samplenum, self.out_ann, | |
284 | [5, [' '.join(format(x.val, '02X') for x in self.misobytes)]]) | |
285 | if self.have_mosi: | |
286 | self.put(self.ss_transfer, self.samplenum, self.out_ann, | |
287 | [6, [' '.join(format(x.val, '02X') for x in self.mosibytes)]]) | |
288 | self.put(self.ss_transfer, self.samplenum, self.out_python, | |
289 | ['TRANSFER', self.mosibytes, self.misobytes]) | |
290 | ||
291 | # Reset decoder state when CS# changes (and the CS# pin is used). | |
292 | self.reset_decoder_state() | |
293 | ||
294 | # We only care about samples if CS# is asserted. | |
295 | if self.have_cs and not self.cs_asserted(cs): | |
296 | return | |
297 | ||
298 | # Ignore sample if the clock pin hasn't changed. | |
299 | if first or not self.matched[0]: | |
300 | return | |
301 | ||
302 | # Sample data on rising/falling clock edge (depends on mode). | |
303 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
304 | if mode == 0 and clk == 0: # Sample on rising clock edge | |
305 | return | |
306 | elif mode == 1 and clk == 1: # Sample on falling clock edge | |
307 | return | |
308 | elif mode == 2 and clk == 1: # Sample on falling clock edge | |
309 | return | |
310 | elif mode == 3 and clk == 0: # Sample on rising clock edge | |
311 | return | |
312 | ||
313 | # Found the correct clock edge, now get the SPI bit(s). | |
314 | self.handle_bit(miso, mosi, clk, cs) | |
315 | ||
316 | def decode(self): | |
317 | # The CLK input is mandatory. Other signals are (individually) | |
318 | # optional. Yet either MISO or MOSI (or both) must be provided. | |
319 | # Tell stacked decoders when we don't have a CS# signal. | |
320 | if not self.has_channel(0): | |
321 | raise ChannelError('Either MISO or MOSI (or both) pins required.') | |
322 | self.have_miso = self.has_channel(1) | |
323 | self.have_mosi = self.has_channel(2) | |
324 | if not self.have_miso and not self.have_mosi: | |
325 | raise ChannelError('Either MISO or MOSI (or both) pins required.') | |
326 | self.have_cs = self.has_channel(3) | |
327 | if not self.have_cs: | |
328 | self.put(0, 0, self.out_python, ['CS-CHANGE', None, None]) | |
329 | ||
330 | # We want all CLK changes. We want all CS changes if CS is used. | |
331 | # Map 'have_cs' from boolean to an integer index. This simplifies | |
332 | # evaluation in other locations. | |
333 | wait_cond = [{0: 'e'}] | |
334 | if self.have_cs: | |
335 | self.have_cs = len(wait_cond) | |
336 | wait_cond.append({3: 'e'}) | |
337 | ||
338 | # "Pixel compatibility" with the v2 implementation. Grab and | |
339 | # process the very first sample before checking for edges. The | |
340 | # previous implementation did this by seeding old values with | |
341 | # None, which led to an immediate "change" in comparison. | |
342 | (clk, miso, mosi, cs) = self.wait({}) | |
343 | self.find_clk_edge(miso, mosi, clk, cs, True) | |
344 | ||
345 | while True: | |
346 | (clk, miso, mosi, cs) = self.wait(wait_cond) | |
347 | self.find_clk_edge(miso, mosi, clk, cs, False) |