[libsigrokdecode.git] / decoders / rtc8564 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b):
    return (b & 0x0f) + ((b >> 4) * 10)

def reg_list():
    l = []
    for i in range(8 + 1):
        l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))

    return tuple(l)

class Decoder(srd.Decoder):
    api_version = 1
    id = 'rtc8564'
    name = 'RTC-8564'
    longname = 'Epson RTC-8564 JE/NB'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['rtc8564']
    annotations = reg_list() + (
        ('read', 'Read date/time'),
        ('write', 'Write date/time'),
        ('bit-reserved', 'Reserved bit'),
        ('bit-vl', 'VL bit'),
        ('bit-century', 'Century bit'),
        ('reg-read', 'Register read'),
        ('reg-write', 'Register write'),
    )
    annotation_rows = (
        ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
        ('regs', 'Register access', (14, 15)),
        ('date-time', 'Date/time', (9, 10)),
    )

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.weekdays = -1
        self.months = -1
        self.years = -1
        self.bits = []

    def start(self):
        # self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putd(self, bit1, bit2, data):
        self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)

    def putr(self, bit):
        self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
                 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])

    def handle_reg_0x00(self, b): # Control register 1
        pass

    def handle_reg_0x01(self, b): # Control register 2
        ti_tp = 1 if (b & (1 << 4)) else 0
        af = 1 if (b & (1 << 3)) else 0
        tf = 1 if (b & (1 << 2)) else 0
        aie = 1 if (b & (1 << 1)) else 0
        tie = 1 if (b & (1 << 0)) else 0

        ann = ''

        s = 'repeated' if ti_tp else 'single-shot'
        ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
               'events\n' % (ti_tp, s)
        s = '' if af else 'no '
        ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
        s = '' if tf else 'no '
        ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
        s = 'enabled' if aie else 'prohibited'
        ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
               'occurs\n' % (aie, s)
        s = 'enabled' if tie else 'prohibited'
        ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
               'event occurs\n' % (tie, s)

        self.putx([1, [ann]])

    def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
        vl = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
                        'VL: %d' % vl, 'VL']])
        s = self.seconds = bcd2int(b & 0x7f)
        self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])

    def handle_reg_0x03(self, b): # Minutes
        self.putr(7)
        m = self.minutes = bcd2int(b & 0x7f)
        self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x04(self, b): # Hours
        self.putr(7)
        self.putr(6)
        h = self.hours = bcd2int(b & 0x3f)
        self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])

    def handle_reg_0x05(self, b): # Days
        self.putr(7)
        self.putr(6)
        d = self.days = bcd2int(b & 0x3f)
        self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])

    def handle_reg_0x06(self, b): # Weekdays
        for i in (7, 6, 5, 4, 3):
            self.putr(i)
        w = self.weekdays = bcd2int(b & 0x07)
        self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])

    def handle_reg_0x07(self, b): # Months / century bit
        c = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
                              'Cent: %d' % c, 'C: %d' % c, 'C']])
        self.putr(6)
        self.putr(5)
        m = self.months = bcd2int(b & 0x1f)
        self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x08(self, b): # Years
        y = self.years = bcd2int(b & 0xff)
        self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])

    def handle_reg_0x09(self, b): # Alarm, minute
        pass

    def handle_reg_0x0a(self, b): # Alarm, hour
        pass

    def handle_reg_0x0b(self, b): # Alarm, day
        pass

    def handle_reg_0x0c(self, b): # Alarm, weekday
        pass

    def handle_reg_0x0d(self, b): # CLKOUT output
        pass

    def handle_reg_0x0e(self, b): # Timer setting
        pass

    def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
        pass

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Collect the 'BITS' packet, then return. The next packet is
        # guaranteed to belong to these bits we just stored.
        if cmd == 'BITS':
            self.bits = databyte
            return

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.block_start_sample = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd != 'ADDRESS WRITE':
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's probably an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
                self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
                                'WR %s' % s, 'WR', 'W']])
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                # TODO: Handle read/write of only parts of these items.
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [9, ['Write date/time: %s' % d, 'Write: %s' % d,
                              'W: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd == 'ADDRESS READ':
                self.state = 'READ RTC REGS2'
                return
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
                self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
                                'RR %s' % s, 'RR', 'R']])
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [10, ['Read date/time: %s' % d, 'Read: %s' % d,
                               'R: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO?
        else:
            raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22
	23	# Return the specified BCD number (max. 8 bits) as integer.
	24	def bcd2int(b):
	25	return (b & 0x0f) + ((b >> 4) * 10)
	26
	27	def reg_list():
	28	l = []
	29	for i in range(8 + 1):
	30	l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))
	31
	32	return tuple(l)
	33
	34	class Decoder(srd.Decoder):
	35	api_version = 1
	36	id = 'rtc8564'
	37	name = 'RTC-8564'
	38	longname = 'Epson RTC-8564 JE/NB'
	39	desc = 'Realtime clock module protocol.'
	40	license = 'gplv2+'
	41	inputs = ['i2c']
	42	outputs = ['rtc8564']
	43	annotations = reg_list() + (
	44	('read', 'Read date/time'),
	45	('write', 'Write date/time'),
	46	('bit-reserved', 'Reserved bit'),
	47	('bit-vl', 'VL bit'),
	48	('bit-century', 'Century bit'),
	49	('reg-read', 'Register read'),
	50	('reg-write', 'Register write'),
	51	)
	52	annotation_rows = (
	53	('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
	54	('regs', 'Register access', (14, 15)),
	55	('date-time', 'Date/time', (9, 10)),
	56	)
	57
	58	def __init__(self, **kwargs):
	59	self.state = 'IDLE'
	60	self.hours = -1
	61	self.minutes = -1
	62	self.seconds = -1
	63	self.days = -1
	64	self.weekdays = -1
	65	self.months = -1
	66	self.years = -1
	67	self.bits = []
	68
	69	def start(self):
	70	# self.out_python = self.register(srd.OUTPUT_PYTHON)
	71	self.out_ann = self.register(srd.OUTPUT_ANN)
	72
	73	def putx(self, data):
	74	self.put(self.ss, self.es, self.out_ann, data)
	75
	76	def putd(self, bit1, bit2, data):
	77	self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
	78
	79	def putr(self, bit):
	80	self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
	81	[11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
	82
	83	def handle_reg_0x00(self, b): # Control register 1
	84	pass
	85
	86	def handle_reg_0x01(self, b): # Control register 2
	87	ti_tp = 1 if (b & (1 << 4)) else 0
	88	af = 1 if (b & (1 << 3)) else 0
	89	tf = 1 if (b & (1 << 2)) else 0
	90	aie = 1 if (b & (1 << 1)) else 0
	91	tie = 1 if (b & (1 << 0)) else 0
	92
	93	ann = ''
	94
	95	s = 'repeated' if ti_tp else 'single-shot'
	96	ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
	97	'events\n' % (ti_tp, s)
	98	s = '' if af else 'no '
	99	ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
	100	s = '' if tf else 'no '
	101	ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
	102	s = 'enabled' if aie else 'prohibited'
	103	ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
	104	'occurs\n' % (aie, s)
	105	s = 'enabled' if tie else 'prohibited'
	106	ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
	107	'event occurs\n' % (tie, s)
	108
	109	self.putx([1, [ann]])
	110
	111	def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
	112	vl = 1 if (b & (1 << 7)) else 0
	113	self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
	114	'VL: %d' % vl, 'VL']])
	115	s = self.seconds = bcd2int(b & 0x7f)
	116	self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
	117
	118	def handle_reg_0x03(self, b): # Minutes
	119	self.putr(7)
	120	m = self.minutes = bcd2int(b & 0x7f)
	121	self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
	122
	123	def handle_reg_0x04(self, b): # Hours
	124	self.putr(7)
	125	self.putr(6)
	126	h = self.hours = bcd2int(b & 0x3f)
	127	self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
	128
	129	def handle_reg_0x05(self, b): # Days
	130	self.putr(7)
	131	self.putr(6)
	132	d = self.days = bcd2int(b & 0x3f)
	133	self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
	134
	135	def handle_reg_0x06(self, b): # Weekdays
	136	for i in (7, 6, 5, 4, 3):
	137	self.putr(i)
	138	w = self.weekdays = bcd2int(b & 0x07)
	139	self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
	140
	141	def handle_reg_0x07(self, b): # Months / century bit
	142	c = 1 if (b & (1 << 7)) else 0
	143	self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
	144	'Cent: %d' % c, 'C: %d' % c, 'C']])
	145	self.putr(6)
	146	self.putr(5)
	147	m = self.months = bcd2int(b & 0x1f)
	148	self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
	149
	150	def handle_reg_0x08(self, b): # Years
	151	y = self.years = bcd2int(b & 0xff)
	152	self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
	153
	154	def handle_reg_0x09(self, b): # Alarm, minute
	155	pass
	156
	157	def handle_reg_0x0a(self, b): # Alarm, hour
	158	pass
	159
	160	def handle_reg_0x0b(self, b): # Alarm, day
	161	pass
	162
	163	def handle_reg_0x0c(self, b): # Alarm, weekday
	164	pass
	165
	166	def handle_reg_0x0d(self, b): # CLKOUT output
	167	pass
	168
	169	def handle_reg_0x0e(self, b): # Timer setting
	170	pass
	171
	172	def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
	173	pass
	174
	175	def decode(self, ss, es, data):
	176	cmd, databyte = data
	177
	178	# Collect the 'BITS' packet, then return. The next packet is
	179	# guaranteed to belong to these bits we just stored.
	180	if cmd == 'BITS':
	181	self.bits = databyte
	182	return
	183
	184	# Store the start/end samples of this I²C packet.
	185	self.ss, self.es = ss, es
	186
	187	# State machine.
	188	if self.state == 'IDLE':
	189	# Wait for an I²C START condition.
	190	if cmd != 'START':
	191	return
	192	self.state = 'GET SLAVE ADDR'
	193	self.block_start_sample = ss
	194	elif self.state == 'GET SLAVE ADDR':
	195	# Wait for an address write operation.
	196	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	197	if cmd != 'ADDRESS WRITE':
	198	return
	199	self.state = 'GET REG ADDR'
	200	elif self.state == 'GET REG ADDR':
	201	# Wait for a data write (master selects the slave register).
	202	if cmd != 'DATA WRITE':
	203	return
	204	self.reg = databyte
	205	self.state = 'WRITE RTC REGS'
	206	elif self.state == 'WRITE RTC REGS':
	207	# If we see a Repeated Start here, it's probably an RTC read.
	208	if cmd == 'START REPEAT':
	209	self.state = 'READ RTC REGS'
	210	return
	211	# Otherwise: Get data bytes until a STOP condition occurs.
	212	if cmd == 'DATA WRITE':
	213	r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
	214	self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
	215	'WR %s' % s, 'WR', 'W']])
	216	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	217	handle_reg(databyte)
	218	self.reg += 1
	219	# TODO: Check for NACK!
	220	elif cmd == 'STOP':
	221	# TODO: Handle read/write of only parts of these items.
	222	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	223	self.years, self.hours, self.minutes, self.seconds)
	224	self.put(self.block_start_sample, es, self.out_ann,
	225	[9, ['Write date/time: %s' % d, 'Write: %s' % d,
	226	'W: %s' % d]])
	227	self.state = 'IDLE'
	228	else:
	229	pass # TODO
	230	elif self.state == 'READ RTC REGS':
	231	# Wait for an address read operation.
	232	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	233	if cmd == 'ADDRESS READ':
	234	self.state = 'READ RTC REGS2'
	235	return
	236	else:
	237	pass # TODO
	238	elif self.state == 'READ RTC REGS2':
	239	if cmd == 'DATA READ':
	240	r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
	241	self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
	242	'RR %s' % s, 'RR', 'R']])
	243	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	244	handle_reg(databyte)
	245	self.reg += 1
	246	# TODO: Check for NACK!
	247	elif cmd == 'STOP':
	248	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	249	self.years, self.hours, self.minutes, self.seconds)
	250	self.put(self.block_start_sample, es, self.out_ann,
	251	[10, ['Read date/time: %s' % d, 'Read: %s' % d,
	252	'R: %s' % d]])
	253	self.state = 'IDLE'
	254	else:
	255	pass # TODO?
	256	else:
	257	raise Exception('Invalid state: %s' % self.state)
	258