]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2020 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | from common.srdhelper import SrdStrEnum | |
22 | ||
23 | ''' | |
24 | OUTPUT_PYTHON format: | |
25 | ||
26 | Packet: | |
27 | [<ptype>, <pdata>] | |
28 | ||
29 | <ptype>: | |
30 | - 'NEW STATE': <pdata> is the new state of the JTAG state machine. | |
31 | Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN', | |
32 | 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR', | |
33 | 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR', | |
34 | 'EXIT2-IR', 'UPDATE-IR'. | |
35 | - 'IR TDI': Bitstring that was clocked into the IR register. | |
36 | - 'IR TDO': Bitstring that was clocked out of the IR register. | |
37 | - 'DR TDI': Bitstring that was clocked into the DR register. | |
38 | - 'DR TDO': Bitstring that was clocked out of the DR register. | |
39 | ||
40 | All bitstrings are a list consisting of two items. The first is a sequence | |
41 | of '1' and '0' characters (the right-most character is the LSB. Example: | |
42 | '01110001', where 1 is the LSB). The second item is a list of ss/es values | |
43 | for each bit that is in the bitstring. | |
44 | ''' | |
45 | ||
46 | s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \ | |
47 | SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \ | |
48 | SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR' | |
49 | St = SrdStrEnum.from_str('St', s) | |
50 | ||
51 | jtag_states = [s.value for s in St] | |
52 | ||
53 | class Decoder(srd.Decoder): | |
54 | api_version = 3 | |
55 | id = 'jtag' | |
56 | name = 'JTAG' | |
57 | longname = 'Joint Test Action Group (IEEE 1149.1)' | |
58 | desc = 'Protocol for testing, debugging, and flashing ICs.' | |
59 | license = 'gplv2+' | |
60 | inputs = ['logic'] | |
61 | outputs = ['jtag'] | |
62 | tags = ['Debug/trace'] | |
63 | channels = ( | |
64 | {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'}, | |
65 | {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'}, | |
66 | {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'}, | |
67 | {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'}, | |
68 | ) | |
69 | optional_channels = ( | |
70 | {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'}, | |
71 | {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, | |
72 | {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, | |
73 | ) | |
74 | annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \ | |
75 | ('bit-tdi', 'Bit (TDI)'), | |
76 | ('bit-tdo', 'Bit (TDO)'), | |
77 | ('bitstring-tdi', 'Bitstring (TDI)'), | |
78 | ('bitstring-tdo', 'Bitstring (TDO)'), | |
79 | ) | |
80 | annotation_rows = ( | |
81 | ('bits-tdi', 'Bits (TDI)', (16,)), | |
82 | ('bits-tdo', 'Bits (TDO)', (17,)), | |
83 | ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)), | |
84 | ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)), | |
85 | ('states', 'States', tuple(range(15 + 1))), | |
86 | ) | |
87 | ||
88 | def __init__(self): | |
89 | self.reset() | |
90 | ||
91 | def reset(self): | |
92 | # self.state = St.TEST_LOGIC_RESET | |
93 | self.state = St.RUN_TEST_IDLE | |
94 | self.oldstate = None | |
95 | self.bits_tdi = [] | |
96 | self.bits_tdo = [] | |
97 | self.bits_samplenums_tdi = [] | |
98 | self.bits_samplenums_tdo = [] | |
99 | self.ss_item = self.es_item = None | |
100 | self.ss_bitstring = self.es_bitstring = None | |
101 | self.saved_item = None | |
102 | self.first = True | |
103 | self.first_bit = True | |
104 | ||
105 | def start(self): | |
106 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
107 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
108 | ||
109 | def putx(self, data): | |
110 | self.put(self.ss_item, self.es_item, self.out_ann, data) | |
111 | ||
112 | def putp(self, data): | |
113 | self.put(self.ss_item, self.es_item, self.out_python, data) | |
114 | ||
115 | def putx_bs(self, data): | |
116 | self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data) | |
117 | ||
118 | def putp_bs(self, data): | |
119 | self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data) | |
120 | ||
121 | def advance_state_machine(self, tms): | |
122 | self.oldstate = self.state | |
123 | ||
124 | # Intro "tree" | |
125 | if self.state == St.TEST_LOGIC_RESET: | |
126 | self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE | |
127 | elif self.state == St.RUN_TEST_IDLE: | |
128 | self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE | |
129 | ||
130 | # DR "tree" | |
131 | elif self.state == St.SELECT_DR_SCAN: | |
132 | self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR | |
133 | elif self.state == St.CAPTURE_DR: | |
134 | self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR | |
135 | elif self.state == St.SHIFT_DR: | |
136 | self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR | |
137 | elif self.state == St.EXIT1_DR: | |
138 | self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR | |
139 | elif self.state == St.PAUSE_DR: | |
140 | self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR | |
141 | elif self.state == St.EXIT2_DR: | |
142 | self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR | |
143 | elif self.state == St.UPDATE_DR: | |
144 | self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE | |
145 | ||
146 | # IR "tree" | |
147 | elif self.state == St.SELECT_IR_SCAN: | |
148 | self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR | |
149 | elif self.state == St.CAPTURE_IR: | |
150 | self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR | |
151 | elif self.state == St.SHIFT_IR: | |
152 | self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR | |
153 | elif self.state == St.EXIT1_IR: | |
154 | self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR | |
155 | elif self.state == St.PAUSE_IR: | |
156 | self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR | |
157 | elif self.state == St.EXIT2_IR: | |
158 | self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR | |
159 | elif self.state == St.UPDATE_IR: | |
160 | self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE | |
161 | ||
162 | def handle_rising_tck_edge(self, pins): | |
163 | (tdi, tdo, tck, tms, trst, srst, rtck) = pins | |
164 | ||
165 | # Rising TCK edges always advance the state machine. | |
166 | self.advance_state_machine(tms) | |
167 | ||
168 | if self.first: | |
169 | # Save the start sample and item for later (no output yet). | |
170 | self.ss_item = self.samplenum | |
171 | self.first = False | |
172 | else: | |
173 | # Output the saved item (from the last CLK edge to the current). | |
174 | self.es_item = self.samplenum | |
175 | # Output the old state (from last rising TCK edge to current one). | |
176 | self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]]) | |
177 | self.putp(['NEW STATE', self.state.value]) | |
178 | ||
179 | # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values. | |
180 | if self.oldstate.value.startswith('SHIFT-') or \ | |
181 | self.oldstate.value.startswith('EXIT1-'): | |
182 | if self.first_bit: | |
183 | self.ss_bitstring = self.samplenum | |
184 | self.first_bit = False | |
185 | else: | |
186 | self.putx([16, [str(self.bits_tdi[0])]]) | |
187 | self.putx([17, [str(self.bits_tdo[0])]]) | |
188 | # Use self.samplenum as ES of the previous bit. | |
189 | self.bits_samplenums_tdi[0][1] = self.samplenum | |
190 | self.bits_samplenums_tdo[0][1] = self.samplenum | |
191 | ||
192 | self.bits_tdi.insert(0, tdi) | |
193 | self.bits_tdo.insert(0, tdo) | |
194 | ||
195 | # Use self.samplenum as SS of the current bit. | |
196 | self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) | |
197 | self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) | |
198 | ||
199 | # Output all TDI/TDO bits if we just switched to UPDATE-*. | |
200 | if self.state.value.startswith('UPDATE-'): | |
201 | ||
202 | self.es_bitstring = self.samplenum | |
203 | ||
204 | t = self.state.value[-2:] + ' TDI' | |
205 | b = ''.join(map(str, self.bits_tdi[1:])) | |
206 | h = ' (0x%x' % int('0b0' + b, 2) + ')' | |
207 | s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits' | |
208 | self.putx_bs([18, [s]]) | |
209 | self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]]) | |
210 | self.bits_tdi = [] | |
211 | self.bits_samplenums_tdi = [] | |
212 | ||
213 | t = self.state.value[-2:] + ' TDO' | |
214 | b = ''.join(map(str, self.bits_tdo[1:])) | |
215 | h = ' (0x%x' % int('0b0' + b, 2) + ')' | |
216 | s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits' | |
217 | self.putx_bs([19, [s]]) | |
218 | self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]]) | |
219 | self.bits_tdo = [] | |
220 | self.bits_samplenums_tdo = [] | |
221 | ||
222 | self.first_bit = True | |
223 | ||
224 | self.ss_bitstring = self.samplenum | |
225 | ||
226 | self.ss_item = self.samplenum | |
227 | ||
228 | def decode(self): | |
229 | while True: | |
230 | # Wait for a rising edge on TCK. | |
231 | self.handle_rising_tck_edge(self.wait({2: 'r'})) |