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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | # Helper dictionary for edge detection. | |
24 | edge_detector = { | |
25 | 'rising': lambda x, y: bool(not x and y), | |
26 | 'falling': lambda x, y: bool(x and not y), | |
27 | 'both': lambda x, y: bool(x ^ y), | |
28 | } | |
29 | ||
30 | class SamplerateError(Exception): | |
31 | pass | |
32 | ||
33 | class Decoder(srd.Decoder): | |
34 | api_version = 2 | |
35 | id = 'jitter' | |
36 | name = 'Jitter' | |
37 | longname = 'Timing jitter calculation' | |
38 | desc = 'Retrieves the timing jitter between two digital signals.' | |
39 | license = 'gplv2+' | |
40 | inputs = ['logic'] | |
41 | outputs = ['jitter'] | |
42 | channels = ( | |
43 | {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'}, | |
44 | {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'}, | |
45 | ) | |
46 | options = ( | |
47 | {'id': 'clk_polarity', 'desc': 'Clock edge polarity', | |
48 | 'default': 'rising', 'values': ('rising', 'falling', 'both')}, | |
49 | {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity', | |
50 | 'default': 'rising', 'values': ('rising', 'falling', 'both')}, | |
51 | ) | |
52 | annotations = ( | |
53 | ('jitter', 'Jitter value'), | |
54 | ('clk_missed', 'Clock missed'), | |
55 | ('sig_missed', 'Signal missed'), | |
56 | ) | |
57 | annotation_rows = ( | |
58 | ('jitter', 'Jitter values', (0,)), | |
59 | ('clk_missed', 'Clock missed', (1,)), | |
60 | ('sig_missed', 'Signal missed', (2,)), | |
61 | ) | |
62 | binary = ( | |
63 | ('ascii-float', 'Jitter values as newline-separated ASCII floats'), | |
64 | ) | |
65 | ||
66 | def __init__(self, **kwargs): | |
67 | self.state = 'CLK' | |
68 | self.samplerate = None | |
69 | self.oldpin = None | |
70 | self.oldclk = self.oldsig = None | |
71 | self.clk_start = None | |
72 | self.sig_start = None | |
73 | self.clk_missed = 0 | |
74 | self.sig_missed = 0 | |
75 | ||
76 | def start(self): | |
77 | self.clk_edge = edge_detector[self.options['clk_polarity']] | |
78 | self.sig_edge = edge_detector[self.options['sig_polarity']] | |
79 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
80 | self.out_bin = self.register(srd.OUTPUT_BINARY) | |
81 | self.out_clk_missed = self.register(srd.OUTPUT_META, | |
82 | meta=(int, 'Clock missed', 'Clock transition missed')) | |
83 | self.out_sig_missed = self.register(srd.OUTPUT_META, | |
84 | meta=(int, 'Signal missed', 'Resulting signal transition missed')) | |
85 | ||
86 | def metadata(self, key, value): | |
87 | if key == srd.SRD_CONF_SAMPLERATE: | |
88 | self.samplerate = value | |
89 | ||
90 | # Helper function for jitter time annotations. | |
91 | def putx(self, delta): | |
92 | # Adjust granularity. | |
93 | if delta == 0 or delta >= 1: | |
94 | delta_s = u"%us" % (delta) | |
95 | elif delta <= 1e-12: | |
96 | delta_s = u"%.1ffs" % (delta * 1e15) | |
97 | elif delta <= 1e-9: | |
98 | delta_s = u"%.1fps" % (delta * 1e12) | |
99 | elif delta <= 1e-6: | |
100 | delta_s = u"%.1fns" % (delta * 1e9) | |
101 | elif delta <= 1e-3: | |
102 | delta_s = u"%.1fμs" % (delta * 1e6) | |
103 | else: | |
104 | delta_s = u"%.1fms" % (delta * 1e3) | |
105 | ||
106 | self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]]) | |
107 | ||
108 | # Helper function for ASCII float jitter values (one value per line). | |
109 | def putb(self, delta): | |
110 | if delta is None: | |
111 | return | |
112 | # Format the delta to an ASCII float value terminated by a newline. | |
113 | x = str(delta) + '\n' | |
114 | self.put(self.clk_start, self.sig_start, self.out_bin, | |
115 | (0, x.encode('UTF-8'))) | |
116 | ||
117 | # Helper function for missed clock and signal annotations. | |
118 | def putm(self, data): | |
119 | self.put(self.samplenum, self.samplenum, self.out_ann, data) | |
120 | ||
121 | def handle_clk(self, clk, sig): | |
122 | if self.clk_start == self.samplenum: | |
123 | # Clock transition already treated. | |
124 | # We have done everything we can with this sample. | |
125 | return True | |
126 | ||
127 | if self.clk_edge(self.oldclk, clk): | |
128 | # Clock edge found. | |
129 | # We note the sample and move to the next state. | |
130 | self.clk_start = self.samplenum | |
131 | self.state = 'SIG' | |
132 | return False | |
133 | else: | |
134 | if self.sig_start is not None \ | |
135 | and self.sig_start != self.samplenum \ | |
136 | and self.sig_edge(self.oldsig, sig): | |
137 | # If any transition in the resulting signal | |
138 | # occurs while we are waiting for a clock, | |
139 | # we increase the missed signal counter. | |
140 | self.sig_missed += 1 | |
141 | self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed) | |
142 | self.putm([2, ['Missed signal', 'MS']]) | |
143 | # No clock edge found, we have done everything we | |
144 | # can with this sample. | |
145 | return True | |
146 | ||
147 | def handle_sig(self, clk, sig): | |
148 | if self.sig_start == self.samplenum: | |
149 | # Signal transition already treated. | |
150 | # We have done everything we can with this sample. | |
151 | return True | |
152 | ||
153 | if self.sig_edge(self.oldsig, sig): | |
154 | # Signal edge found. | |
155 | # We note the sample, calculate the jitter | |
156 | # and move to the next state. | |
157 | self.sig_start = self.samplenum | |
158 | self.state = 'CLK' | |
159 | # Calculate and report the timing jitter. | |
160 | delta = (self.sig_start - self.clk_start) / self.samplerate | |
161 | self.putx(delta) | |
162 | self.putb(delta) | |
163 | return False | |
164 | else: | |
165 | if self.clk_start != self.samplenum \ | |
166 | and self.clk_edge(self.oldclk, clk): | |
167 | # If any transition in the clock signal | |
168 | # occurs while we are waiting for a resulting | |
169 | # signal, we increase the missed clock counter. | |
170 | self.clk_missed += 1 | |
171 | self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed) | |
172 | self.putm([1, ['Missed clock', 'MC']]) | |
173 | # No resulting signal edge found, we have done | |
174 | # everything we can with this sample. | |
175 | return True | |
176 | ||
177 | def decode(self, ss, es, data): | |
178 | if not self.samplerate: | |
179 | raise SamplerateError('Cannot decode without samplerate.') | |
180 | ||
181 | for (self.samplenum, pins) in data: | |
182 | # We are only interested in transitions. | |
183 | if self.oldpin == pins: | |
184 | continue | |
185 | ||
186 | self.oldpin, (clk, sig) = pins, pins | |
187 | ||
188 | if self.oldclk is None and self.oldsig is None: | |
189 | self.oldclk, self.oldsig = clk, sig | |
190 | ||
191 | # State machine: | |
192 | # For each sample we can move 2 steps forward in the state machine. | |
193 | while True: | |
194 | # Clock state has the lead. | |
195 | if self.state == 'CLK': | |
196 | if self.handle_clk(clk, sig): | |
197 | break | |
198 | if self.state == 'SIG': | |
199 | if self.handle_sig(clk, sig): | |
200 | break | |
201 | ||
202 | # Save current CLK/SIG values for the next round. | |
203 | self.oldclk, self.oldsig = clk, sig |