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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2015 Jeremy Swanson <jeremy@rakocontrols.com> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | ||
22 | class SamplerateError(Exception): | |
23 | pass | |
24 | ||
25 | class Decoder(srd.Decoder): | |
26 | api_version = 3 | |
27 | id = 'dsi' | |
28 | name = 'DSI' | |
29 | longname = 'Digital Serial Interface' | |
30 | desc = 'Digital Serial Interface (DSI) lighting protocol.' | |
31 | license = 'gplv2+' | |
32 | inputs = ['logic'] | |
33 | outputs = [] | |
34 | tags = ['Embedded/industrial', 'Lighting'] | |
35 | channels = ( | |
36 | {'id': 'dsi', 'name': 'DSI', 'desc': 'DSI data line'}, | |
37 | ) | |
38 | options = ( | |
39 | {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high', | |
40 | 'values': ('active-low', 'active-high')}, | |
41 | ) | |
42 | annotations = ( | |
43 | ('bit', 'Bit'), | |
44 | ('startbit', 'Start bit'), | |
45 | ('level', 'Dimmer level'), | |
46 | ('raw', 'Raw data'), | |
47 | ) | |
48 | annotation_rows = ( | |
49 | ('bits', 'Bits', (0,)), | |
50 | ('raw-vals', 'Raw data', (3,)), | |
51 | ('fields', 'Fields', (1, 2)), | |
52 | ) | |
53 | ||
54 | def __init__(self): | |
55 | self.reset() | |
56 | ||
57 | def reset(self): | |
58 | self.samplerate = None | |
59 | self.edges, self.bits, self.ss_es_bits = [], [], [] | |
60 | self.state = 'IDLE' | |
61 | ||
62 | def start(self): | |
63 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
64 | self.old_dsi = 1 if self.options['polarity'] == 'active-low' else 0 | |
65 | ||
66 | def metadata(self, key, value): | |
67 | if key == srd.SRD_CONF_SAMPLERATE: | |
68 | self.samplerate = value | |
69 | # One bit: 1666.7us (one half low, one half high). | |
70 | # This is how many samples are in 1TE. | |
71 | self.halfbit = int((self.samplerate * 0.0016667) / 2.0) | |
72 | ||
73 | def putb(self, bit1, bit2, data): | |
74 | ss, es = self.ss_es_bits[bit1][0], self.ss_es_bits[bit2][1] | |
75 | self.put(ss, es, self.out_ann, data) | |
76 | ||
77 | def handle_bits(self, length): | |
78 | a, c, f, g, b = 0, 0, 0, 0, self.bits | |
79 | # Individual raw bits. | |
80 | for i in range(length): | |
81 | if i == 0: | |
82 | ss = max(0, self.bits[0][0]) | |
83 | else: | |
84 | ss = self.ss_es_bits[i - 1][1] | |
85 | es = self.bits[i][0] + (self.halfbit * 2) | |
86 | self.ss_es_bits.append([ss, es]) | |
87 | self.putb(i, i, [0, ['%d' % self.bits[i][1]]]) | |
88 | # Bits[0:0]: Startbit | |
89 | s = ['Startbit: %d' % b[0][1], 'ST: %d' % b[0][1], 'ST', 'S', 'S'] | |
90 | self.putb(0, 0, [1, s]) | |
91 | self.putb(0, 0, [3, s]) | |
92 | # Bits[1:8] | |
93 | for i in range(8): | |
94 | f |= (b[1 + i][1] << (7 - i)) | |
95 | g = f / 2.55 | |
96 | if length == 9: # BACKWARD Frame | |
97 | s = ['Data: %02X' % f, 'Dat: %02X' % f, | |
98 | 'Dat: %02X' % f, 'D: %02X' % f, 'D'] | |
99 | self.putb(1, 8, [3, s]) | |
100 | s = ['Level: %d%%' % g, 'Lev: %d%%' % g, | |
101 | 'Lev: %d%%' % g, 'L: %d' % g, 'D'] | |
102 | self.putb(1, 8, [2, s]) | |
103 | return | |
104 | ||
105 | def reset_decoder_state(self): | |
106 | self.edges, self.bits, self.ss_es_bits = [], [], [] | |
107 | self.state = 'IDLE' | |
108 | ||
109 | def decode(self): | |
110 | if not self.samplerate: | |
111 | raise SamplerateError('Cannot decode without samplerate.') | |
112 | bit = 0 | |
113 | while True: | |
114 | # TODO: Come up with more appropriate self.wait() conditions. | |
115 | (self.dsi,) = self.wait() | |
116 | if self.options['polarity'] == 'active-high': | |
117 | self.dsi ^= 1 # Invert. | |
118 | ||
119 | # State machine. | |
120 | if self.state == 'IDLE': | |
121 | # Wait for any edge (rising or falling). | |
122 | if self.old_dsi == self.dsi: | |
123 | continue | |
124 | # Add in the first half of the start bit. | |
125 | self.edges.append(self.samplenum - int(self.halfbit)) | |
126 | self.edges.append(self.samplenum) | |
127 | # Start bit is 0->1. | |
128 | self.phase0 = self.dsi ^ 1 | |
129 | self.state = 'PHASE1' | |
130 | self.old_dsi = self.dsi | |
131 | # Get the next sample point. | |
132 | self.old_dsi = self.dsi | |
133 | continue | |
134 | ||
135 | if self.old_dsi != self.dsi: | |
136 | self.edges.append(self.samplenum) | |
137 | elif self.samplenum == (self.edges[-1] + int(self.halfbit * 1.5)): | |
138 | self.edges.append(self.samplenum - int(self.halfbit * 0.5)) | |
139 | else: | |
140 | continue | |
141 | ||
142 | bit = self.old_dsi | |
143 | if self.state == 'PHASE0': | |
144 | self.phase0 = bit | |
145 | self.state = 'PHASE1' | |
146 | elif self.state == 'PHASE1': | |
147 | if (bit == 1) and (self.phase0 == 1): # Stop bit. | |
148 | if len(self.bits) == 17 or len(self.bits) == 9: | |
149 | # Forward or Backward. | |
150 | self.handle_bits(len(self.bits)) | |
151 | self.reset_decoder_state() # Reset upon errors. | |
152 | continue | |
153 | else: | |
154 | self.bits.append([self.edges[-3], bit]) | |
155 | self.state = 'PHASE0' | |
156 | ||
157 | self.old_dsi = self.dsi |