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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2020 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | ## | |
20 | ||
21 | import re | |
22 | import sigrokdecode as srd | |
23 | from common.srdhelper import bcd2int, SrdIntEnum | |
24 | ||
25 | days_of_week = ( | |
26 | 'Sunday', 'Monday', 'Tuesday', 'Wednesday', | |
27 | 'Thursday', 'Friday', 'Saturday', | |
28 | ) | |
29 | ||
30 | regs = ( | |
31 | 'Seconds', 'Minutes', 'Hours', 'Day', 'Date', 'Month', 'Year', | |
32 | 'Control', 'RAM', | |
33 | ) | |
34 | ||
35 | bits = ( | |
36 | 'Clock halt', 'Seconds', 'Reserved', 'Minutes', '12/24 hours', 'AM/PM', | |
37 | 'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM', | |
38 | ) | |
39 | ||
40 | rates = { | |
41 | 0b00: '1Hz', | |
42 | 0b01: '4096Hz', | |
43 | 0b10: '8192Hz', | |
44 | 0b11: '32768Hz', | |
45 | } | |
46 | ||
47 | DS1307_I2C_ADDRESS = 0x68 | |
48 | ||
49 | def regs_and_bits(): | |
50 | l = [('reg_' + r.lower(), r + ' register') for r in regs] | |
51 | l += [('bit_' + re.sub('\/| ', '_', b).lower(), b + ' bit') for b in bits] | |
52 | return tuple(l) | |
53 | ||
54 | a = ['REG_' + r.upper() for r in regs] + \ | |
55 | ['BIT_' + re.sub('\/| ', '_', b).upper() for b in bits] + \ | |
56 | ['READ_DATE_TIME', 'WRITE_DATE_TIME', 'READ_REG', 'WRITE_REG', 'WARNING'] | |
57 | Ann = SrdIntEnum.from_list('Ann', a) | |
58 | ||
59 | class Decoder(srd.Decoder): | |
60 | api_version = 3 | |
61 | id = 'ds1307' | |
62 | name = 'DS1307' | |
63 | longname = 'Dallas DS1307' | |
64 | desc = 'Dallas DS1307 realtime clock module protocol.' | |
65 | license = 'gplv2+' | |
66 | inputs = ['i2c'] | |
67 | outputs = [] | |
68 | tags = ['Clock/timing', 'IC'] | |
69 | annotations = regs_and_bits() + ( | |
70 | ('read_date_time', 'Read date/time'), | |
71 | ('write_date_time', 'Write date/time'), | |
72 | ('read_reg', 'Register read'), | |
73 | ('write_reg', 'Register write'), | |
74 | ('warning', 'Warning'), | |
75 | ) | |
76 | annotation_rows = ( | |
77 | ('bits', 'Bits', Ann.prefixes('BIT_')), | |
78 | ('regs', 'Registers', Ann.prefixes('REG_')), | |
79 | ('date_time', 'Date/time', Ann.prefixes('READ_ WRITE_')), | |
80 | ('warnings', 'Warnings', (Ann.WARNING,)), | |
81 | ) | |
82 | ||
83 | def __init__(self): | |
84 | self.reset() | |
85 | ||
86 | def reset(self): | |
87 | self.state = 'IDLE' | |
88 | self.hours = -1 | |
89 | self.minutes = -1 | |
90 | self.seconds = -1 | |
91 | self.days = -1 | |
92 | self.date = -1 | |
93 | self.months = -1 | |
94 | self.years = -1 | |
95 | self.bits = [] | |
96 | ||
97 | def start(self): | |
98 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
99 | ||
100 | def putx(self, data): | |
101 | self.put(self.ss, self.es, self.out_ann, data) | |
102 | ||
103 | def putd(self, bit1, bit2, data): | |
104 | self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data) | |
105 | ||
106 | def putr(self, bit): | |
107 | self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann, | |
108 | [Ann.BIT_RESERVED, ['Reserved bit', 'Reserved', 'Rsvd', 'R']]) | |
109 | ||
110 | def handle_reg_0x00(self, b): # Seconds (0-59) / Clock halt bit | |
111 | self.putd(7, 0, [Ann.REG_SECONDS, ['Seconds', 'Sec', 'S']]) | |
112 | ch = 1 if (b & (1 << 7)) else 0 | |
113 | self.putd(7, 7, [Ann.BIT_CLOCK_HALT, ['Clock halt: %d' % ch, | |
114 | 'Clk hlt: %d' % ch, 'CH: %d' % ch, 'CH']]) | |
115 | s = self.seconds = bcd2int(b & 0x7f) | |
116 | self.putd(6, 0, [Ann.BIT_SECONDS, ['Second: %d' % s, 'Sec: %d' % s, | |
117 | 'S: %d' % s, 'S']]) | |
118 | ||
119 | def handle_reg_0x01(self, b): # Minutes (0-59) | |
120 | self.putd(7, 0, [Ann.REG_MINUTES, ['Minutes', 'Min', 'M']]) | |
121 | self.putr(7) | |
122 | m = self.minutes = bcd2int(b & 0x7f) | |
123 | self.putd(6, 0, [Ann.BIT_MINUTES, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']]) | |
124 | ||
125 | def handle_reg_0x02(self, b): # Hours (1-12+AM/PM or 0-23) | |
126 | self.putd(7, 0, [Ann.REG_HOURS, ['Hours', 'H']]) | |
127 | self.putr(7) | |
128 | ampm_mode = True if (b & (1 << 6)) else False | |
129 | if ampm_mode: | |
130 | self.putd(6, 6, [Ann.BIT_12_24_HOURS, ['12-hour mode', '12h mode', '12h']]) | |
131 | a = 'PM' if (b & (1 << 5)) else 'AM' | |
132 | self.putd(5, 5, [Ann.BIT_AM_PM, [a, a[0]]]) | |
133 | h = self.hours = bcd2int(b & 0x1f) | |
134 | self.putd(4, 0, [Ann.BIT_HOURS, ['Hour: %d' % h, 'H: %d' % h, 'H']]) | |
135 | else: | |
136 | self.putd(6, 6, [Ann.BIT_12_24_HOURS, ['24-hour mode', '24h mode', '24h']]) | |
137 | h = self.hours = bcd2int(b & 0x3f) | |
138 | self.putd(5, 0, [Ann.BIT_HOURS, ['Hour: %d' % h, 'H: %d' % h, 'H']]) | |
139 | ||
140 | def handle_reg_0x03(self, b): # Day / day of week (1-7) | |
141 | self.putd(7, 0, [Ann.REG_DAY, ['Day of week', 'Day', 'D']]) | |
142 | for i in (7, 6, 5, 4, 3): | |
143 | self.putr(i) | |
144 | w = self.days = bcd2int(b & 0x07) | |
145 | ws = days_of_week[self.days - 1] | |
146 | self.putd(2, 0, [Ann.BIT_DAY, ['Weekday: %s' % ws, 'WD: %s' % ws, 'WD', 'W']]) | |
147 | ||
148 | def handle_reg_0x04(self, b): # Date (1-31) | |
149 | self.putd(7, 0, [Ann.REG_DATE, ['Date', 'D']]) | |
150 | for i in (7, 6): | |
151 | self.putr(i) | |
152 | d = self.date = bcd2int(b & 0x3f) | |
153 | self.putd(5, 0, [Ann.BIT_DATE, ['Date: %d' % d, 'D: %d' % d, 'D']]) | |
154 | ||
155 | def handle_reg_0x05(self, b): # Month (1-12) | |
156 | self.putd(7, 0, [Ann.REG_MONTH, ['Month', 'Mon', 'M']]) | |
157 | for i in (7, 6, 5): | |
158 | self.putr(i) | |
159 | m = self.months = bcd2int(b & 0x1f) | |
160 | self.putd(4, 0, [Ann.BIT_MONTH, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']]) | |
161 | ||
162 | def handle_reg_0x06(self, b): # Year (0-99) | |
163 | self.putd(7, 0, [Ann.REG_YEAR, ['Year', 'Y']]) | |
164 | y = self.years = bcd2int(b & 0xff) | |
165 | self.years += 2000 | |
166 | self.putd(7, 0, [Ann.BIT_YEAR, ['Year: %d' % y, 'Y: %d' % y, 'Y']]) | |
167 | ||
168 | def handle_reg_0x07(self, b): # Control Register | |
169 | self.putd(7, 0, [Ann.REG_CONTROL, ['Control', 'Ctrl', 'C']]) | |
170 | for i in (6, 5, 3, 2): | |
171 | self.putr(i) | |
172 | o = 1 if (b & (1 << 7)) else 0 | |
173 | s = 1 if (b & (1 << 4)) else 0 | |
174 | s2 = 'en' if (b & (1 << 4)) else 'dis' | |
175 | r = rates[b & 0x03] | |
176 | self.putd(7, 7, [Ann.BIT_OUT, ['Output control: %d' % o, | |
177 | 'OUT: %d' % o, 'O: %d' % o, 'O']]) | |
178 | self.putd(4, 4, [Ann.BIT_SQWE, ['Square wave output: %sabled' % s2, | |
179 | 'SQWE: %sabled' % s2, 'SQWE: %d' % s, 'S: %d' % s, 'S']]) | |
180 | self.putd(1, 0, [Ann.BIT_RS, ['Square wave output rate: %s' % r, | |
181 | 'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r, | |
182 | 'RS: %s' % s, 'RS', 'R']]) | |
183 | ||
184 | def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f) | |
185 | self.putd(7, 0, [Ann.REG_RAM, ['RAM', 'R']]) | |
186 | self.putd(7, 0, [Ann.BIT_RAM, ['SRAM: 0x%02X' % b, '0x%02X' % b]]) | |
187 | ||
188 | def output_datetime(self, cls, rw): | |
189 | # TODO: Handle read/write of only parts of these items. | |
190 | d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % ( | |
191 | days_of_week[self.days - 1], self.date, self.months, | |
192 | self.years, self.hours, self.minutes, self.seconds) | |
193 | self.put(self.ss_block, self.es, self.out_ann, | |
194 | [cls, ['%s date/time: %s' % (rw, d)]]) | |
195 | ||
196 | def handle_reg(self, b): | |
197 | r = self.reg if self.reg < 8 else 0x3f | |
198 | fn = getattr(self, 'handle_reg_0x%02x' % r) | |
199 | fn(b) | |
200 | # Honor address auto-increment feature of the DS1307. When the | |
201 | # address reaches 0x3f, it will wrap around to address 0. | |
202 | self.reg += 1 | |
203 | if self.reg > 0x3f: | |
204 | self.reg = 0 | |
205 | ||
206 | def is_correct_chip(self, addr): | |
207 | if addr == DS1307_I2C_ADDRESS: | |
208 | return True | |
209 | self.put(self.ss_block, self.es, self.out_ann, | |
210 | [Ann.WARNING, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]]) | |
211 | return False | |
212 | ||
213 | def decode(self, ss, es, data): | |
214 | cmd, databyte = data | |
215 | ||
216 | # Collect the 'BITS' packet, then return. The next packet is | |
217 | # guaranteed to belong to these bits we just stored. | |
218 | if cmd == 'BITS': | |
219 | self.bits = databyte | |
220 | return | |
221 | ||
222 | # Store the start/end samples of this I²C packet. | |
223 | self.ss, self.es = ss, es | |
224 | ||
225 | # State machine. | |
226 | if self.state == 'IDLE': | |
227 | # Wait for an I²C START condition. | |
228 | if cmd != 'START': | |
229 | return | |
230 | self.state = 'GET SLAVE ADDR' | |
231 | self.ss_block = ss | |
232 | elif self.state == 'GET SLAVE ADDR': | |
233 | # Wait for an address write operation. | |
234 | if cmd != 'ADDRESS WRITE': | |
235 | return | |
236 | if not self.is_correct_chip(databyte): | |
237 | self.state = 'IDLE' | |
238 | return | |
239 | self.state = 'GET REG ADDR' | |
240 | elif self.state == 'GET REG ADDR': | |
241 | # Wait for a data write (master selects the slave register). | |
242 | if cmd != 'DATA WRITE': | |
243 | return | |
244 | self.reg = databyte | |
245 | self.state = 'WRITE RTC REGS' | |
246 | elif self.state == 'WRITE RTC REGS': | |
247 | # If we see a Repeated Start here, it's an RTC read. | |
248 | if cmd == 'START REPEAT': | |
249 | self.state = 'READ RTC REGS' | |
250 | return | |
251 | # Otherwise: Get data bytes until a STOP condition occurs. | |
252 | if cmd == 'DATA WRITE': | |
253 | self.handle_reg(databyte) | |
254 | elif cmd == 'STOP': | |
255 | self.output_datetime(Ann.WRITE_DATE_TIME, 'Written') | |
256 | self.state = 'IDLE' | |
257 | elif self.state == 'READ RTC REGS': | |
258 | # Wait for an address read operation. | |
259 | if cmd != 'ADDRESS READ': | |
260 | return | |
261 | if not self.is_correct_chip(databyte): | |
262 | self.state = 'IDLE' | |
263 | return | |
264 | self.state = 'READ RTC REGS2' | |
265 | elif self.state == 'READ RTC REGS2': | |
266 | if cmd == 'DATA READ': | |
267 | self.handle_reg(databyte) | |
268 | elif cmd == 'STOP': | |
269 | self.output_datetime(Ann.READ_DATE_TIME, 'Read') | |
270 | self.state = 'IDLE' |