]>
Commit | Line | Data |
---|---|---|
8da8c826 VV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2019 Vitaliy Vorobyov | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <config.h> | |
21 | #include <string.h> | |
22 | #include "protocol.h" | |
9e0693f9 UH |
23 | |
24 | /* | |
25 | * Register description (all registers are 32bit): | |
26 | * | |
27 | * Rx - means register with index x (register address is x*4) | |
28 | * | |
29 | * R0(wr): trigger sel0 (low/high) | |
30 | * R0(rd): n*256 samples (post trigger) captured | |
31 | * | |
32 | * R1(wr): trigger sel1 (level/edge) | |
33 | * R1(rd): current sampled value | |
34 | * | |
35 | * R2(wr): trigger enable mask | |
36 | * | |
37 | * R2(rd): (status register) | |
38 | * b0: 1 - keys entered | |
39 | * b1: 1 - triggered | |
40 | * b3: 1 - capture done | |
41 | * | |
42 | * not configured: B6FF9C97, 12FF9C97, 92FF9C97, 16FF9C97, ... | |
43 | * configured: A5A5A5A0, after enter keys A5A5A5A1 | |
44 | * | |
45 | * sel1 (one bit per channel): | |
46 | * 0 - level triggered | |
47 | * 1 - edge triggered | |
48 | * | |
49 | * sel0 (one bit per channel): | |
50 | * 0 - (low level trigger, sel1=0), (falling edge, sel1=1) | |
51 | * 1 - (high level trigger, sel1=0), (raising edge, sel1=1) | |
52 | * | |
53 | * mask (one bit per channel): | |
54 | * 0 - disable trigger on channel n | |
55 | * 1 - enable trigger on channel n | |
56 | * | |
57 | * R3: upload base address or num samples (0x300000) | |
58 | * | |
59 | * R4: pll divisor - 1 | |
60 | * 0 - div 1 (no division) | |
61 | * 1 - div 2 | |
62 | * 2 - div 3 | |
63 | * ... | |
64 | * n-1 - div n | |
65 | * | |
66 | * R5(rd/wr): | |
67 | * b0: 1 - enable pll mul 2, 0 - disable pll mul 2 | |
68 | * b1: ?? | |
69 | * b2: ?? | |
70 | * b3: ?? | |
71 | * b4: | |
72 | * b5: ->0->1 upload next data chunk (to pc) | |
73 | * b6: ?? | |
74 | * b7: 0 - enable pll mul 1.25, 1 - disable pll mul 1.25 | |
75 | * b8: ?? | |
76 | * | |
77 | * R6: post trigger depth, value x means (x+1)*256 (samples), min value is 1 | |
78 | * R7: pre trigger depth, value y means (y+1)*256 (samples), min value is 1 | |
79 | * (x+1)*256 + (y+1)*256 <= 64M | |
80 | * | |
81 | * R9: PWM1 HI (1 width-1) | |
82 | * R10: PWM1 LO (0 width-1) | |
83 | * | |
84 | * R11: PWM2 HI (1 width-1) | |
85 | * R12: PWM2 LO (0 width-1) | |
86 | * | |
87 | * R14: | |
88 | * 1 - start sample? | |
89 | * 0 - upload done? | |
90 | * | |
91 | * R16: rom key 0 | |
92 | * R17: rom key 1 | |
93 | * | |
94 | * key0 is F6 81 13 64 | |
95 | * key1 is 00 00 00 00 | |
96 | * | |
97 | * start sample: | |
98 | * r5 <= b2 <= 0 | |
99 | * r5 <= b3 <= 0 | |
100 | * r5 <= b5 <= 0 | |
101 | * | |
102 | * r5 <= b6 <= 1 | |
103 | * r5 <= b1 <= 1 | |
104 | * r5 <= b1 <= 0 | |
105 | * | |
106 | * r5 <= b8 <= 1 | |
107 | * r5 <= b8 <= 0 | |
108 | * | |
109 | * r5 <= b6 <= 1 | |
110 | * r5 <= b2 <= 1 | |
111 | * | |
112 | * read back: | |
113 | * r5 <= 0x08 (b3) | |
114 | * r5 <= 0x28 (b5,b3) | |
115 | */ | |
116 | ||
117 | #define BITSTREAM_NAME "sysclk-sla5032.bit" | |
118 | #define BITSTREAM_MAX_SIZE (512 * 1024) /* Bitstream size limit for safety */ | |
119 | #define BITSTREAM_HEADER_SIZE 0x69 | |
120 | #define FW_CHUNK_SIZE 250 | |
121 | #define XILINX_SYNC_WORD 0xAA995566 | |
122 | ||
123 | static int la_write_cmd_buf(const struct sr_usb_dev_inst *usb, uint8_t cmd, | |
124 | unsigned int addr, unsigned int len, const void *data) | |
125 | { | |
126 | uint8_t *cmd_pkt; | |
127 | int ret, xfer_len; | |
128 | int cmd_len; | |
129 | ||
130 | cmd_pkt = g_try_malloc(len + 10); | |
131 | if (!cmd_pkt) { | |
132 | ret = SR_ERR_MALLOC; | |
133 | goto exit; | |
134 | } | |
135 | ||
136 | cmd_pkt[0] = cmd; | |
137 | cmd_len = 1; | |
138 | xfer_len = 0; | |
139 | ||
140 | switch(cmd) { | |
141 | case CMD_INIT_FW_UPLOAD: /* init firmware upload */ | |
142 | break; | |
143 | case CMD_UPLOAD_FW_CHUNK: | |
144 | cmd_pkt[1] = len; | |
145 | cmd_len += 1 + len; | |
146 | memcpy(&cmd_pkt[2], data, len); | |
147 | break; | |
148 | case CMD_READ_REG: /* read register */ | |
149 | cmd_pkt[1] = addr; | |
150 | cmd_pkt[2] = len; | |
151 | cmd_len += 2; | |
152 | break; | |
153 | case CMD_WRITE_REG: /* write register */ | |
154 | cmd_pkt[1] = addr; | |
155 | cmd_pkt[2] = len; | |
156 | cmd_len += 2 + len; | |
157 | memcpy(&cmd_pkt[3], data, len); | |
158 | break; | |
159 | case CMD_READ_MEM: /* read mem */ | |
160 | cmd_pkt[1] = (addr >> 8) & 0xFF; | |
161 | cmd_pkt[2] = addr & 0xFF; | |
162 | cmd_pkt[3] = len; | |
163 | cmd_len += 3; | |
164 | break; | |
165 | case CMD_READ_DATA: /* read samples */ | |
166 | cmd_pkt[1] = addr; | |
167 | cmd_len += 1; | |
168 | break; | |
169 | } | |
170 | ||
171 | ret = libusb_bulk_transfer(usb->devhdl, EP_COMMAND, cmd_pkt, cmd_len, | |
172 | &xfer_len, USB_CMD_TIMEOUT_MS); | |
173 | if (ret != 0) { | |
174 | sr_dbg("Failed to send command %d: %s.", | |
175 | cmd, libusb_error_name(ret)); | |
176 | return SR_ERR; | |
177 | } | |
178 | ||
179 | if (xfer_len != cmd_len) { | |
180 | sr_dbg("Invalid send command response of length %d.", xfer_len); | |
181 | return SR_ERR; | |
182 | } | |
183 | ||
184 | exit: | |
185 | g_free(cmd_pkt); | |
186 | return ret; | |
187 | } | |
188 | ||
189 | static int la_read_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t *val) | |
190 | { | |
191 | int ret, xfer_len; | |
192 | uint32_t reply; | |
193 | ||
194 | ret = la_write_cmd_buf(usb, CMD_READ_REG, reg * sizeof(uint32_t), | |
195 | sizeof(reply), NULL); /* rd reg */ | |
196 | if (ret != SR_OK) | |
197 | return ret; | |
198 | ||
199 | ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)&reply, | |
200 | sizeof(reply), &xfer_len, USB_REPLY_TIMEOUT_MS); | |
201 | if (ret != SR_OK) | |
202 | return ret; | |
203 | ||
204 | if (xfer_len != sizeof(uint32_t)) { | |
205 | sr_dbg("Invalid register read response of length %d.", xfer_len); | |
206 | return SR_ERR; | |
207 | } | |
208 | ||
209 | *val = GUINT32_FROM_BE(reply); | |
210 | ||
211 | return ret; | |
212 | } | |
213 | ||
214 | static int la_write_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t val) | |
215 | { | |
216 | uint32_t val_be; | |
217 | ||
218 | val_be = GUINT32_TO_BE(val); | |
219 | ||
220 | return la_write_cmd_buf(usb, CMD_WRITE_REG, reg * sizeof(uint32_t), | |
221 | sizeof(val_be), &val_be); /* wr reg */ | |
222 | } | |
223 | ||
224 | static int la_read_mem(const struct sr_usb_dev_inst *usb, unsigned int addr, unsigned int len, void *data) | |
225 | { | |
226 | int ret, xfer_len; | |
227 | ||
228 | ret = la_write_cmd_buf(usb, CMD_READ_MEM, addr, len, NULL); /* rd mem */ | |
229 | if (ret != SR_OK) | |
230 | return ret; | |
231 | ||
232 | xfer_len = 0; | |
233 | ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)data, | |
234 | len, &xfer_len, USB_REPLY_TIMEOUT_MS); | |
235 | if (xfer_len != (int)len) { | |
236 | sr_dbg("Invalid memory read response of length %d.", xfer_len); | |
237 | return SR_ERR; | |
238 | } | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | static int la_read_samples(const struct sr_usb_dev_inst *usb, unsigned int addr) | |
244 | { | |
245 | return la_write_cmd_buf(usb, CMD_READ_DATA, addr, 0, NULL); /* rd samples */ | |
246 | } | |
247 | ||
98ed645e | 248 | static int sla5032_set_depth(const struct sr_usb_dev_inst *usb, uint32_t pre, uint32_t post) |
9e0693f9 UH |
249 | { |
250 | int ret; | |
251 | ||
252 | /* (pre + 1)*256 + (post + 1)*256 <= 64*1024*1024 */ | |
253 | ret = la_write_reg(usb, 7, pre); | |
254 | if (ret != SR_OK) | |
255 | return ret; | |
256 | ||
257 | return la_write_reg(usb, 6, post); | |
258 | } | |
259 | ||
98ed645e | 260 | static int sla5032_set_triggers(const struct sr_usb_dev_inst *usb, |
9e0693f9 UH |
261 | uint32_t trg_value, uint32_t trg_edge_mask, uint32_t trg_mask) |
262 | { | |
263 | int ret; | |
264 | ||
265 | sr_dbg("set trigger: val: %08X, e_mask: %08X, mask: %08X.", trg_value, | |
266 | trg_edge_mask, trg_mask); | |
267 | ||
268 | ret = la_write_reg(usb, 0, trg_value); | |
269 | if (ret != SR_OK) | |
270 | return ret; | |
271 | ||
272 | ret = la_write_reg(usb, 1, trg_edge_mask); | |
273 | if (ret != SR_OK) | |
274 | return ret; | |
275 | ||
276 | return la_write_reg(usb, 2, trg_mask); | |
277 | } | |
278 | ||
279 | static int la_set_res_reg_bit(const struct sr_usb_dev_inst *usb, | |
280 | unsigned int reg, unsigned int bit, unsigned int set_bit) | |
281 | { | |
282 | int ret; | |
283 | uint32_t v; | |
284 | ||
285 | v = 0; | |
286 | ret = la_read_reg(usb, reg, &v); | |
287 | if (ret != SR_OK) | |
288 | return ret; | |
289 | ||
290 | if (set_bit) | |
291 | v |= (1u << bit); | |
292 | else | |
293 | v &= ~(1u << bit); | |
294 | ||
295 | return la_write_reg(usb, reg, v); | |
296 | } | |
297 | ||
298 | struct pll_tbl_entry_t | |
299 | { | |
300 | unsigned int sr; | |
301 | uint32_t pll_div_minus_1; | |
302 | unsigned int pll_mul_flags; | |
303 | }; | |
304 | ||
305 | enum { | |
306 | PLL_MUL2 = 1, /* x2 */ | |
307 | PLL_MUL1_25 = 2, /* x1.25 */ | |
308 | }; | |
309 | ||
310 | static const struct pll_tbl_entry_t pll_tbl[] = { | |
311 | { 500000000, 0, PLL_MUL2 | PLL_MUL1_25 }, /* 500M = f*2*1.25/1 */ | |
312 | { 400000000, 0, PLL_MUL2 }, /* 400M = f*2/1 */ | |
313 | { 250000000, 0, PLL_MUL1_25 }, /* 250M = f*1.25/1 */ | |
314 | { 200000000, 0, 0 }, /* 200M = f/1 */ | |
315 | { 100000000, 1, 0 }, /* 100M = f/2 */ | |
316 | { 50000000, 3, 0 }, /* 50M = f/4 */ | |
317 | { 25000000, 7, 0 }, /* 25M = f/8 */ | |
318 | { 20000000, 9, 0 }, /* 20M = f/10 */ | |
319 | { 10000000, 19, 0 }, /* 10M = f/20 */ | |
320 | { 5000000, 39, 0 }, /* 5M = f/40 */ | |
321 | { 2000000, 99, 0 }, /* 2M = f/100 */ | |
322 | { 1000000, 199, 0 }, /* 1M = f/200 */ | |
323 | { 500000, 399, 0 }, /* 500k = f/400 */ | |
324 | { 200000, 999, 0 }, /* 200k = f/1000 */ | |
325 | { 100000, 1999, 0 }, /* 100k = f/2000 */ | |
326 | { 50000, 3999, 0 }, /* 50k = f/4000 */ | |
327 | { 20000, 9999, 0 }, /* 20k = f/10000 */ | |
328 | { 10000, 19999, 0 }, /* 10k = f/20000 */ | |
329 | { 5000, 39999, 0 }, /* 5k = f/40000 */ | |
330 | { 2000, 99999, 0 }, /* 2k = f/100000 */ | |
331 | }; | |
332 | ||
98ed645e | 333 | static int sla5032_set_samplerate(const struct sr_usb_dev_inst *usb, unsigned int sr) |
9e0693f9 UH |
334 | { |
335 | int i, ret; | |
336 | const struct pll_tbl_entry_t *e; | |
337 | ||
338 | e = NULL; | |
339 | for (i = 0; i < (int)ARRAY_SIZE(pll_tbl); i++) { | |
340 | if (sr == pll_tbl[i].sr) { | |
341 | e = &pll_tbl[i]; | |
342 | break; | |
343 | } | |
344 | } | |
345 | ||
346 | if (!e) | |
347 | return SR_ERR_SAMPLERATE; | |
348 | ||
349 | sr_dbg("set sample rate: %u.", e->sr); | |
350 | ||
351 | ret = la_write_reg(usb, 4, e->pll_div_minus_1); | |
352 | if (ret != SR_OK) | |
353 | return ret; | |
354 | ||
355 | ret = la_set_res_reg_bit(usb, 5, 0, | |
356 | (e->pll_mul_flags & PLL_MUL2) ? 1 : 0); /* bit0 (1=en_mul2) */ | |
357 | if (ret != SR_OK) | |
358 | return ret; | |
359 | ||
360 | return la_set_res_reg_bit(usb, 5, 7, | |
361 | (e->pll_mul_flags & PLL_MUL1_25) ? 0 : 1); /* bit7 (0=en_mul_1.25) */ | |
362 | } | |
363 | ||
98ed645e | 364 | static int sla5032_start_sample(const struct sr_usb_dev_inst *usb) |
9e0693f9 UH |
365 | { |
366 | int ret; | |
367 | const unsigned int bits[10][2] = { | |
368 | {2, 0}, {3, 0}, {5, 0}, {6, 1}, {1, 1}, | |
369 | {1, 0}, {8, 1}, {8, 0}, {6, 1}, {2, 1}, | |
370 | }; | |
371 | ||
372 | ret = la_write_reg(usb, 14, 1); | |
373 | if (ret != SR_OK) | |
374 | return ret; | |
375 | ||
376 | for (size_t i = 0; i < ARRAY_SIZE(bits); i++) { | |
377 | ret = la_set_res_reg_bit(usb, 5, bits[i][0], bits[i][1]); | |
378 | if (ret != SR_OK) | |
379 | return ret; | |
380 | } | |
381 | ||
382 | return ret; | |
383 | } | |
384 | ||
98ed645e | 385 | static int sla5032_get_status(const struct sr_usb_dev_inst *usb, uint32_t status[3]) |
9e0693f9 UH |
386 | { |
387 | int ret; | |
388 | uint32_t v; | |
389 | ||
390 | ret = la_read_reg(usb, 1, &status[0]); | |
391 | if (ret != SR_OK) | |
392 | return ret; | |
393 | ||
394 | status[1] = 1; /* wait trigger */ | |
395 | ||
396 | ret = la_read_reg(usb, 0, &status[2]); | |
397 | if (ret != SR_OK) | |
398 | return ret; | |
399 | ||
400 | v = 0; | |
401 | ret = la_read_reg(usb, 2, &v); | |
402 | if (ret != SR_OK) | |
403 | return ret; | |
404 | ||
405 | if (v & 8) { | |
406 | status[1] = 3; /* sample done */ | |
407 | sr_dbg("get status, reg2: %08X.", v); | |
408 | } else if (v & 2) { | |
409 | status[1] = 2; /* triggered */ | |
410 | } | |
411 | ||
412 | return ret; | |
413 | } | |
414 | ||
415 | static int la_read_samples_data(const struct sr_usb_dev_inst *usb, void *buf, | |
416 | unsigned int len, int *xfer_len) | |
417 | { | |
418 | return libusb_bulk_transfer(usb->devhdl, EP_DATA, (uint8_t *)buf, len, | |
419 | xfer_len, USB_DATA_TIMEOUT_MS); | |
420 | } | |
421 | ||
98ed645e | 422 | static int sla5032_read_data_chunk(const struct sr_usb_dev_inst *usb, |
9e0693f9 UH |
423 | void *buf, unsigned int len, int *xfer_len) |
424 | { | |
425 | int ret; | |
426 | ||
427 | ret = la_read_samples(usb, 3); | |
428 | if (ret != SR_OK) | |
429 | return ret; | |
430 | ||
431 | ret = la_write_reg(usb, 3, 0x300000); | |
432 | if (ret != SR_OK) | |
433 | return ret; | |
434 | ||
435 | ret = la_set_res_reg_bit(usb, 5, 4, 0); | |
436 | if (ret != SR_OK) | |
437 | return ret; | |
438 | ||
439 | ret = la_set_res_reg_bit(usb, 5, 4, 1); | |
440 | if (ret != SR_OK) | |
441 | return ret; | |
442 | ||
443 | return la_read_samples_data(usb, buf, len, xfer_len); | |
444 | } | |
445 | ||
98ed645e | 446 | static int sla5032_set_read_back(const struct sr_usb_dev_inst *usb) |
9e0693f9 UH |
447 | { |
448 | int ret; | |
449 | ||
450 | ret = la_write_reg(usb, 5, 0x08); | |
451 | if (ret != SR_OK) | |
452 | return ret; | |
453 | ||
454 | return la_write_reg(usb, 5, 0x28); | |
455 | } | |
456 | ||
f3178f12 | 457 | static int sla5032_set_pwm1(const struct sr_usb_dev_inst *usb, uint32_t hi, uint32_t lo) |
9e0693f9 UH |
458 | { |
459 | int ret; | |
460 | ||
461 | ret = la_write_reg(usb, 9, hi); | |
462 | if (ret != SR_OK) | |
463 | return ret; | |
464 | ||
465 | return la_write_reg(usb, 10, lo); | |
466 | } | |
467 | ||
f3178f12 | 468 | static int sla5032_set_pwm2(const struct sr_usb_dev_inst *usb, uint32_t hi, uint32_t lo) |
9e0693f9 UH |
469 | { |
470 | int ret; | |
471 | ||
472 | ret = la_write_reg(usb, 11, hi); | |
473 | if (ret != SR_OK) | |
474 | return ret; | |
475 | ||
476 | return la_write_reg(usb, 12, lo); | |
477 | } | |
478 | ||
f3178f12 | 479 | static int sla5032_write_reg14_zero(const struct sr_usb_dev_inst *usb) |
9e0693f9 UH |
480 | { |
481 | return la_write_reg(usb, 14, 0); | |
482 | } | |
483 | ||
484 | static int la_cfg_fpga_done(const struct sr_usb_dev_inst *usb, unsigned int addr) | |
485 | { | |
486 | uint8_t done_key[8]; | |
487 | uint32_t k0, k1; | |
488 | unsigned int reg2; | |
489 | int ret; | |
490 | ||
491 | memset(done_key, 0, sizeof(done_key)); | |
492 | ||
493 | ret = la_read_mem(usb, addr, sizeof(done_key), done_key); /* read key from eeprom */ | |
494 | if (ret != SR_OK) | |
495 | return ret; | |
496 | ||
497 | k0 = RL32(done_key); /* 0x641381F6 */ | |
498 | k1 = RL32(done_key + 4); /* 0x00000000 */ | |
499 | ||
500 | sr_dbg("cfg fpga done, k0: %08X, k1: %08X.", k0, k1); | |
501 | ||
502 | ret = la_write_reg(usb, 16, k0); | |
503 | if (ret != SR_OK) | |
504 | return ret; | |
505 | ||
506 | ret = la_write_reg(usb, 17, k1); | |
507 | if (ret != SR_OK) | |
508 | return ret; | |
509 | ||
510 | reg2 = 0; | |
511 | ret = la_read_reg(usb, 2, ®2); | |
512 | ||
513 | sr_dbg("cfg fpga done, reg2: %08X.", reg2); | |
514 | ||
515 | return ret; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Load a bitstream file into memory. Returns a newly allocated array | |
520 | * consisting of a 32-bit length field followed by the bitstream data. | |
521 | */ | |
522 | static unsigned char *load_bitstream(struct sr_context *ctx, | |
523 | const char *name, int *length_p) | |
524 | { | |
525 | struct sr_resource fw; | |
526 | unsigned char *stream, *fw_data; | |
527 | ssize_t length, count; | |
528 | ||
529 | if (sr_resource_open(ctx, &fw, SR_RESOURCE_FIRMWARE, name) != SR_OK) | |
530 | return NULL; | |
531 | ||
532 | if (fw.size <= BITSTREAM_HEADER_SIZE || fw.size > BITSTREAM_MAX_SIZE) { | |
533 | sr_err("Refusing to load bitstream of unreasonable size " | |
534 | "(%" PRIu64 " bytes).", fw.size); | |
535 | sr_resource_close(ctx, &fw); | |
536 | return NULL; | |
537 | } | |
538 | ||
539 | stream = g_try_malloc(fw.size); | |
540 | if (!stream) { | |
541 | sr_err("Failed to allocate bitstream buffer."); | |
542 | sr_resource_close(ctx, &fw); | |
543 | return NULL; | |
544 | } | |
545 | ||
546 | count = sr_resource_read(ctx, &fw, stream, fw.size); | |
547 | sr_resource_close(ctx, &fw); | |
548 | ||
549 | if (count != (ssize_t)fw.size) { | |
550 | sr_err("Failed to read bitstream '%s'.", name); | |
551 | g_free(stream); | |
552 | return NULL; | |
553 | } | |
554 | ||
555 | if (RB32(stream + BITSTREAM_HEADER_SIZE) != XILINX_SYNC_WORD) { | |
556 | sr_err("Invalid bitstream signature."); | |
557 | g_free(stream); | |
558 | return NULL; | |
559 | } | |
560 | ||
561 | length = fw.size - BITSTREAM_HEADER_SIZE + 0x100; | |
562 | fw_data = g_try_malloc(length); | |
563 | if (!fw_data) { | |
564 | sr_err("Failed to allocate bitstream aligned buffer."); | |
565 | return NULL; | |
566 | } | |
567 | ||
568 | memset(fw_data, 0xFF, 0x100); | |
569 | memcpy(fw_data + 0x100, stream + BITSTREAM_HEADER_SIZE, | |
570 | fw.size - BITSTREAM_HEADER_SIZE); | |
571 | g_free(stream); | |
572 | ||
573 | *length_p = length; | |
574 | ||
575 | return fw_data; | |
576 | } | |
577 | ||
f3178f12 | 578 | static int sla5032_is_configured(const struct sr_usb_dev_inst *usb, gboolean *is_configured) |
9e0693f9 UH |
579 | { |
580 | int ret; | |
581 | uint32_t reg2; | |
582 | ||
583 | reg2 = 0; | |
584 | ret = la_read_reg(usb, 2, ®2); | |
585 | if (ret == SR_OK) | |
586 | *is_configured = (reg2 & 0xFFFFFFF1) == 0xA5A5A5A1 ? TRUE : FALSE; | |
587 | ||
588 | return ret; | |
589 | } | |
590 | ||
591 | /* Load a Binary File from the firmware directory, transfer it to the device. */ | |
592 | static int sla5032_send_bitstream(struct sr_context *ctx, | |
593 | const struct sr_usb_dev_inst *usb, const char *name) | |
594 | { | |
595 | unsigned char *stream; | |
596 | int ret, length, i, n, m; | |
597 | uint32_t reg2; | |
598 | ||
599 | if (!ctx || !usb || !name) | |
600 | return SR_ERR_BUG; | |
601 | ||
602 | stream = load_bitstream(ctx, name, &length); | |
603 | if (!stream) | |
604 | return SR_ERR; | |
605 | ||
606 | sr_dbg("Downloading FPGA bitstream '%s'.", name); | |
607 | ||
608 | reg2 = 0; | |
609 | ret = la_read_reg(usb, 2, ®2); | |
610 | sr_dbg("send bitstream, reg2: %08X.", reg2); | |
611 | ||
612 | /* Transfer the entire bitstream in one URB. */ | |
613 | ret = la_write_cmd_buf(usb, CMD_INIT_FW_UPLOAD, 0, 0, NULL); /* init firmware upload */ | |
614 | if (ret != SR_OK) { | |
615 | g_free(stream); | |
616 | return ret; | |
617 | } | |
618 | ||
619 | n = length / FW_CHUNK_SIZE; | |
620 | m = length % FW_CHUNK_SIZE; | |
621 | ||
622 | for (i = 0; i < n; i++) { | |
623 | /* upload firmware chunk */ | |
624 | ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0, | |
625 | FW_CHUNK_SIZE, &stream[i * FW_CHUNK_SIZE]); | |
626 | ||
627 | if (ret != SR_OK) { | |
628 | g_free(stream); | |
629 | return ret; | |
630 | } | |
631 | } | |
632 | ||
633 | if (m != 0) { | |
634 | /* upload firmware last chunk */ | |
635 | ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0, m, | |
636 | &stream[n * FW_CHUNK_SIZE]); | |
637 | ||
638 | if (ret != SR_OK) { | |
639 | g_free(stream); | |
640 | return ret; | |
641 | } | |
642 | } | |
643 | ||
644 | g_free(stream); | |
645 | ||
646 | la_cfg_fpga_done(usb, 4000); | |
647 | ||
648 | sla5032_write_reg14_zero(usb); | |
649 | ||
650 | sr_dbg("FPGA bitstream download of %d bytes done.", length); | |
651 | ||
652 | return SR_OK; | |
653 | } | |
654 | ||
655 | /* Select and transfer FPGA bitstream for the current configuration. */ | |
656 | SR_PRIV int sla5032_apply_fpga_config(const struct sr_dev_inst *sdi) | |
657 | { | |
658 | struct dev_context *devc; | |
659 | struct drv_context *drvc; | |
660 | int ret; | |
661 | gboolean is_configured; | |
662 | ||
663 | devc = sdi->priv; | |
664 | drvc = sdi->driver->context; | |
665 | ||
666 | if (FPGA_NOCONF != devc->active_fpga_config) | |
667 | return SR_OK; /* No change. */ | |
668 | ||
669 | is_configured = FALSE; | |
670 | ret = sla5032_is_configured(sdi->conn, &is_configured); | |
671 | if (ret != SR_OK) | |
672 | return ret; | |
673 | ||
674 | if (is_configured) { | |
675 | devc->active_fpga_config = FPGA_CONF; | |
676 | return ret; | |
677 | } | |
678 | ||
679 | sr_dbg("FPGA not configured, send bitstream."); | |
680 | ret = sla5032_send_bitstream(drvc->sr_ctx, sdi->conn, BITSTREAM_NAME); | |
681 | devc->active_fpga_config = (ret == SR_OK) ? FPGA_CONF : FPGA_NOCONF; | |
682 | ||
683 | return ret; | |
684 | } | |
8da8c826 VV |
685 | |
686 | /* Callback handling data */ | |
687 | static int la_prepare_data(int fd, int revents, void *cb_data) | |
688 | { | |
689 | struct sr_dev_inst *sdi; | |
690 | struct dev_context *devc; | |
691 | struct sr_usb_dev_inst *usb; | |
692 | int i, j, ret, xfer_len; | |
693 | uint8_t *rle_buf, *samples; | |
694 | const uint8_t *p, *q; | |
695 | uint16_t rle_count; | |
696 | int samples_count, rle_samples_count; | |
697 | uint32_t status[3]; | |
698 | struct sr_datafeed_packet packet; | |
699 | struct sr_datafeed_logic logic; | |
700 | uint32_t value; | |
701 | int trigger_offset; | |
702 | ||
703 | enum { | |
704 | RLE_SAMPLE_SIZE = sizeof(uint32_t) + sizeof(uint16_t), | |
705 | RLE_SAMPLES_COUNT = 0x100000, | |
706 | RLE_BUF_SIZE = RLE_SAMPLES_COUNT * RLE_SAMPLE_SIZE, | |
707 | RLE_END_MARKER = 0xFFFF, | |
708 | }; | |
709 | ||
710 | (void)fd; | |
711 | (void)revents; | |
712 | ||
713 | sdi = cb_data; | |
714 | devc = sdi->priv; | |
715 | usb = sdi->conn; | |
716 | ||
717 | memset(status, 0, sizeof(status)); | |
718 | ret = sla5032_get_status(usb, status); | |
719 | if (ret != SR_OK) { | |
720 | sla5032_write_reg14_zero(usb); | |
721 | sr_dev_acquisition_stop(sdi); | |
722 | return G_SOURCE_CONTINUE; | |
723 | } | |
724 | ||
725 | /* data not ready (acquision in progress) */ | |
726 | if (status[1] != 3) | |
727 | return G_SOURCE_CONTINUE; | |
728 | ||
729 | sr_dbg("acquision done, status: %u.", (unsigned int)status[2]); | |
730 | ||
731 | /* data ready (download, decode and send to sigrok) */ | |
732 | ret = sla5032_set_read_back(usb); | |
733 | if (ret != SR_OK) { | |
734 | sla5032_write_reg14_zero(usb); | |
735 | sr_dev_acquisition_stop(sdi); | |
736 | return G_SOURCE_CONTINUE; | |
737 | } | |
738 | ||
739 | rle_buf = g_try_malloc(RLE_BUF_SIZE); | |
740 | if (rle_buf == NULL) { | |
741 | sla5032_write_reg14_zero(usb); | |
742 | sr_dev_acquisition_stop(sdi); | |
743 | return G_SOURCE_CONTINUE; | |
744 | } | |
745 | ||
746 | do { | |
747 | xfer_len = 0; | |
748 | ret = sla5032_read_data_chunk(usb, rle_buf, RLE_BUF_SIZE, &xfer_len); | |
749 | if (ret != SR_OK) { | |
750 | sla5032_write_reg14_zero(usb); | |
751 | g_free(rle_buf); | |
752 | sr_dev_acquisition_stop(sdi); | |
753 | ||
754 | sr_dbg("acquision done, ret: %d.", ret); | |
755 | return G_SOURCE_CONTINUE; | |
756 | } | |
757 | ||
758 | sr_dbg("acquision done, xfer_len: %d.", xfer_len); | |
759 | ||
760 | if (xfer_len == 0) { | |
761 | sla5032_write_reg14_zero(usb); | |
762 | g_free(rle_buf); | |
763 | sr_dev_acquisition_stop(sdi); | |
764 | return G_SOURCE_CONTINUE; | |
765 | } | |
766 | ||
767 | p = rle_buf; | |
768 | samples_count = 0; | |
769 | rle_samples_count = xfer_len / RLE_SAMPLE_SIZE; | |
770 | ||
771 | sr_dbg("acquision done, rle_samples_count: %d.", rle_samples_count); | |
772 | ||
773 | for (i = 0; i < rle_samples_count; i++) { | |
774 | p += sizeof(uint32_t); /* skip sample value */ | |
775 | ||
776 | rle_count = RL16(p); /* read RLE counter */ | |
777 | p += sizeof(uint16_t); | |
778 | if (rle_count == RLE_END_MARKER) { | |
779 | rle_samples_count = i; | |
780 | break; | |
781 | } | |
782 | samples_count += rle_count + 1; | |
783 | } | |
784 | sr_dbg("acquision done, samples_count: %d.", samples_count); | |
785 | ||
786 | if (samples_count == 0) { | |
787 | sr_dbg("acquision done, no samples."); | |
788 | sla5032_write_reg14_zero(usb); | |
789 | g_free(rle_buf); | |
790 | sr_dev_acquisition_stop(sdi); | |
791 | return G_SOURCE_CONTINUE; | |
792 | } | |
793 | ||
794 | /* Decode RLE */ | |
795 | samples = g_try_malloc(samples_count * sizeof(uint32_t)); | |
796 | if (!samples) { | |
797 | sr_dbg("memory allocation error."); | |
798 | sla5032_write_reg14_zero(usb); | |
799 | g_free(rle_buf); | |
800 | sr_dev_acquisition_stop(sdi); | |
801 | return G_SOURCE_CONTINUE; | |
802 | } | |
803 | ||
804 | p = rle_buf; | |
805 | q = samples; | |
806 | for (i = 0; i < rle_samples_count; i++) { | |
807 | value = RL32(p); | |
808 | p += sizeof(uint32_t); /* read sample value */ | |
809 | ||
810 | rle_count = RL16(p); /* read RLE counter */ | |
811 | p += sizeof(uint16_t); | |
812 | ||
813 | if (rle_count == RLE_END_MARKER) { | |
814 | sr_dbg("RLE end marker found."); | |
815 | break; | |
816 | } | |
817 | ||
818 | for (j = 0; j <= rle_count; j++) { | |
819 | WL32(q, value); | |
820 | q += sizeof(uint32_t); | |
821 | } | |
822 | } | |
823 | ||
824 | if (devc->trigger_fired) { | |
825 | /* Send the incoming transfer to the session bus. */ | |
826 | packet.type = SR_DF_LOGIC; | |
827 | packet.payload = &logic; | |
828 | ||
829 | logic.length = samples_count * sizeof(uint32_t); | |
830 | logic.unitsize = sizeof(uint32_t); | |
831 | logic.data = samples; | |
832 | sr_session_send(sdi, &packet); | |
833 | } else { | |
834 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
835 | samples, samples_count * sizeof(uint32_t), NULL); | |
836 | if (trigger_offset > -1) { | |
837 | packet.type = SR_DF_LOGIC; | |
838 | packet.payload = &logic; | |
839 | int num_samples = samples_count - trigger_offset; | |
840 | ||
841 | logic.length = num_samples * sizeof(uint32_t); | |
842 | logic.unitsize = sizeof(uint32_t); | |
843 | logic.data = samples + trigger_offset * sizeof(uint32_t); | |
844 | sr_session_send(sdi, &packet); | |
845 | ||
846 | devc->trigger_fired = TRUE; | |
847 | } | |
848 | } | |
849 | ||
850 | g_free(samples); | |
851 | } while (rle_samples_count == RLE_SAMPLES_COUNT); | |
852 | ||
853 | sr_dbg("acquision stop, rle_samples_count < RLE_SAMPLES_COUNT."); | |
854 | ||
855 | sla5032_write_reg14_zero(usb); | |
856 | ||
857 | sr_dev_acquisition_stop(sdi); /* if all data transfered */ | |
858 | ||
859 | g_free(rle_buf); | |
860 | ||
861 | if (devc->stl) { | |
862 | soft_trigger_logic_free(devc->stl); | |
863 | devc->stl = NULL; | |
864 | } | |
865 | ||
866 | return G_SOURCE_CONTINUE; | |
867 | } | |
868 | ||
98ed645e | 869 | SR_PRIV int sla5032_start_acquisition(const struct sr_dev_inst *sdi) |
8da8c826 VV |
870 | { |
871 | struct dev_context *devc; | |
872 | struct sr_usb_dev_inst *usb; | |
f3178f12 | 873 | struct sr_trigger *trigger; |
8da8c826 VV |
874 | int ret; |
875 | enum { poll_interval_ms = 100 }; | |
876 | uint64_t pre, post; | |
877 | ||
878 | devc = sdi->priv; | |
879 | usb = sdi->conn; | |
880 | ||
881 | if (devc->state != STATE_IDLE) { | |
882 | sr_err("Not in idle state, cannot start acquisition."); | |
883 | return SR_ERR; | |
884 | } | |
885 | ||
886 | pre = (devc->limit_samples * devc->capture_ratio) / 100; | |
887 | post = devc->limit_samples - pre; | |
888 | ||
889 | if ((trigger = sr_session_trigger_get(sdi->session))) { | |
890 | devc->stl = soft_trigger_logic_new(sdi, trigger, pre); | |
891 | if (!devc->stl) { | |
892 | sr_err("stl alloc error."); | |
893 | return SR_ERR_MALLOC; | |
894 | } | |
895 | devc->trigger_fired = FALSE; | |
896 | } | |
897 | else | |
898 | devc->trigger_fired = TRUE; | |
899 | ||
900 | sr_dbg("start acquision, smp lim: %" PRIu64 ", cap ratio: %" PRIu64 | |
901 | ".", devc->limit_samples, devc->capture_ratio); | |
902 | ||
903 | sr_dbg("start acquision, pre: %" PRIu64 ", post: %" PRIu64 ".", pre, post); | |
904 | pre /= 256; | |
262cb996 | 905 | pre = MAX(pre, 2); |
8da8c826 VV |
906 | pre--; |
907 | ||
908 | post /= 256; | |
262cb996 | 909 | post = MAX(post, 2); |
8da8c826 VV |
910 | post--; |
911 | ||
912 | sr_dbg("start acquision, pre: %" PRIx64 ", post: %" PRIx64 ".", pre, post); | |
913 | ||
914 | /* (x + 1) * 256 (samples) pre, post */ | |
915 | ret = sla5032_set_depth(usb, pre, post); | |
916 | if (ret != SR_OK) | |
917 | return ret; | |
918 | ||
919 | ret = sla5032_set_triggers(usb, devc->trigger_values, devc->trigger_edge_mask, devc->trigger_mask); | |
920 | if (ret != SR_OK) | |
921 | return ret; | |
922 | ||
923 | ret = sla5032_set_samplerate(usb, devc->samplerate); | |
924 | if (ret != SR_OK) | |
925 | return ret; | |
926 | ||
927 | /* TODO: make PWM generator as separate configurable subdevice */ | |
928 | enum { | |
929 | pwm1_hi = 20000000 - 1, | |
930 | pwm1_lo = 200000 - 1, | |
931 | pwm2_hi = 15 - 1, | |
932 | pwm2_lo = 5 - 1, | |
933 | }; | |
934 | ||
935 | ret = sla5032_set_pwm1(usb, pwm1_hi, pwm1_lo); | |
936 | if (ret != SR_OK) | |
937 | return ret; | |
938 | ||
939 | ret = sla5032_set_pwm2(usb, pwm2_hi, pwm2_lo); | |
940 | if (ret != SR_OK) | |
941 | return ret; | |
942 | ||
943 | ret = sla5032_start_sample(usb); | |
944 | if (ret != SR_OK) | |
945 | return ret; | |
946 | ||
947 | sr_session_source_add(sdi->session, -1, 0, poll_interval_ms, | |
948 | la_prepare_data, (struct sr_dev_inst *)sdi); | |
949 | ||
950 | std_session_send_df_header(sdi); | |
951 | ||
952 | return ret; | |
953 | } |