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aeaad0b0 DE |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H | |
21 | #define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H | |
22 | ||
5874e88d DE |
23 | #define LOG_PREFIX "sysclk-lwla" |
24 | ||
5874e88d | 25 | #include <stdint.h> |
93ed0241 | 26 | #include <libusb.h> |
5874e88d | 27 | #include <glib.h> |
c1aae900 | 28 | #include <libsigrok/libsigrok.h> |
be64f90b | 29 | #include <libsigrok-internal.h> |
aeaad0b0 | 30 | |
5874e88d | 31 | #define VENDOR_NAME "SysClk" |
5874e88d | 32 | |
be64f90b DE |
33 | /* Maximum configurable sample count limit. |
34 | * Due to compression, there is no meaningful hardware limit the driver | |
35 | * could report. So this value is less than 2^64-1 for no reason other | |
36 | * than to safeguard against integer overflows. | |
5874e88d | 37 | */ |
be64f90b | 38 | #define MAX_LIMIT_SAMPLES (UINT64_C(1000) * 1000 * 1000 * 1000) |
5874e88d | 39 | |
be64f90b DE |
40 | /* Maximum configurable acquisition time limit. |
41 | * Due to compression, there is no hardware limit that would be meaningful | |
42 | * in practice. However, the LWLA1016 reports the elapsed time as a 32-bit | |
43 | * value, so keep this below 2^32. | |
5874e88d | 44 | */ |
be64f90b | 45 | #define MAX_LIMIT_MSEC (1000 * 1000 * 1000) |
5874e88d | 46 | |
be64f90b | 47 | struct acquisition_state; |
5874e88d | 48 | |
ca314e06 | 49 | /* USB vendor and product IDs. */ |
be64f90b DE |
50 | enum { |
51 | USB_VID_SYSCLK = 0x2961, | |
52 | USB_PID_LWLA1016 = 0x6688, | |
53 | USB_PID_LWLA1034 = 0x6689, | |
54 | }; | |
29d58767 | 55 | |
ca314e06 | 56 | /* USB device characteristics. */ |
be64f90b DE |
57 | enum { |
58 | USB_CONFIG = 1, | |
59 | USB_INTERFACE = 0, | |
e35a4592 | 60 | USB_TIMEOUT_MS = 1000, |
6358f0a9 DE |
61 | }; |
62 | ||
ca314e06 | 63 | /** USB device end points. */ |
93ed0241 DE |
64 | enum usb_endpoint { |
65 | EP_COMMAND = 2, | |
66 | EP_CONFIG = 4, | |
67 | EP_REPLY = 6 | LIBUSB_ENDPOINT_IN | |
68 | }; | |
69 | ||
ca314e06 | 70 | /** LWLA1034 clock sources. */ |
5874e88d | 71 | enum clock_source { |
be64f90b | 72 | CLOCK_INTERNAL = 0, |
6358f0a9 | 73 | CLOCK_EXT_CLK, |
5874e88d DE |
74 | }; |
75 | ||
ca314e06 | 76 | /** LWLA1034 trigger sources. */ |
e6e54bd2 DE |
77 | enum trigger_source { |
78 | TRIGGER_CHANNELS = 0, | |
79 | TRIGGER_EXT_TRG, | |
80 | }; | |
81 | ||
ca314e06 | 82 | /** Edge choices for the LWLA1034 external clock and trigger inputs. */ |
6358f0a9 DE |
83 | enum signal_edge { |
84 | EDGE_POSITIVE = 0, | |
85 | EDGE_NEGATIVE, | |
e6e54bd2 DE |
86 | }; |
87 | ||
be64f90b DE |
88 | /* Common indicator for no or unknown FPGA config. */ |
89 | enum { | |
90 | FPGA_NOCONF = -1, | |
91 | }; | |
92 | ||
ca314e06 | 93 | /** Acquisition protocol states. */ |
be64f90b DE |
94 | enum protocol_state { |
95 | /* idle states */ | |
5874e88d | 96 | STATE_IDLE = 0, |
5874e88d | 97 | STATE_STATUS_WAIT, |
be64f90b DE |
98 | /* device command states */ |
99 | STATE_START_CAPTURE, | |
5874e88d | 100 | STATE_STOP_CAPTURE, |
5874e88d | 101 | STATE_READ_PREPARE, |
be64f90b DE |
102 | STATE_READ_FINISH, |
103 | /* command followed by response */ | |
104 | STATE_EXPECT_RESPONSE = 1 << 3, | |
105 | STATE_STATUS_REQUEST = STATE_EXPECT_RESPONSE, | |
106 | STATE_LENGTH_REQUEST, | |
5874e88d | 107 | STATE_READ_REQUEST, |
5874e88d DE |
108 | }; |
109 | ||
aeaad0b0 | 110 | struct dev_context { |
be64f90b | 111 | uint64_t samplerate; /* requested samplerate */ |
be64f90b DE |
112 | uint64_t limit_msec; /* requested capture duration in ms */ |
113 | uint64_t limit_samples; /* requested capture length in samples */ | |
5874e88d | 114 | |
407b6e2c | 115 | uint64_t channel_mask; /* bit mask of enabled channels */ |
be64f90b DE |
116 | uint64_t trigger_mask; /* trigger enable mask */ |
117 | uint64_t trigger_edge_mask; /* trigger type mask */ | |
118 | uint64_t trigger_values; /* trigger level/slope bits */ | |
aeaad0b0 | 119 | |
be64f90b DE |
120 | const struct model_info *model; /* device model descriptor */ |
121 | struct acquisition_state *acquisition; /* running capture state */ | |
122 | int active_fpga_config; /* FPGA configuration index */ | |
78648577 | 123 | gboolean short_transfer_quirk; /* 64 bytes response limit */ |
aeaad0b0 | 124 | |
be64f90b DE |
125 | enum protocol_state state; /* async protocol state */ |
126 | gboolean cancel_requested; /* stop after current transfer */ | |
127 | gboolean transfer_error; /* error during device communication */ | |
aeaad0b0 | 128 | |
be64f90b DE |
129 | gboolean cfg_rle; /* RLE compression setting */ |
130 | enum clock_source cfg_clock_source; /* clock source setting */ | |
131 | enum signal_edge cfg_clock_edge; /* ext clock edge setting */ | |
132 | enum trigger_source cfg_trigger_source; /* trigger source setting */ | |
133 | enum signal_edge cfg_trigger_slope; /* ext trigger slope setting */ | |
be64f90b | 134 | }; |
6358f0a9 | 135 | |
ca314e06 | 136 | /** LWLA model descriptor. */ |
be64f90b DE |
137 | struct model_info { |
138 | char name[12]; | |
139 | int num_channels; | |
5874e88d | 140 | |
be64f90b DE |
141 | unsigned int num_devopts; |
142 | uint32_t devopts[8]; | |
e6e54bd2 | 143 | |
be64f90b DE |
144 | unsigned int num_samplerates; |
145 | uint64_t samplerates[20]; | |
c81069b3 | 146 | |
be64f90b DE |
147 | int (*apply_fpga_config)(const struct sr_dev_inst *sdi); |
148 | int (*device_init_check)(const struct sr_dev_inst *sdi); | |
149 | int (*setup_acquisition)(const struct sr_dev_inst *sdi); | |
5874e88d | 150 | |
be64f90b DE |
151 | int (*prepare_request)(const struct sr_dev_inst *sdi); |
152 | int (*handle_response)(const struct sr_dev_inst *sdi); | |
aeaad0b0 DE |
153 | }; |
154 | ||
ef7df53d DE |
155 | extern SR_PRIV const struct model_info lwla1016_info; |
156 | extern SR_PRIV const struct model_info lwla1034_info; | |
5874e88d | 157 | |
5874e88d | 158 | SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi); |
aeaad0b0 | 159 | |
db24496a | 160 | #endif |