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1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <config.h> | |
21 | #include "lwla.h" | |
22 | #include "protocol.h" | |
23 | ||
24 | /* Number of logic channels. | |
25 | */ | |
26 | #define NUM_CHANNELS 34 | |
27 | ||
28 | /* Bit mask covering all logic channels. | |
29 | */ | |
30 | #define ALL_CHANNELS_MASK ((UINT64_C(1) << NUM_CHANNELS) - 1) | |
31 | ||
32 | /* Unit size for the sigrok logic datafeed. | |
33 | */ | |
34 | #define UNIT_SIZE ((NUM_CHANNELS + 7) / 8) | |
35 | ||
36 | /* Size of the acquisition buffer in device memory units. | |
37 | */ | |
38 | #define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */ | |
39 | ||
40 | /* Capture memory read start address. | |
41 | */ | |
42 | #define READ_START_ADDR 4 | |
43 | ||
44 | /* Number of device memory units (36 bit) to read at a time. Slices of 8 | |
45 | * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk | |
46 | * length should be a multiple of 8 to ensure alignment to slice boundaries. | |
47 | * | |
48 | * Experimentation has shown that reading chunks larger than about 1024 bytes | |
49 | * is unreliable. The threshold seems to relate to the buffer size on the FX2 | |
50 | * USB chip: The configured endpoint buffer size is 512, and with double or | |
51 | * triple buffering enabled a multiple of 512 bytes can be kept in fly. | |
52 | * | |
53 | * The vendor software limits reads to 120 words (15 slices, 540 bytes) at | |
54 | * a time. So far, it appears safe to increase this to 224 words (28 slices, | |
55 | * 1008 bytes), thus making the most of two 512 byte buffers. | |
56 | */ | |
57 | #define READ_CHUNK_LEN36 (28 * 8) | |
58 | ||
59 | /* Bit mask for the RLE repeat-count-follows flag. */ | |
60 | #define RLE_FLAG_LEN_FOLLOWS (UINT64_C(1) << 35) | |
61 | ||
62 | /** LWLA1034 register addresses. | |
63 | */ | |
64 | enum reg_addr { | |
65 | REG_MEM_CTRL = 0x1074, /* capture buffer control */ | |
66 | REG_MEM_FILL = 0x1078, /* capture buffer fill level */ | |
67 | REG_MEM_START = 0x107C, /* capture buffer start address */ | |
68 | ||
69 | REG_CLK_BOOST = 0x1094, /* logic clock boost flag */ | |
70 | ||
71 | REG_LONG_STROBE = 0x10B0, /* long register read/write strobe */ | |
72 | REG_LONG_ADDR = 0x10B4, /* long register address */ | |
73 | REG_LONG_LOW = 0x10B8, /* long register low word */ | |
74 | REG_LONG_HIGH = 0x10BC, /* long register high word */ | |
75 | }; | |
76 | ||
77 | /** Flag bits for REG_MEM_CTRL. | |
78 | */ | |
79 | enum mem_ctrl_flag { | |
80 | MEM_CTRL_WRITE = 1 << 0, /* "wr1rd0" bit */ | |
81 | MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */ | |
82 | }; | |
83 | ||
84 | /* LWLA1034 long register addresses. | |
85 | */ | |
86 | enum long_reg_addr { | |
87 | LREG_CHAN_MASK = 0, /* channel enable mask */ | |
88 | LREG_DIV_COUNT = 1, /* clock divider max count */ | |
89 | LREG_TRG_VALUE = 2, /* trigger level/slope bits */ | |
90 | LREG_TRG_TYPE = 3, /* trigger type bits (level or edge) */ | |
91 | LREG_TRG_ENABLE = 4, /* trigger enable mask */ | |
92 | LREG_MEM_FILL = 5, /* capture memory fill level or limit */ | |
93 | ||
94 | LREG_DURATION = 7, /* elapsed time in ms (0.8 ms at 125 MS/s) */ | |
95 | LREG_CHAN_STATE = 8, /* current logic levels at the inputs */ | |
96 | LREG_STATUS = 9, /* capture status flags */ | |
97 | ||
98 | LREG_CAP_CTRL = 10, /* capture control bits */ | |
99 | LREG_TEST_ID = 100, /* constant test ID */ | |
100 | }; | |
101 | ||
102 | /** Flag bits for LREG_CAP_CTRL. | |
103 | */ | |
104 | enum cap_ctrl_flag { | |
105 | CAP_CTRL_TRG_EN = 1 << 0, /* "trg_en" bit */ | |
106 | CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */ | |
107 | CAP_CTRL_FLUSH_FIFO = 1 << 4, /* "flush_fifo" bit */ | |
108 | CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */ | |
109 | CAP_CTRL_CLR_COUNTER = 1 << 6, /* "clr_cntr0" bit */ | |
110 | }; | |
111 | ||
112 | /* Available FPGA configurations. | |
113 | */ | |
114 | enum fpga_config { | |
115 | FPGA_OFF = 0, /* FPGA shutdown config */ | |
116 | FPGA_INT, /* internal clock config */ | |
117 | FPGA_EXTPOS, /* external clock, rising edge config */ | |
118 | FPGA_EXTNEG, /* external clock, falling edge config */ | |
119 | }; | |
120 | ||
121 | /* FPGA bitstream resource filenames. | |
122 | */ | |
123 | static const char bitstream_map[][32] = { | |
124 | [FPGA_OFF] = "sysclk-lwla1034-off.rbf", | |
125 | [FPGA_INT] = "sysclk-lwla1034-int.rbf", | |
126 | [FPGA_EXTPOS] = "sysclk-lwla1034-extpos.rbf", | |
127 | [FPGA_EXTNEG] = "sysclk-lwla1034-extneg.rbf", | |
128 | }; | |
129 | ||
130 | /* Read 64-bit long register. | |
131 | */ | |
132 | static int read_long_reg(const struct sr_usb_dev_inst *usb, | |
133 | uint32_t addr, uint64_t *value) | |
134 | { | |
135 | uint32_t low, high, dummy; | |
136 | int ret; | |
137 | ||
138 | ret = lwla_write_reg(usb, REG_LONG_ADDR, addr); | |
139 | if (ret != SR_OK) | |
140 | return ret; | |
141 | ||
142 | ret = lwla_read_reg(usb, REG_LONG_STROBE, &dummy); | |
143 | if (ret != SR_OK) | |
144 | return ret; | |
145 | ||
146 | ret = lwla_read_reg(usb, REG_LONG_HIGH, &high); | |
147 | if (ret != SR_OK) | |
148 | return ret; | |
149 | ||
150 | ret = lwla_read_reg(usb, REG_LONG_LOW, &low); | |
151 | if (ret != SR_OK) | |
152 | return ret; | |
153 | ||
154 | *value = ((uint64_t)high << 32) | low; | |
155 | ||
156 | return SR_OK; | |
157 | } | |
158 | ||
159 | /* Queue access sequence for a long register write. | |
160 | */ | |
161 | static void queue_long_regval(struct acquisition_state *acq, | |
162 | uint32_t addr, uint64_t value) | |
163 | { | |
164 | lwla_queue_regval(acq, REG_LONG_ADDR, addr); | |
165 | lwla_queue_regval(acq, REG_LONG_LOW, value & 0xFFFFFFFF); | |
166 | lwla_queue_regval(acq, REG_LONG_HIGH, value >> 32); | |
167 | lwla_queue_regval(acq, REG_LONG_STROBE, 0); | |
168 | } | |
169 | ||
170 | /* Helper to fill in the long register bulk write command. | |
171 | */ | |
172 | static inline void bulk_long_set(struct acquisition_state *acq, | |
7ed80817 | 173 | unsigned int idx, uint64_t value) |
be64f90b DE |
174 | { |
175 | acq->xfer_buf_out[4 * idx + 3] = LWLA_WORD_0(value); | |
176 | acq->xfer_buf_out[4 * idx + 4] = LWLA_WORD_1(value); | |
177 | acq->xfer_buf_out[4 * idx + 5] = LWLA_WORD_2(value); | |
178 | acq->xfer_buf_out[4 * idx + 6] = LWLA_WORD_3(value); | |
179 | } | |
180 | ||
181 | /* Helper for dissecting the response to a long register bulk read. | |
182 | */ | |
183 | static inline uint64_t bulk_long_get(const struct acquisition_state *acq, | |
7ed80817 | 184 | unsigned int idx) |
be64f90b DE |
185 | { |
186 | uint64_t low, high; | |
187 | ||
188 | low = LWLA_TO_UINT32(acq->xfer_buf_in[2 * idx]); | |
189 | high = LWLA_TO_UINT32(acq->xfer_buf_in[2 * idx + 1]); | |
190 | ||
191 | return (high << 32) | low; | |
192 | } | |
193 | ||
194 | /* Demangle and decompress incoming sample data from the transfer buffer. | |
195 | * The data chunk is taken from the acquisition state, and is expected to | |
196 | * contain a multiple of 8 packed 36-bit words. | |
197 | */ | |
198 | static void read_response(struct acquisition_state *acq) | |
199 | { | |
200 | uint64_t sample, high_nibbles, word; | |
201 | uint32_t *slice; | |
202 | uint8_t *out_p; | |
7ed80817 DE |
203 | unsigned int words_left; |
204 | unsigned int max_samples, run_samples; | |
205 | unsigned int wi, ri, si; | |
be64f90b DE |
206 | |
207 | /* Number of 36-bit words remaining in the transfer buffer. */ | |
208 | words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop) | |
209 | - acq->mem_addr_done; | |
210 | ||
211 | for (wi = 0;; wi++) { | |
212 | /* Calculate number of samples to write into packet. */ | |
213 | max_samples = MIN(acq->samples_max - acq->samples_done, | |
214 | PACKET_SIZE / UNIT_SIZE - acq->out_index); | |
215 | run_samples = MIN(max_samples, acq->run_len); | |
216 | ||
217 | /* Expand run-length samples into session packet. */ | |
218 | sample = acq->sample; | |
219 | out_p = &acq->out_packet[acq->out_index * UNIT_SIZE]; | |
220 | ||
221 | for (ri = 0; ri < run_samples; ri++) { | |
222 | out_p[0] = sample & 0xFF; | |
223 | out_p[1] = (sample >> 8) & 0xFF; | |
224 | out_p[2] = (sample >> 16) & 0xFF; | |
225 | out_p[3] = (sample >> 24) & 0xFF; | |
226 | out_p[4] = (sample >> 32) & 0xFF; | |
227 | out_p += UNIT_SIZE; | |
228 | } | |
229 | acq->run_len -= run_samples; | |
230 | acq->out_index += run_samples; | |
231 | acq->samples_done += run_samples; | |
232 | ||
233 | if (run_samples == max_samples) | |
234 | break; /* packet full or sample limit reached */ | |
235 | if (wi >= words_left) | |
236 | break; /* done with current transfer */ | |
237 | ||
238 | /* Get the current slice of 8 packed 36-bit words. */ | |
239 | slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9]; | |
240 | si = (acq->in_index + wi) % 8; /* word index within slice */ | |
241 | ||
242 | /* Extract the next 36-bit word. */ | |
243 | high_nibbles = LWLA_TO_UINT32(slice[8]); | |
244 | word = LWLA_TO_UINT32(slice[si]); | |
245 | word |= (high_nibbles << (4 * si + 4)) & (UINT64_C(0xF) << 32); | |
246 | ||
247 | if (acq->rle == RLE_STATE_DATA) { | |
248 | acq->sample = word & ALL_CHANNELS_MASK; | |
249 | acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1; | |
250 | acq->rle = ((word & RLE_FLAG_LEN_FOLLOWS) != 0) | |
251 | ? RLE_STATE_LEN : RLE_STATE_DATA; | |
252 | } else { | |
253 | acq->run_len += word << 1; | |
254 | acq->rle = RLE_STATE_DATA; | |
255 | } | |
256 | } | |
257 | acq->in_index += wi; | |
258 | acq->mem_addr_done += wi; | |
259 | } | |
260 | ||
261 | /* Select and transfer FPGA bitstream for the current configuration. | |
262 | */ | |
263 | static int apply_fpga_config(const struct sr_dev_inst *sdi) | |
264 | { | |
265 | struct dev_context *devc; | |
266 | struct drv_context *drvc; | |
267 | int config; | |
268 | int ret; | |
269 | ||
270 | devc = sdi->priv; | |
271 | drvc = sdi->driver->context; | |
272 | ||
273 | if (sdi->status == SR_ST_INACTIVE) | |
274 | config = FPGA_OFF; | |
275 | else if (devc->cfg_clock_source == CLOCK_INTERNAL) | |
276 | config = FPGA_INT; | |
277 | else if (devc->cfg_clock_edge == EDGE_POSITIVE) | |
278 | config = FPGA_EXTPOS; | |
279 | else | |
280 | config = FPGA_EXTNEG; | |
281 | ||
282 | if (config == devc->active_fpga_config) | |
283 | return SR_OK; /* no change */ | |
284 | ||
285 | ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn, | |
286 | bitstream_map[config]); | |
287 | devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF; | |
288 | ||
289 | return ret; | |
290 | } | |
291 | ||
292 | /* Perform initialization self test. | |
293 | */ | |
294 | static int device_init_check(const struct sr_dev_inst *sdi) | |
295 | { | |
296 | uint64_t value; | |
297 | int ret; | |
298 | ||
299 | ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value); | |
300 | if (ret != SR_OK) | |
301 | return ret; | |
302 | ||
303 | /* Ignore the value returned by the first read. */ | |
304 | ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value); | |
305 | if (ret != SR_OK) | |
306 | return ret; | |
307 | ||
308 | if (value != UINT64_C(0x1234567887654321)) { | |
309 | sr_err("Received invalid test word 0x%016" PRIX64 ".", value); | |
310 | return SR_ERR; | |
311 | } | |
312 | return SR_OK; | |
313 | } | |
314 | ||
315 | /* Set up the device in preparation for an acquisition session. | |
316 | */ | |
317 | static int setup_acquisition(const struct sr_dev_inst *sdi) | |
318 | { | |
319 | uint64_t divider_count; | |
320 | uint64_t trigger_mask; | |
321 | struct dev_context *devc; | |
322 | struct sr_usb_dev_inst *usb; | |
323 | struct acquisition_state *acq; | |
324 | int ret; | |
325 | ||
326 | devc = sdi->priv; | |
327 | usb = sdi->conn; | |
328 | acq = devc->acquisition; | |
329 | ||
330 | acq->reg_seq_pos = 0; | |
331 | acq->reg_seq_len = 0; | |
332 | ||
333 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX); | |
334 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE); | |
335 | ||
336 | queue_long_regval(acq, LREG_CAP_CTRL, | |
337 | CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO | | |
338 | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER); | |
339 | ||
340 | lwla_queue_regval(acq, REG_CLK_BOOST, acq->clock_boost); | |
341 | ||
342 | ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len); | |
343 | acq->reg_seq_len = 0; | |
344 | ||
345 | if (ret != SR_OK) | |
346 | return ret; | |
347 | ||
348 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_LREGS); | |
349 | acq->xfer_buf_out[1] = LWLA_WORD(0); | |
350 | acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1); | |
351 | ||
352 | bulk_long_set(acq, LREG_CHAN_MASK, devc->channel_mask); | |
353 | ||
354 | if (devc->samplerate > 0 && devc->samplerate <= SR_MHZ(100) | |
355 | && !acq->clock_boost) | |
356 | divider_count = SR_MHZ(100) / devc->samplerate - 1; | |
357 | else | |
358 | divider_count = 0; | |
359 | ||
360 | bulk_long_set(acq, LREG_DIV_COUNT, divider_count); | |
361 | bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values); | |
362 | bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask); | |
363 | ||
364 | trigger_mask = devc->trigger_mask; | |
365 | ||
366 | /* Set bits to select external TRG input edge. */ | |
367 | if (devc->cfg_trigger_source == TRIGGER_EXT_TRG) | |
368 | switch (devc->cfg_trigger_slope) { | |
369 | case EDGE_POSITIVE: | |
370 | trigger_mask |= UINT64_C(1) << 35; | |
371 | break; | |
372 | case EDGE_NEGATIVE: | |
373 | trigger_mask |= UINT64_C(1) << 34; | |
374 | break; | |
375 | } | |
376 | ||
377 | bulk_long_set(acq, LREG_TRG_ENABLE, trigger_mask); | |
378 | ||
379 | /* Set the capture memory full threshold. This is slightly less | |
380 | * than the actual maximum, most likely in order to compensate for | |
381 | * pipeline latency. | |
382 | */ | |
383 | bulk_long_set(acq, LREG_MEM_FILL, MEMORY_DEPTH - 16); | |
384 | ||
385 | /* Fill remaining words with zeroes. */ | |
386 | bulk_long_set(acq, 6, 0); | |
387 | bulk_long_set(acq, LREG_DURATION, 0); | |
388 | bulk_long_set(acq, LREG_CHAN_STATE, 0); | |
389 | bulk_long_set(acq, LREG_STATUS, 0); | |
390 | ||
391 | return lwla_send_command(sdi->conn, acq->xfer_buf_out, | |
392 | 3 + (LREG_STATUS + 1) * 4); | |
393 | } | |
394 | ||
395 | static int prepare_request(const struct sr_dev_inst *sdi) | |
396 | { | |
397 | struct dev_context *devc; | |
398 | struct acquisition_state *acq; | |
7ed80817 | 399 | unsigned int count; |
be64f90b DE |
400 | |
401 | devc = sdi->priv; | |
402 | acq = devc->acquisition; | |
403 | ||
404 | acq->xfer_out->length = 0; | |
405 | acq->reg_seq_pos = 0; | |
406 | acq->reg_seq_len = 0; | |
407 | ||
408 | switch (devc->state) { | |
409 | case STATE_START_CAPTURE: | |
410 | queue_long_regval(acq, LREG_CAP_CTRL, CAP_CTRL_TRG_EN); | |
411 | break; | |
412 | case STATE_STOP_CAPTURE: | |
413 | queue_long_regval(acq, LREG_CAP_CTRL, 0); | |
414 | lwla_queue_regval(acq, REG_CLK_BOOST, 0); | |
415 | break; | |
416 | case STATE_READ_PREPARE: | |
417 | lwla_queue_regval(acq, REG_CLK_BOOST, 1); | |
418 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX); | |
419 | lwla_queue_regval(acq, REG_MEM_START, READ_START_ADDR); | |
420 | break; | |
421 | case STATE_READ_FINISH: | |
422 | lwla_queue_regval(acq, REG_CLK_BOOST, 0); | |
423 | break; | |
424 | case STATE_STATUS_REQUEST: | |
425 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_LREGS); | |
426 | acq->xfer_buf_out[1] = LWLA_WORD(0); | |
427 | acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1); | |
428 | acq->xfer_out->length = 3 * sizeof(acq->xfer_buf_out[0]); | |
429 | break; | |
430 | case STATE_LENGTH_REQUEST: | |
431 | lwla_queue_regval(acq, REG_MEM_FILL, 0); | |
432 | break; | |
433 | case STATE_READ_REQUEST: | |
434 | /* Always read a multiple of 8 device words. */ | |
435 | count = MIN(READ_CHUNK_LEN36, acq->mem_addr_stop | |
436 | - acq->mem_addr_next + 7) / 8 * 8; | |
437 | ||
438 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36); | |
439 | acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next); | |
440 | acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next); | |
441 | acq->xfer_buf_out[3] = LWLA_WORD_0(count); | |
442 | acq->xfer_buf_out[4] = LWLA_WORD_1(count); | |
443 | acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]); | |
444 | ||
445 | acq->mem_addr_next += count; | |
446 | break; | |
447 | default: | |
448 | sr_err("BUG: unhandled request state %d.", devc->state); | |
449 | return SR_ERR_BUG; | |
450 | } | |
451 | ||
452 | return SR_OK; | |
453 | } | |
454 | ||
455 | static int handle_response(const struct sr_dev_inst *sdi) | |
456 | { | |
457 | struct dev_context *devc; | |
458 | struct acquisition_state *acq; | |
459 | int expect_len; | |
460 | ||
461 | devc = sdi->priv; | |
462 | acq = devc->acquisition; | |
463 | ||
464 | switch (devc->state) { | |
465 | case STATE_STATUS_REQUEST: | |
466 | if (acq->xfer_in->actual_length != (LREG_STATUS + 1) * 8) { | |
467 | sr_err("Received size %d doesn't match expected size %d.", | |
468 | acq->xfer_in->actual_length, (LREG_STATUS + 1) * 8); | |
469 | return SR_ERR; | |
470 | } | |
471 | acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF; | |
472 | acq->duration_now = bulk_long_get(acq, LREG_DURATION); | |
473 | /* Shift left by one so the bit positions match the LWLA1016. */ | |
474 | acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1; | |
475 | /* | |
476 | * It seems that the 125 MS/s mode is implemented simply by | |
477 | * running the FPGA logic at a 25% higher clock rate. As a | |
478 | * result, the millisecond counter for the capture duration | |
479 | * is also off by 25%, and thus needs to be corrected here. | |
480 | */ | |
481 | if (acq->clock_boost) | |
482 | acq->duration_now = acq->duration_now * 4 / 5; | |
483 | break; | |
484 | case STATE_LENGTH_REQUEST: | |
485 | acq->mem_addr_next = READ_START_ADDR; | |
486 | acq->mem_addr_stop = acq->reg_sequence[0].val; | |
487 | break; | |
488 | case STATE_READ_REQUEST: | |
489 | /* Expect a multiple of 8 36-bit words packed into 9 32-bit | |
490 | * words. */ | |
491 | expect_len = (acq->mem_addr_next - acq->mem_addr_done | |
492 | + acq->in_index + 7) / 8 * 9 * sizeof(acq->xfer_buf_in[0]); | |
493 | ||
494 | if (acq->xfer_in->actual_length != expect_len) { | |
495 | sr_err("Received size %d does not match expected size %d.", | |
496 | acq->xfer_in->actual_length, expect_len); | |
497 | devc->transfer_error = TRUE; | |
498 | return SR_ERR; | |
499 | } | |
500 | read_response(acq); | |
501 | break; | |
502 | default: | |
503 | sr_err("BUG: unhandled response state %d.", devc->state); | |
504 | return SR_ERR_BUG; | |
505 | } | |
506 | ||
507 | return SR_OK; | |
508 | } | |
509 | ||
510 | /** Model descriptor for the LWLA1034. | |
511 | */ | |
512 | SR_PRIV const struct model_info lwla1034_info = { | |
513 | .name = "LWLA1034", | |
514 | .num_channels = NUM_CHANNELS, | |
515 | ||
516 | .num_devopts = 8, | |
517 | .devopts = { | |
518 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
519 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
520 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
521 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
522 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
523 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
524 | SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
525 | SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
526 | }, | |
527 | .num_samplerates = 20, | |
528 | .samplerates = { | |
529 | SR_MHZ(125), SR_MHZ(100), | |
530 | SR_MHZ(50), SR_MHZ(20), SR_MHZ(10), | |
531 | SR_MHZ(5), SR_MHZ(2), SR_MHZ(1), | |
532 | SR_KHZ(500), SR_KHZ(200), SR_KHZ(100), | |
533 | SR_KHZ(50), SR_KHZ(20), SR_KHZ(10), | |
534 | SR_KHZ(5), SR_KHZ(2), SR_KHZ(1), | |
535 | SR_HZ(500), SR_HZ(200), SR_HZ(100), | |
536 | }, | |
537 | ||
538 | .apply_fpga_config = &apply_fpga_config, | |
539 | .device_init_check = &device_init_check, | |
540 | .setup_acquisition = &setup_acquisition, | |
541 | ||
542 | .prepare_request = &prepare_request, | |
543 | .handle_response = &handle_response, | |
544 | }; |