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Commit | Line | Data |
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df92e5cf | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
df92e5cf | 3 | * |
f48cef78 UH |
4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> |
5 | * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt> | |
6 | * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com> | |
df92e5cf | 7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
23 | ||
753d722f UH |
24 | /* serial protocol */ |
25 | #define mso_trans(a, v) \ | |
26 | (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \ | |
27 | ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7)) | |
28 | ||
29 | static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e }; | |
30 | static const char mso_foot[] = { 0x7e }; | |
31 | ||
df92e5cf | 32 | extern SR_PRIV struct sr_dev_driver link_mso19_driver_info; |
df92e5cf | 33 | |
4db2aaff | 34 | SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial, |
00b44ccb | 35 | uint16_t payload[], int n) |
4db2aaff | 36 | { |
37 | int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot); | |
38 | char *p, *buf; | |
39 | ||
40 | ret = SR_ERR; | |
41 | ||
42 | if (serial->fd < 0) | |
43 | goto ret; | |
44 | ||
a95f142e | 45 | buf = g_malloc(s); |
4db2aaff | 46 | |
47 | p = buf; | |
48 | memcpy(p, mso_head, sizeof(mso_head)); | |
49 | p += sizeof(mso_head); | |
50 | ||
51 | for (i = 0; i < n; i++) { | |
a24e9d04 | 52 | *(uint16_t *) p = g_htons(payload[i]); |
4db2aaff | 53 | p += 2; |
54 | } | |
55 | memcpy(p, mso_foot, sizeof(mso_foot)); | |
56 | ||
57 | w = 0; | |
58 | while (w < s) { | |
59 | ret = serial_write(serial, buf + w, s - w); | |
60 | if (ret < 0) { | |
61 | ret = SR_ERR; | |
62 | goto free; | |
63 | } | |
64 | w += ret; | |
65 | } | |
66 | ret = SR_OK; | |
67 | free: | |
68 | g_free(buf); | |
69 | ret: | |
70 | return ret; | |
71 | } | |
72 | ||
753d722f | 73 | SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi) |
4b719338 | 74 | { |
75 | struct dev_context *devc = sdi->priv; | |
087a9161 | 76 | uint16_t threshold_value = mso_calc_raw_from_mv(devc); |
4b719338 | 77 | |
00b44ccb UH |
78 | threshold_value = 0x153C; |
79 | uint8_t trigger_config = 0; | |
4b719338 | 80 | |
00b44ccb UH |
81 | if (devc->trigger_slope) |
82 | trigger_config |= 0x04; //Trigger on falling edge | |
4b719338 | 83 | |
84 | switch (devc->trigger_outsrc) { | |
85 | case 1: | |
00b44ccb | 86 | trigger_config |= 0x00; //Trigger pulse output |
4b719338 | 87 | break; |
88 | case 2: | |
00b44ccb | 89 | trigger_config |= 0x08; //PWM DAC from the pattern generator buffer |
4b719338 | 90 | break; |
91 | case 3: | |
00b44ccb | 92 | trigger_config |= 0x18; //White noise |
4b719338 | 93 | break; |
4b719338 | 94 | } |
95 | ||
087a9161 | 96 | switch (devc->trigger_chan) { |
00b44ccb UH |
97 | case 0: |
98 | trigger_config |= 0x00; //DSO level trigger //b00000000 | |
99 | break; | |
100 | case 1: | |
101 | trigger_config |= 0x20; //DSO level trigger & width < trigger_width | |
102 | break; | |
103 | case 2: | |
104 | trigger_config |= 0x40; //DSO level trigger & width >= trigger_width | |
105 | break; | |
106 | case 3: | |
107 | trigger_config |= 0x60; //LA combination trigger | |
108 | break; | |
109 | } | |
110 | ||
111 | //Last bit of trigger config reg 4 needs to be 1 for trigger enable, | |
112 | //otherwise the trigger is not enabled | |
113 | if (devc->use_trigger) | |
114 | trigger_config |= 0x80; | |
087a9161 | 115 | |
116 | uint16_t ops[18]; | |
117 | ops[0] = mso_trans(3, threshold_value & 0xff); | |
00b44ccb | 118 | //The trigger_config also holds the 2 MSB bits from the threshold value |
5952553f | 119 | ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03)); |
087a9161 | 120 | ops[2] = mso_trans(5, devc->la_trigger); |
121 | ops[3] = mso_trans(6, devc->la_trigger_mask); | |
122 | ops[4] = mso_trans(7, devc->trigger_holdoff[0]); | |
123 | ops[5] = mso_trans(8, devc->trigger_holdoff[1]); | |
124 | ||
125 | ops[6] = mso_trans(11, | |
00b44ccb UH |
126 | devc->dso_trigger_width / |
127 | SR_HZ_TO_NS(devc->cur_rate)); | |
4b719338 | 128 | |
129 | /* Select the SPI/I2C trigger config bank */ | |
087a9161 | 130 | ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2))); |
4b719338 | 131 | /* Configure the SPI/I2C protocol trigger */ |
087a9161 | 132 | ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]); |
133 | ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]); | |
134 | ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]); | |
135 | ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]); | |
136 | ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]); | |
137 | ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]); | |
138 | ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]); | |
139 | ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]); | |
140 | ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode); | |
4b719338 | 141 | /* Select the default config bank */ |
087a9161 | 142 | ops[17] = mso_trans(REG_CTL2, devc->ctlbase2); |
4b719338 | 143 | |
4db2aaff | 144 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
4b719338 | 145 | } |
146 | ||
753d722f | 147 | SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi) |
4b719338 | 148 | { |
149 | struct dev_context *devc = sdi->priv; | |
150 | ||
151 | return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]); | |
152 | } | |
153 | ||
154 | SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi) | |
155 | { | |
156 | uint16_t ops[] = { mso_trans(REG_BUFFER, 0) }; | |
157 | struct dev_context *devc = sdi->priv; | |
158 | ||
159 | sr_dbg("Requesting buffer dump."); | |
160 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
161 | } | |
162 | ||
753d722f | 163 | SR_PRIV int mso_arm(const struct sr_dev_inst *sdi) |
4b719338 | 164 | { |
165 | struct dev_context *devc = sdi->priv; | |
166 | uint16_t ops[] = { | |
167 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM), | |
168 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM), | |
169 | mso_trans(REG_CTL1, devc->ctlbase1), | |
170 | }; | |
171 | ||
172 | sr_dbg("Requesting trigger arm."); | |
173 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
174 | } | |
175 | ||
176 | SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi) | |
177 | { | |
178 | struct dev_context *devc = sdi->priv; | |
179 | uint16_t ops[] = { | |
180 | mso_trans(REG_CTL1, devc->ctlbase1 | 8), | |
181 | mso_trans(REG_CTL1, devc->ctlbase1), | |
182 | }; | |
183 | ||
184 | sr_dbg("Requesting forced capture."); | |
185 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
186 | } | |
187 | ||
753d722f | 188 | SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val) |
4b719338 | 189 | { |
190 | struct dev_context *devc = sdi->priv; | |
191 | uint16_t ops[] = { | |
192 | mso_trans(REG_DAC1, (val >> 8) & 0xff), | |
193 | mso_trans(REG_DAC2, val & 0xff), | |
194 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC), | |
195 | }; | |
196 | ||
197 | sr_dbg("Setting dac word to 0x%x.", val); | |
198 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
199 | } | |
200 | ||
00b44ccb | 201 | SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc) |
4b719338 | 202 | { |
203 | return (uint16_t) (0x200 - | |
00b44ccb UH |
204 | ((devc->dso_trigger_voltage / devc->dso_probe_attn) / |
205 | devc->vbit)); | |
4b719338 | 206 | } |
207 | ||
df92e5cf | 208 | SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct, |
00b44ccb | 209 | struct dev_context *devc) |
df92e5cf | 210 | { |
211 | unsigned int u1, u2, u3, u4, u5, u6; | |
212 | ||
31e53772 UH |
213 | (void)iProduct; |
214 | ||
00b44ccb UH |
215 | /* FIXME: This code is in the original app, but I think its |
216 | * used only for the GUI */ | |
217 | /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03")) | |
218 | devc->num_sample_rates = 0x16; | |
219 | else | |
220 | devc->num_sample_rates = 0x10; */ | |
df92e5cf | 221 | |
222 | /* parse iSerial */ | |
223 | if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u", | |
00b44ccb | 224 | &u1, &u2, &u3, &u4, &u5, &u6) != 6) |
df92e5cf | 225 | return SR_ERR; |
226 | devc->hwmodel = u4; | |
227 | devc->hwrev = u5; | |
df92e5cf | 228 | devc->vbit = u1 / 10000; |
229 | if (devc->vbit == 0) | |
230 | devc->vbit = 4.19195; | |
231 | devc->dac_offset = u2; | |
232 | if (devc->dac_offset == 0) | |
233 | devc->dac_offset = 0x1ff; | |
234 | devc->offset_range = u3; | |
235 | if (devc->offset_range == 0) | |
236 | devc->offset_range = 0x17d; | |
237 | ||
238 | /* | |
239 | * FIXME: There is more code on the original software to handle | |
240 | * bigger iSerial strings, but as I can't test on my device | |
241 | * I will not implement it yet | |
242 | */ | |
243 | ||
244 | return SR_OK; | |
245 | } | |
246 | ||
4db2aaff | 247 | SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi) |
df92e5cf | 248 | { |
4db2aaff | 249 | struct dev_context *devc = sdi->priv; |
250 | uint16_t ops[2]; | |
df92e5cf | 251 | |
4db2aaff | 252 | ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC)); |
253 | ops[1] = mso_trans(REG_CTL1, devc->ctlbase1); | |
254 | devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4; | |
df92e5cf | 255 | |
4db2aaff | 256 | sr_dbg("Requesting ADC reset."); |
257 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
258 | } | |
df92e5cf | 259 | |
4db2aaff | 260 | SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi) |
261 | { | |
262 | struct dev_context *devc = sdi->priv; | |
263 | uint16_t ops[1]; | |
df92e5cf | 264 | |
4db2aaff | 265 | devc->ctlbase1 |= BIT_CTL1_RESETFSM; |
266 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 267 | |
4db2aaff | 268 | sr_dbg("Requesting ADC reset."); |
269 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
df92e5cf | 270 | } |
271 | ||
4db2aaff | 272 | SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state) |
df92e5cf | 273 | { |
274 | struct dev_context *devc = sdi->priv; | |
4db2aaff | 275 | uint16_t ops[1]; |
df92e5cf | 276 | |
4db2aaff | 277 | devc->ctlbase1 &= ~BIT_CTL1_LED; |
278 | if (state) | |
279 | devc->ctlbase1 |= BIT_CTL1_LED; | |
280 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 281 | |
4db2aaff | 282 | sr_dbg("Requesting LED toggle."); |
df92e5cf | 283 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
284 | } | |
285 | ||
286 | SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi) | |
287 | { | |
288 | struct sr_datafeed_packet packet; | |
289 | struct dev_context *devc; | |
290 | ||
291 | devc = sdi->priv; | |
102f1239 | 292 | serial_source_remove(sdi->session, devc->serial); |
df92e5cf | 293 | |
294 | /* Terminate session */ | |
295 | packet.type = SR_DF_END; | |
296 | sr_session_send(sdi, &packet); | |
297 | } | |
298 | ||
299 | SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val) | |
300 | { | |
301 | uint16_t ops[] = { | |
302 | mso_trans(REG_CLKRATE1, (val >> 8) & 0xff), | |
303 | mso_trans(REG_CLKRATE2, val & 0xff), | |
304 | }; | |
305 | ||
306 | sr_dbg("Setting clkrate word to 0x%x.", val); | |
307 | return mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
308 | } | |
309 | ||
753d722f | 310 | SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate) |
df92e5cf | 311 | { |
312 | struct dev_context *devc = sdi->priv; | |
313 | unsigned int i; | |
314 | int ret = SR_ERR; | |
315 | ||
316 | for (i = 0; i < ARRAY_SIZE(rate_map); i++) { | |
317 | if (rate_map[i].rate == rate) { | |
318 | devc->ctlbase2 = rate_map[i].slowmode; | |
4b719338 | 319 | ret = mso_clkrate_out(devc->serial, rate_map[i].val); |
df92e5cf | 320 | if (ret == SR_OK) |
321 | devc->cur_rate = rate; | |
322 | return ret; | |
323 | } | |
324 | } | |
4db2aaff | 325 | |
00b44ccb | 326 | if (ret != SR_OK) |
4db2aaff | 327 | sr_err("Unsupported rate."); |
328 | ||
df92e5cf | 329 | return ret; |
330 | } | |
331 | ||
365f04d6 | 332 | SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info) |
df92e5cf | 333 | { |
334 | uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) }; | |
335 | int ret; | |
336 | ||
337 | sr_dbg("Requesting trigger state."); | |
338 | ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
98fec29e | 339 | if (!info || ret != SR_OK) |
df92e5cf | 340 | return ret; |
341 | ||
00b44ccb UH |
342 | uint8_t buf = 0; |
343 | if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */ | |
df92e5cf | 344 | ret = SR_ERR; |
365f04d6 | 345 | if (!info) |
346 | *info = buf; | |
df92e5cf | 347 | |
348 | sr_dbg("Trigger state is: 0x%x.", *info); | |
349 | return ret; | |
350 | } | |
351 | ||
352 | SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data) | |
353 | { | |
df92e5cf | 354 | struct sr_datafeed_packet packet; |
355 | struct sr_datafeed_logic logic; | |
356 | struct sr_dev_inst *sdi; | |
df92e5cf | 357 | GSList *l; |
4db2aaff | 358 | int i; |
df92e5cf | 359 | |
41812aca | 360 | struct drv_context *drvc = di->context; |
df92e5cf | 361 | |
362 | /* Find this device's devc struct by its fd. */ | |
4db2aaff | 363 | struct dev_context *devc = NULL; |
df92e5cf | 364 | for (l = drvc->instances; l; l = l->next) { |
365 | sdi = l->data; | |
366 | devc = sdi->priv; | |
367 | if (devc->serial->fd == fd) | |
368 | break; | |
369 | devc = NULL; | |
370 | } | |
371 | if (!devc) | |
372 | /* Shouldn't happen. */ | |
373 | return TRUE; | |
374 | ||
375 | (void)revents; | |
376 | ||
377 | uint8_t in[1024]; | |
378 | size_t s = serial_read(devc->serial, in, sizeof(in)); | |
5a24e89c | 379 | |
df92e5cf | 380 | if (s <= 0) |
381 | return FALSE; | |
00b44ccb UH |
382 | |
383 | /* Check if we triggered, then send a command that we are ready | |
384 | * to read the data */ | |
385 | if (devc->trigger_state != MSO_TRIGGER_DATAREADY) { | |
386 | devc->trigger_state = in[0]; | |
387 | if (devc->trigger_state == MSO_TRIGGER_DATAREADY) { | |
388 | mso_read_buffer(sdi); | |
389 | devc->buffer_n = 0; | |
390 | } else { | |
391 | mso_check_trigger(devc->serial, NULL); | |
392 | } | |
393 | return TRUE; | |
394 | } | |
df92e5cf | 395 | |
396 | /* the hardware always dumps 1024 samples, 24bits each */ | |
397 | if (devc->buffer_n < 3072) { | |
398 | memcpy(devc->buffer + devc->buffer_n, in, s); | |
399 | devc->buffer_n += s; | |
400 | } | |
401 | if (devc->buffer_n < 3072) | |
5a24e89c | 402 | return TRUE; |
df92e5cf | 403 | |
404 | /* do the conversion */ | |
405 | uint8_t logic_out[1024]; | |
406 | double analog_out[1024]; | |
407 | for (i = 0; i < 1024; i++) { | |
408 | /* FIXME: Need to do conversion to mV */ | |
409 | analog_out[i] = (devc->buffer[i * 3] & 0x3f) | | |
00b44ccb | 410 | ((devc->buffer[i * 3 + 1] & 0xf) << 6); |
ff08a52a | 411 | (void)analog_out; |
df92e5cf | 412 | logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) | |
00b44ccb | 413 | ((devc->buffer[i * 3 + 2] & 0x3f) << 2); |
df92e5cf | 414 | } |
415 | ||
416 | packet.type = SR_DF_LOGIC; | |
417 | packet.payload = &logic; | |
418 | logic.length = 1024; | |
419 | logic.unitsize = 1; | |
420 | logic.data = logic_out; | |
421 | sr_session_send(cb_data, &packet); | |
422 | ||
00b44ccb | 423 | devc->num_samples += 1024; |
eb913174 | 424 | |
00b44ccb UH |
425 | if (devc->limit_samples && devc->num_samples >= devc->limit_samples) { |
426 | sr_info("Requested number of samples reached."); | |
427 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
428 | } | |
429 | ||
430 | return TRUE; | |
df92e5cf | 431 | } |
5a24e89c | 432 | |
ba7dd8bb | 433 | SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi) |
5a24e89c | 434 | { |
5a24e89c | 435 | struct dev_context *devc; |
ba7dd8bb | 436 | struct sr_channel *ch; |
5a24e89c | 437 | GSList *l; |
5a24e89c | 438 | char *tc; |
439 | ||
5a24e89c | 440 | devc = sdi->priv; |
5a24e89c | 441 | |
00b44ccb UH |
442 | devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored). |
443 | devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode). | |
444 | devc->dso_trigger_voltage = 3; | |
445 | devc->dso_probe_attn = 1; | |
446 | devc->trigger_outsrc = 0; | |
447 | devc->trigger_chan = 3; //LA combination trigger | |
448 | devc->use_trigger = FALSE; | |
087a9161 | 449 | |
ba7dd8bb UH |
450 | for (l = sdi->channels; l; l = l->next) { |
451 | ch = (struct sr_channel *)l->data; | |
452 | if (ch->enabled == FALSE) | |
5a24e89c | 453 | continue; |
454 | ||
ba7dd8bb UH |
455 | int channel_bit = 1 << (ch->index); |
456 | if (!(ch->trigger)) | |
5a24e89c | 457 | continue; |
458 | ||
00b44ccb | 459 | devc->use_trigger = TRUE; |
5a24e89c | 460 | //Configure trigger mask and value. |
ba7dd8bb UH |
461 | for (tc = ch->trigger; *tc; tc++) { |
462 | devc->la_trigger_mask &= ~channel_bit; | |
00b44ccb | 463 | if (*tc == '1') |
ba7dd8bb | 464 | devc->la_trigger |= channel_bit; |
00b44ccb UH |
465 | } |
466 | } | |
5a24e89c | 467 | |
468 | return SR_OK; | |
5a24e89c | 469 | } |