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df92e5cf | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
df92e5cf | 3 | * |
f48cef78 UH |
4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> |
5 | * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt> | |
6 | * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com> | |
df92e5cf | 7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
23 | ||
753d722f UH |
24 | /* serial protocol */ |
25 | #define mso_trans(a, v) \ | |
26 | (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \ | |
27 | ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7)) | |
28 | ||
29 | static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e }; | |
30 | static const char mso_foot[] = { 0x7e }; | |
31 | ||
df92e5cf | 32 | extern SR_PRIV struct sr_dev_driver link_mso19_driver_info; |
33 | static struct sr_dev_driver *di = &link_mso19_driver_info; | |
34 | ||
4db2aaff | 35 | SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial, |
00b44ccb | 36 | uint16_t payload[], int n) |
4db2aaff | 37 | { |
38 | int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot); | |
39 | char *p, *buf; | |
40 | ||
41 | ret = SR_ERR; | |
42 | ||
43 | if (serial->fd < 0) | |
44 | goto ret; | |
45 | ||
46 | if (!(buf = g_try_malloc(s))) { | |
47 | sr_err("Failed to malloc message buffer."); | |
48 | ret = SR_ERR_MALLOC; | |
49 | goto ret; | |
50 | } | |
51 | ||
52 | p = buf; | |
53 | memcpy(p, mso_head, sizeof(mso_head)); | |
54 | p += sizeof(mso_head); | |
55 | ||
56 | for (i = 0; i < n; i++) { | |
a24e9d04 | 57 | *(uint16_t *) p = g_htons(payload[i]); |
4db2aaff | 58 | p += 2; |
59 | } | |
60 | memcpy(p, mso_foot, sizeof(mso_foot)); | |
61 | ||
62 | w = 0; | |
63 | while (w < s) { | |
64 | ret = serial_write(serial, buf + w, s - w); | |
65 | if (ret < 0) { | |
66 | ret = SR_ERR; | |
67 | goto free; | |
68 | } | |
69 | w += ret; | |
70 | } | |
71 | ret = SR_OK; | |
72 | free: | |
73 | g_free(buf); | |
74 | ret: | |
75 | return ret; | |
76 | } | |
77 | ||
753d722f | 78 | SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi) |
4b719338 | 79 | { |
80 | struct dev_context *devc = sdi->priv; | |
087a9161 | 81 | uint16_t threshold_value = mso_calc_raw_from_mv(devc); |
4b719338 | 82 | |
00b44ccb UH |
83 | threshold_value = 0x153C; |
84 | uint8_t trigger_config = 0; | |
4b719338 | 85 | |
00b44ccb UH |
86 | if (devc->trigger_slope) |
87 | trigger_config |= 0x04; //Trigger on falling edge | |
4b719338 | 88 | |
89 | switch (devc->trigger_outsrc) { | |
90 | case 1: | |
00b44ccb | 91 | trigger_config |= 0x00; //Trigger pulse output |
4b719338 | 92 | break; |
93 | case 2: | |
00b44ccb | 94 | trigger_config |= 0x08; //PWM DAC from the pattern generator buffer |
4b719338 | 95 | break; |
96 | case 3: | |
00b44ccb | 97 | trigger_config |= 0x18; //White noise |
4b719338 | 98 | break; |
4b719338 | 99 | } |
100 | ||
087a9161 | 101 | switch (devc->trigger_chan) { |
00b44ccb UH |
102 | case 0: |
103 | trigger_config |= 0x00; //DSO level trigger //b00000000 | |
104 | break; | |
105 | case 1: | |
106 | trigger_config |= 0x20; //DSO level trigger & width < trigger_width | |
107 | break; | |
108 | case 2: | |
109 | trigger_config |= 0x40; //DSO level trigger & width >= trigger_width | |
110 | break; | |
111 | case 3: | |
112 | trigger_config |= 0x60; //LA combination trigger | |
113 | break; | |
114 | } | |
115 | ||
116 | //Last bit of trigger config reg 4 needs to be 1 for trigger enable, | |
117 | //otherwise the trigger is not enabled | |
118 | if (devc->use_trigger) | |
119 | trigger_config |= 0x80; | |
087a9161 | 120 | |
121 | uint16_t ops[18]; | |
122 | ops[0] = mso_trans(3, threshold_value & 0xff); | |
00b44ccb | 123 | //The trigger_config also holds the 2 MSB bits from the threshold value |
5952553f | 124 | ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03)); |
087a9161 | 125 | ops[2] = mso_trans(5, devc->la_trigger); |
126 | ops[3] = mso_trans(6, devc->la_trigger_mask); | |
127 | ops[4] = mso_trans(7, devc->trigger_holdoff[0]); | |
128 | ops[5] = mso_trans(8, devc->trigger_holdoff[1]); | |
129 | ||
130 | ops[6] = mso_trans(11, | |
00b44ccb UH |
131 | devc->dso_trigger_width / |
132 | SR_HZ_TO_NS(devc->cur_rate)); | |
4b719338 | 133 | |
134 | /* Select the SPI/I2C trigger config bank */ | |
087a9161 | 135 | ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2))); |
4b719338 | 136 | /* Configure the SPI/I2C protocol trigger */ |
087a9161 | 137 | ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]); |
138 | ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]); | |
139 | ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]); | |
140 | ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]); | |
141 | ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]); | |
142 | ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]); | |
143 | ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]); | |
144 | ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]); | |
145 | ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode); | |
4b719338 | 146 | /* Select the default config bank */ |
087a9161 | 147 | ops[17] = mso_trans(REG_CTL2, devc->ctlbase2); |
4b719338 | 148 | |
4db2aaff | 149 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
4b719338 | 150 | } |
151 | ||
753d722f | 152 | SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi) |
4b719338 | 153 | { |
154 | struct dev_context *devc = sdi->priv; | |
155 | ||
156 | return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]); | |
157 | } | |
158 | ||
159 | SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi) | |
160 | { | |
161 | uint16_t ops[] = { mso_trans(REG_BUFFER, 0) }; | |
162 | struct dev_context *devc = sdi->priv; | |
163 | ||
164 | sr_dbg("Requesting buffer dump."); | |
165 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
166 | } | |
167 | ||
753d722f | 168 | SR_PRIV int mso_arm(const struct sr_dev_inst *sdi) |
4b719338 | 169 | { |
170 | struct dev_context *devc = sdi->priv; | |
171 | uint16_t ops[] = { | |
172 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM), | |
173 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM), | |
174 | mso_trans(REG_CTL1, devc->ctlbase1), | |
175 | }; | |
176 | ||
177 | sr_dbg("Requesting trigger arm."); | |
178 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
179 | } | |
180 | ||
181 | SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi) | |
182 | { | |
183 | struct dev_context *devc = sdi->priv; | |
184 | uint16_t ops[] = { | |
185 | mso_trans(REG_CTL1, devc->ctlbase1 | 8), | |
186 | mso_trans(REG_CTL1, devc->ctlbase1), | |
187 | }; | |
188 | ||
189 | sr_dbg("Requesting forced capture."); | |
190 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
191 | } | |
192 | ||
753d722f | 193 | SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val) |
4b719338 | 194 | { |
195 | struct dev_context *devc = sdi->priv; | |
196 | uint16_t ops[] = { | |
197 | mso_trans(REG_DAC1, (val >> 8) & 0xff), | |
198 | mso_trans(REG_DAC2, val & 0xff), | |
199 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC), | |
200 | }; | |
201 | ||
202 | sr_dbg("Setting dac word to 0x%x.", val); | |
203 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
204 | } | |
205 | ||
00b44ccb | 206 | SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc) |
4b719338 | 207 | { |
208 | return (uint16_t) (0x200 - | |
00b44ccb UH |
209 | ((devc->dso_trigger_voltage / devc->dso_probe_attn) / |
210 | devc->vbit)); | |
4b719338 | 211 | } |
212 | ||
df92e5cf | 213 | SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct, |
00b44ccb | 214 | struct dev_context *devc) |
df92e5cf | 215 | { |
216 | unsigned int u1, u2, u3, u4, u5, u6; | |
217 | ||
31e53772 UH |
218 | (void)iProduct; |
219 | ||
00b44ccb UH |
220 | /* FIXME: This code is in the original app, but I think its |
221 | * used only for the GUI */ | |
222 | /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03")) | |
223 | devc->num_sample_rates = 0x16; | |
224 | else | |
225 | devc->num_sample_rates = 0x10; */ | |
df92e5cf | 226 | |
227 | /* parse iSerial */ | |
228 | if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u", | |
00b44ccb | 229 | &u1, &u2, &u3, &u4, &u5, &u6) != 6) |
df92e5cf | 230 | return SR_ERR; |
231 | devc->hwmodel = u4; | |
232 | devc->hwrev = u5; | |
df92e5cf | 233 | devc->vbit = u1 / 10000; |
234 | if (devc->vbit == 0) | |
235 | devc->vbit = 4.19195; | |
236 | devc->dac_offset = u2; | |
237 | if (devc->dac_offset == 0) | |
238 | devc->dac_offset = 0x1ff; | |
239 | devc->offset_range = u3; | |
240 | if (devc->offset_range == 0) | |
241 | devc->offset_range = 0x17d; | |
242 | ||
243 | /* | |
244 | * FIXME: There is more code on the original software to handle | |
245 | * bigger iSerial strings, but as I can't test on my device | |
246 | * I will not implement it yet | |
247 | */ | |
248 | ||
249 | return SR_OK; | |
250 | } | |
251 | ||
4db2aaff | 252 | SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi) |
df92e5cf | 253 | { |
4db2aaff | 254 | struct dev_context *devc = sdi->priv; |
255 | uint16_t ops[2]; | |
df92e5cf | 256 | |
4db2aaff | 257 | ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC)); |
258 | ops[1] = mso_trans(REG_CTL1, devc->ctlbase1); | |
259 | devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4; | |
df92e5cf | 260 | |
4db2aaff | 261 | sr_dbg("Requesting ADC reset."); |
262 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
263 | } | |
df92e5cf | 264 | |
4db2aaff | 265 | SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi) |
266 | { | |
267 | struct dev_context *devc = sdi->priv; | |
268 | uint16_t ops[1]; | |
df92e5cf | 269 | |
4db2aaff | 270 | devc->ctlbase1 |= BIT_CTL1_RESETFSM; |
271 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 272 | |
4db2aaff | 273 | sr_dbg("Requesting ADC reset."); |
274 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
df92e5cf | 275 | } |
276 | ||
4db2aaff | 277 | SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state) |
df92e5cf | 278 | { |
279 | struct dev_context *devc = sdi->priv; | |
4db2aaff | 280 | uint16_t ops[1]; |
df92e5cf | 281 | |
4db2aaff | 282 | devc->ctlbase1 &= ~BIT_CTL1_LED; |
283 | if (state) | |
284 | devc->ctlbase1 |= BIT_CTL1_LED; | |
285 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 286 | |
4db2aaff | 287 | sr_dbg("Requesting LED toggle."); |
df92e5cf | 288 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
289 | } | |
290 | ||
291 | SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi) | |
292 | { | |
293 | struct sr_datafeed_packet packet; | |
294 | struct dev_context *devc; | |
295 | ||
296 | devc = sdi->priv; | |
102f1239 | 297 | serial_source_remove(sdi->session, devc->serial); |
df92e5cf | 298 | |
299 | /* Terminate session */ | |
300 | packet.type = SR_DF_END; | |
301 | sr_session_send(sdi, &packet); | |
302 | } | |
303 | ||
304 | SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val) | |
305 | { | |
306 | uint16_t ops[] = { | |
307 | mso_trans(REG_CLKRATE1, (val >> 8) & 0xff), | |
308 | mso_trans(REG_CLKRATE2, val & 0xff), | |
309 | }; | |
310 | ||
311 | sr_dbg("Setting clkrate word to 0x%x.", val); | |
312 | return mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
313 | } | |
314 | ||
753d722f | 315 | SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate) |
df92e5cf | 316 | { |
317 | struct dev_context *devc = sdi->priv; | |
318 | unsigned int i; | |
319 | int ret = SR_ERR; | |
320 | ||
321 | for (i = 0; i < ARRAY_SIZE(rate_map); i++) { | |
322 | if (rate_map[i].rate == rate) { | |
323 | devc->ctlbase2 = rate_map[i].slowmode; | |
4b719338 | 324 | ret = mso_clkrate_out(devc->serial, rate_map[i].val); |
df92e5cf | 325 | if (ret == SR_OK) |
326 | devc->cur_rate = rate; | |
327 | return ret; | |
328 | } | |
329 | } | |
4db2aaff | 330 | |
00b44ccb | 331 | if (ret != SR_OK) |
4db2aaff | 332 | sr_err("Unsupported rate."); |
333 | ||
df92e5cf | 334 | return ret; |
335 | } | |
336 | ||
365f04d6 | 337 | SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info) |
df92e5cf | 338 | { |
339 | uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) }; | |
340 | int ret; | |
341 | ||
342 | sr_dbg("Requesting trigger state."); | |
343 | ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
344 | if (info == NULL || ret != SR_OK) | |
345 | return ret; | |
346 | ||
00b44ccb UH |
347 | uint8_t buf = 0; |
348 | if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */ | |
df92e5cf | 349 | ret = SR_ERR; |
365f04d6 | 350 | if (!info) |
351 | *info = buf; | |
df92e5cf | 352 | |
353 | sr_dbg("Trigger state is: 0x%x.", *info); | |
354 | return ret; | |
355 | } | |
356 | ||
357 | SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data) | |
358 | { | |
df92e5cf | 359 | struct sr_datafeed_packet packet; |
360 | struct sr_datafeed_logic logic; | |
361 | struct sr_dev_inst *sdi; | |
df92e5cf | 362 | GSList *l; |
4db2aaff | 363 | int i; |
df92e5cf | 364 | |
4db2aaff | 365 | struct drv_context *drvc = di->priv; |
df92e5cf | 366 | |
367 | /* Find this device's devc struct by its fd. */ | |
4db2aaff | 368 | struct dev_context *devc = NULL; |
df92e5cf | 369 | for (l = drvc->instances; l; l = l->next) { |
370 | sdi = l->data; | |
371 | devc = sdi->priv; | |
372 | if (devc->serial->fd == fd) | |
373 | break; | |
374 | devc = NULL; | |
375 | } | |
376 | if (!devc) | |
377 | /* Shouldn't happen. */ | |
378 | return TRUE; | |
379 | ||
380 | (void)revents; | |
381 | ||
382 | uint8_t in[1024]; | |
383 | size_t s = serial_read(devc->serial, in, sizeof(in)); | |
5a24e89c | 384 | |
df92e5cf | 385 | if (s <= 0) |
386 | return FALSE; | |
00b44ccb UH |
387 | |
388 | /* Check if we triggered, then send a command that we are ready | |
389 | * to read the data */ | |
390 | if (devc->trigger_state != MSO_TRIGGER_DATAREADY) { | |
391 | devc->trigger_state = in[0]; | |
392 | if (devc->trigger_state == MSO_TRIGGER_DATAREADY) { | |
393 | mso_read_buffer(sdi); | |
394 | devc->buffer_n = 0; | |
395 | } else { | |
396 | mso_check_trigger(devc->serial, NULL); | |
397 | } | |
398 | return TRUE; | |
399 | } | |
df92e5cf | 400 | |
401 | /* the hardware always dumps 1024 samples, 24bits each */ | |
402 | if (devc->buffer_n < 3072) { | |
403 | memcpy(devc->buffer + devc->buffer_n, in, s); | |
404 | devc->buffer_n += s; | |
405 | } | |
406 | if (devc->buffer_n < 3072) | |
5a24e89c | 407 | return TRUE; |
df92e5cf | 408 | |
409 | /* do the conversion */ | |
410 | uint8_t logic_out[1024]; | |
411 | double analog_out[1024]; | |
412 | for (i = 0; i < 1024; i++) { | |
413 | /* FIXME: Need to do conversion to mV */ | |
414 | analog_out[i] = (devc->buffer[i * 3] & 0x3f) | | |
00b44ccb | 415 | ((devc->buffer[i * 3 + 1] & 0xf) << 6); |
ff08a52a | 416 | (void)analog_out; |
df92e5cf | 417 | logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) | |
00b44ccb | 418 | ((devc->buffer[i * 3 + 2] & 0x3f) << 2); |
df92e5cf | 419 | } |
420 | ||
421 | packet.type = SR_DF_LOGIC; | |
422 | packet.payload = &logic; | |
423 | logic.length = 1024; | |
424 | logic.unitsize = 1; | |
425 | logic.data = logic_out; | |
426 | sr_session_send(cb_data, &packet); | |
427 | ||
00b44ccb | 428 | devc->num_samples += 1024; |
eb913174 | 429 | |
00b44ccb UH |
430 | if (devc->limit_samples && devc->num_samples >= devc->limit_samples) { |
431 | sr_info("Requested number of samples reached."); | |
432 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
433 | } | |
434 | ||
435 | return TRUE; | |
df92e5cf | 436 | } |
5a24e89c | 437 | |
ba7dd8bb | 438 | SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi) |
5a24e89c | 439 | { |
5a24e89c | 440 | struct dev_context *devc; |
ba7dd8bb | 441 | struct sr_channel *ch; |
5a24e89c | 442 | GSList *l; |
5a24e89c | 443 | char *tc; |
444 | ||
5a24e89c | 445 | devc = sdi->priv; |
5a24e89c | 446 | |
00b44ccb UH |
447 | devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored). |
448 | devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode). | |
449 | devc->dso_trigger_voltage = 3; | |
450 | devc->dso_probe_attn = 1; | |
451 | devc->trigger_outsrc = 0; | |
452 | devc->trigger_chan = 3; //LA combination trigger | |
453 | devc->use_trigger = FALSE; | |
087a9161 | 454 | |
ba7dd8bb UH |
455 | for (l = sdi->channels; l; l = l->next) { |
456 | ch = (struct sr_channel *)l->data; | |
457 | if (ch->enabled == FALSE) | |
5a24e89c | 458 | continue; |
459 | ||
ba7dd8bb UH |
460 | int channel_bit = 1 << (ch->index); |
461 | if (!(ch->trigger)) | |
5a24e89c | 462 | continue; |
463 | ||
00b44ccb | 464 | devc->use_trigger = TRUE; |
5a24e89c | 465 | //Configure trigger mask and value. |
ba7dd8bb UH |
466 | for (tc = ch->trigger; *tc; tc++) { |
467 | devc->la_trigger_mask &= ~channel_bit; | |
00b44ccb | 468 | if (*tc == '1') |
ba7dd8bb | 469 | devc->la_trigger |= channel_bit; |
00b44ccb UH |
470 | } |
471 | } | |
5a24e89c | 472 | |
473 | return SR_OK; | |
5a24e89c | 474 | } |