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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
24 | #include <stdint.h> | |
25 | #include <string.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <stdio.h> | |
29 | #include <errno.h> | |
30 | #include <math.h> | |
3f48ab02 | 31 | #include <inttypes.h> |
f2cd2deb FS |
32 | #include <libsigrok/libsigrok.h> |
33 | #include "libsigrok-internal.h" | |
34 | #include "protocol.h" | |
35 | ||
f2cd2deb | 36 | #define UC_FIRMWARE "kingst-la-%04x.fw" |
9de389b1 KG |
37 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" |
38 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
8b172e78 KG |
39 | #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" |
40 | #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" | |
f2cd2deb | 41 | |
8b172e78 KG |
42 | #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) |
43 | #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) | |
f2cd2deb FS |
44 | #define MAX_SAMPLE_DEPTH 10e9 |
45 | #define MAX_PWM_FREQ SR_MHZ(20) | |
8b172e78 | 46 | #define PWM_CLOCK SR_MHZ(200) /* this is 200MHz for both the LA2016 and LA1016 */ |
f2cd2deb | 47 | |
00849545 | 48 | /* usb vendor class control requests to the cypress FX2 microcontroller */ |
84fe94bd SA |
49 | #define CMD_FPGA_ENABLE 0x10 |
50 | #define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ | |
51 | #define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ | |
52 | #define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ | |
53 | #define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ | |
54 | #define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ | |
55 | #define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ | |
00849545 | 56 | |
42f6dd55 KG |
57 | /* |
58 | * fpga spi register addresses for control request CMD_FPGA_SPI: | |
59 | * There are around 60 byte-wide registers within the fpga and | |
60 | * these are the base addresses used for accessing them. | |
61 | * On the spi bus, the msb of the address byte is set for read | |
62 | * and cleared for write, but that is handled by the fx2 mcu | |
63 | * as appropriate. In this driver code just use IN transactions | |
64 | * to read, OUT to write. | |
65 | */ | |
84fe94bd SA |
66 | #define REG_RUN 0x00 /* read capture status, write capture start */ |
67 | #define REG_PWM_EN 0x02 /* user pwm channels on/off */ | |
68 | #define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ | |
69 | #define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ | |
70 | #define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ | |
71 | #define REG_TRIGGER 0x20 /* write level and edge trigger config */ | |
72 | #define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ | |
73 | #define REG_PWM1 0x70 /* write config for user pwm1 */ | |
74 | #define REG_PWM2 0x78 /* write config for user pwm2 */ | |
f2cd2deb FS |
75 | |
76 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
77 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
78 | void *data, uint16_t wLength) | |
79 | { | |
80 | struct sr_usb_dev_inst *usb; | |
81 | int ret; | |
82 | ||
83 | usb = sdi->conn; | |
84 | ||
85 | if ((ret = libusb_control_transfer( | |
86 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
87 | bRequest, wValue, wIndex, (unsigned char *)data, wLength, | |
88 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
89 | sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.", | |
90 | wLength, bRequest, wValue, wIndex, | |
91 | libusb_error_name(ret)); | |
92 | return SR_ERR; | |
93 | } | |
94 | ||
95 | return SR_OK; | |
96 | } | |
97 | ||
98 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
99 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
100 | void *data, uint16_t wLength) | |
101 | { | |
102 | struct sr_usb_dev_inst *usb; | |
103 | int ret; | |
104 | ||
105 | usb = sdi->conn; | |
106 | ||
107 | if ((ret = libusb_control_transfer( | |
108 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
109 | bRequest, wValue, wIndex, (unsigned char*)data, wLength, | |
110 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
111 | sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.", | |
112 | wLength, bRequest, wValue, wIndex, | |
113 | libusb_error_name(ret)); | |
114 | return SR_ERR; | |
115 | } | |
116 | ||
117 | return SR_OK; | |
118 | } | |
119 | ||
9de389b1 | 120 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname) |
f2cd2deb | 121 | { |
3f48ab02 | 122 | struct dev_context *devc; |
f2cd2deb FS |
123 | struct drv_context *drvc; |
124 | struct sr_usb_dev_inst *usb; | |
125 | struct sr_resource bitstream; | |
c3d40037 HK |
126 | uint8_t buffer[sizeof(uint32_t)]; |
127 | uint8_t *wrptr; | |
f2cd2deb FS |
128 | uint8_t cmd_resp; |
129 | uint8_t block[4096]; | |
3f48ab02 FS |
130 | int len, act_len; |
131 | unsigned int pos; | |
f2cd2deb | 132 | int ret; |
3f48ab02 | 133 | unsigned int zero_pad_to = 0x2c000; |
f2cd2deb | 134 | |
3f48ab02 | 135 | devc = sdi->priv; |
f2cd2deb FS |
136 | drvc = sdi->driver->context; |
137 | usb = sdi->conn; | |
138 | ||
9de389b1 | 139 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 140 | |
9de389b1 | 141 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); |
f2cd2deb | 142 | if (ret != SR_OK) { |
9de389b1 | 143 | sr_err("could not find fpga firmware %s!", bitstream_fname); |
f2cd2deb FS |
144 | return ret; |
145 | } | |
146 | ||
3f48ab02 | 147 | devc->bitstream_size = (uint32_t)bitstream.size; |
c3d40037 HK |
148 | wrptr = buffer; |
149 | write_u32le_inc(&wrptr, devc->bitstream_size); | |
00849545 | 150 | if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { |
f2cd2deb FS |
151 | sr_err("failed to give upload init command"); |
152 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
153 | return ret; | |
154 | } | |
155 | ||
156 | pos = 0; | |
157 | while (1) { | |
3f48ab02 FS |
158 | if (pos < bitstream.size) { |
159 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); | |
160 | if (len < 0) { | |
161 | sr_err("failed to read from fpga bitstream!"); | |
162 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
163 | return SR_ERR; | |
164 | } | |
165 | } else { | |
166 | // fill with zero's until zero_pad_to | |
167 | len = zero_pad_to - pos; | |
168 | if ((unsigned)len > sizeof(block)) | |
169 | len = sizeof(block); | |
170 | memset(&block, 0, len); | |
f2cd2deb FS |
171 | } |
172 | if (len == 0) | |
173 | break; | |
174 | ||
175 | ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
176 | if (ret != 0) { | |
177 | sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); | |
178 | ret = SR_ERR; | |
179 | break; | |
180 | } | |
181 | if (act_len != len) { | |
182 | sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len); | |
183 | ret = SR_ERR; | |
184 | break; | |
185 | } | |
186 | pos += len; | |
187 | } | |
188 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
189 | if (ret != 0) | |
190 | return ret; | |
3f48ab02 | 191 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size); |
f2cd2deb | 192 | |
00849545 | 193 | if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { |
f2cd2deb FS |
194 | sr_err("failed to read response after FPGA bitstream upload"); |
195 | return ret; | |
196 | } | |
3f48ab02 FS |
197 | if (cmd_resp != 0) { |
198 | sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp); | |
199 | return SR_ERR; | |
200 | } | |
201 | ||
202 | g_usleep(30000); | |
f2cd2deb | 203 | |
00849545 | 204 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
205 | sr_err("failed enable fpga"); |
206 | return ret; | |
207 | } | |
208 | ||
3f48ab02 | 209 | g_usleep(40000); |
f2cd2deb FS |
210 | return SR_OK; |
211 | } | |
212 | ||
213 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
214 | { | |
215 | struct dev_context *devc; | |
f2cd2deb FS |
216 | int ret; |
217 | ||
218 | devc = sdi->priv; | |
f2cd2deb | 219 | |
f2ad79d1 KG |
220 | uint16_t duty_R79,duty_R56; |
221 | uint8_t buf[2 * sizeof(uint16_t)]; | |
222 | uint8_t *wrptr; | |
223 | ||
224 | /* clamp threshold setting within valid range for LA2016 */ | |
225 | if (voltage > 4.0) { | |
226 | voltage = 4.0; | |
227 | } | |
228 | else if (voltage < -4.0) { | |
229 | voltage = -4.0; | |
230 | } | |
231 | ||
232 | /* | |
233 | * The fpga has two programmable pwm outputs which feed a dac that | |
234 | * is used to adjust input offset. The dac changes the input | |
235 | * swing around the fixed fpga input threshold. | |
236 | * The two pwm outputs can be seen on R79 and R56 respectvely. | |
237 | * Frequency is fixed at 100kHz and duty is varied. | |
238 | * The R79 pwm uses just three settings. | |
239 | * The R56 pwm varies with required threshold and its behaviour | |
240 | * also changes depending on the setting of R79 PWM. | |
241 | */ | |
242 | ||
243 | /* | |
244 | * calculate required pwm duty register values from requested threshold voltage | |
245 | * see last page of schematic (on wiki) for an explanation of these numbers | |
246 | */ | |
247 | if (voltage >= 2.9) { | |
248 | duty_R79 = 0; /* this pwm is off (0V)*/ | |
249 | duty_R56 = (uint16_t)(302 * voltage - 363); | |
250 | } | |
251 | else if (voltage <= -0.4) { | |
252 | duty_R79 = 0x02D7; /* 72% duty */ | |
253 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
254 | } | |
255 | else { | |
256 | duty_R79 = 0x00f2; /* 25% duty */ | |
257 | duty_R56 = (uint16_t)(302 * voltage + 121); | |
258 | } | |
259 | ||
260 | /* clamp duty register values at sensible limits */ | |
261 | if (duty_R56 < 10) { | |
262 | duty_R56 = 10; | |
263 | } | |
264 | else if (duty_R56 > 1100) { | |
265 | duty_R56 = 1100; | |
266 | } | |
267 | ||
268 | sr_dbg("set threshold voltage %.2fV", voltage); | |
269 | sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79); | |
270 | ||
271 | wrptr = buf; | |
272 | write_u16le_inc(&wrptr, duty_R56); | |
273 | write_u16le_inc(&wrptr, duty_R79); | |
274 | ||
275 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 276 | if (ret != SR_OK) { |
f2ad79d1 | 277 | sr_err("error setting new threshold voltage of %.2fV", voltage); |
f2cd2deb FS |
278 | return ret; |
279 | } | |
280 | devc->threshold_voltage = voltage; | |
281 | ||
282 | return SR_OK; | |
283 | } | |
284 | ||
285 | static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) | |
286 | { | |
287 | struct dev_context *devc; | |
288 | uint8_t cfg; | |
289 | int ret; | |
290 | ||
291 | devc = sdi->priv; | |
292 | cfg = 0; | |
293 | ||
294 | if (p1) cfg |= 1 << 0; | |
295 | if (p2) cfg |= 1 << 1; | |
296 | ||
297 | sr_dbg("set pwm enable %d %d", p1, p2); | |
42f6dd55 | 298 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb FS |
299 | if (ret != SR_OK) { |
300 | sr_err("error setting new pwm enable 0x%02x", cfg); | |
301 | return ret; | |
302 | } | |
303 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; | |
304 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
305 | ||
306 | return SR_OK; | |
307 | } | |
308 | ||
309 | static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) | |
310 | { | |
42f6dd55 | 311 | int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; |
f2cd2deb FS |
312 | struct dev_context *devc; |
313 | pwm_setting_dev_t cfg; | |
314 | pwm_setting_t *setting; | |
315 | int ret; | |
c3d40037 HK |
316 | uint8_t buf[2 * sizeof(uint32_t)]; |
317 | uint8_t *wrptr; | |
f2cd2deb FS |
318 | |
319 | devc = sdi->priv; | |
320 | ||
321 | if (which < 1 || which > 2) { | |
322 | sr_err("invalid pwm channel: %d", which); | |
323 | return SR_ERR; | |
324 | } | |
325 | if (freq > MAX_PWM_FREQ) { | |
326 | sr_err("pwm frequency too high: %.1f", freq); | |
327 | return SR_ERR; | |
328 | } | |
329 | if (duty > 100 || duty < 0) { | |
330 | sr_err("invalid pwm percentage: %f", duty); | |
331 | return SR_ERR; | |
332 | } | |
333 | ||
334 | cfg.period = (uint32_t)(PWM_CLOCK / freq); | |
335 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
336 | sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty); | |
337 | ||
c3d40037 HK |
338 | wrptr = buf; |
339 | write_u32le_inc(&wrptr, cfg.period); | |
340 | write_u32le_inc(&wrptr, cfg.duty); | |
00849545 | 341 | ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); |
f2cd2deb FS |
342 | if (ret != SR_OK) { |
343 | sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty); | |
344 | return ret; | |
345 | } | |
346 | setting = &devc->pwm_setting[which - 1]; | |
347 | setting->freq = freq; | |
348 | setting->duty = duty; | |
f2cd2deb FS |
349 | |
350 | return SR_OK; | |
351 | } | |
352 | ||
353 | static int set_defaults(const struct sr_dev_inst *sdi) | |
354 | { | |
355 | struct dev_context *devc; | |
356 | int ret; | |
357 | ||
358 | devc = sdi->priv; | |
359 | ||
360 | devc->capture_ratio = 5; /* percent */ | |
361 | devc->cur_channels = 0xffff; | |
362 | devc->limit_samples = 5000000; | |
8b172e78 | 363 | devc->cur_samplerate = SR_MHZ(100); |
f2cd2deb FS |
364 | |
365 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
366 | if (ret) | |
367 | return ret; | |
368 | ||
369 | ret = enable_pwm(sdi, 0, 0); | |
370 | if (ret) | |
371 | return ret; | |
372 | ||
373 | ret = set_pwm(sdi, 1, 1e3, 50); | |
374 | if (ret) | |
375 | return ret; | |
376 | ||
377 | ret = set_pwm(sdi, 2, 100e3, 50); | |
378 | if (ret) | |
379 | return ret; | |
380 | ||
381 | ret = enable_pwm(sdi, 1, 1); | |
382 | if (ret) | |
383 | return ret; | |
384 | ||
385 | return SR_OK; | |
386 | } | |
387 | ||
388 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
389 | { | |
390 | struct dev_context *devc; | |
391 | struct sr_trigger *trigger; | |
392 | trigger_cfg_t cfg; | |
393 | GSList *stages; | |
394 | GSList *channel; | |
395 | struct sr_trigger_stage *stage1; | |
396 | struct sr_trigger_match *match; | |
397 | uint16_t ch_mask; | |
398 | int ret; | |
c3d40037 HK |
399 | uint8_t buf[4 * sizeof(uint32_t)]; |
400 | uint8_t *wrptr; | |
f2cd2deb FS |
401 | |
402 | devc = sdi->priv; | |
403 | trigger = sr_session_trigger_get(sdi->session); | |
404 | ||
405 | memset(&cfg, 0, sizeof(cfg)); | |
406 | ||
407 | cfg.channels = devc->cur_channels; | |
408 | ||
409 | if (trigger && trigger->stages) { | |
410 | stages = trigger->stages; | |
411 | stage1 = stages->data; | |
412 | if (stages->next) { | |
413 | sr_err("Only one trigger stage supported for now."); | |
414 | return SR_ERR; | |
415 | } | |
416 | channel = stage1->matches; | |
417 | while (channel) { | |
418 | match = channel->data; | |
419 | ch_mask = 1 << match->channel->index; | |
420 | ||
421 | switch (match->match) { | |
422 | case SR_TRIGGER_ZERO: | |
423 | cfg.level |= ch_mask; | |
424 | cfg.high_or_falling &= ~ch_mask; | |
425 | break; | |
426 | case SR_TRIGGER_ONE: | |
427 | cfg.level |= ch_mask; | |
428 | cfg.high_or_falling |= ch_mask; | |
429 | break; | |
430 | case SR_TRIGGER_RISING: | |
431 | if ((cfg.enabled & ~cfg.level)) { | |
432 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
433 | return SR_ERR; | |
434 | } | |
435 | cfg.level &= ~ch_mask; | |
436 | cfg.high_or_falling &= ~ch_mask; | |
437 | break; | |
438 | case SR_TRIGGER_FALLING: | |
439 | if ((cfg.enabled & ~cfg.level)) { | |
440 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
441 | return SR_ERR; | |
442 | } | |
443 | cfg.level &= ~ch_mask; | |
444 | cfg.high_or_falling |= ch_mask; | |
445 | break; | |
446 | default: | |
447 | sr_err("Unknown trigger value."); | |
448 | return SR_ERR; | |
449 | } | |
450 | cfg.enabled |= ch_mask; | |
451 | channel = channel->next; | |
452 | } | |
453 | } | |
454 | sr_dbg("set trigger configuration channels: 0x%04x, " | |
455 | "trigger-enabled 0x%04x, level-triggered 0x%04x, " | |
456 | "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level, | |
457 | cfg.high_or_falling); | |
458 | ||
459 | devc->had_triggers_configured = cfg.enabled != 0; | |
460 | ||
c3d40037 HK |
461 | wrptr = buf; |
462 | write_u32le_inc(&wrptr, cfg.channels); | |
463 | write_u32le_inc(&wrptr, cfg.enabled); | |
464 | write_u32le_inc(&wrptr, cfg.level); | |
465 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
42f6dd55 | 466 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb FS |
467 | if (ret != SR_OK) { |
468 | sr_err("error setting trigger config!"); | |
469 | return ret; | |
470 | } | |
471 | ||
472 | return SR_OK; | |
473 | } | |
474 | ||
475 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
476 | { | |
477 | struct dev_context *devc; | |
f2cd2deb | 478 | double clock_divisor; |
f2cd2deb FS |
479 | uint64_t total; |
480 | int ret; | |
c3d40037 HK |
481 | uint16_t divisor; |
482 | uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; | |
483 | uint8_t *wrptr; | |
f2cd2deb FS |
484 | |
485 | devc = sdi->priv; | |
486 | total = 128 * 1024 * 1024; | |
487 | ||
8b172e78 | 488 | if (devc->cur_samplerate > devc->max_samplerate) { |
f2cd2deb FS |
489 | sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); |
490 | return SR_ERR; | |
491 | } | |
492 | ||
8b172e78 | 493 | clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; |
f2cd2deb FS |
494 | if (clock_divisor > 0xffff) |
495 | clock_divisor = 0xffff; | |
c3d40037 | 496 | divisor = (uint16_t)(clock_divisor + 0.5); |
8b172e78 | 497 | devc->cur_samplerate = devc->max_samplerate / divisor; |
f2cd2deb FS |
498 | |
499 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
500 | sr_err("too high sample depth: %" PRIu64, devc->limit_samples); | |
501 | return SR_ERR; | |
502 | } | |
f2cd2deb FS |
503 | |
504 | devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; | |
505 | ||
f2cd2deb | 506 | sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%", |
955ab604 | 507 | devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio); |
f2cd2deb | 508 | |
c3d40037 HK |
509 | wrptr = buf; |
510 | write_u32le_inc(&wrptr, devc->limit_samples); | |
0d8e1ffc KG |
511 | write_u8_inc(&wrptr, 0); |
512 | write_u32le_inc(&wrptr, devc->pre_trigger_size); | |
84fe94bd | 513 | write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00); |
0d8e1ffc KG |
514 | write_u16le_inc(&wrptr, divisor); |
515 | write_u8_inc(&wrptr, 0); | |
c3d40037 | 516 | |
42f6dd55 | 517 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb FS |
518 | if (ret != SR_OK) { |
519 | sr_err("error setting sample config!"); | |
520 | return ret; | |
521 | } | |
522 | ||
523 | return SR_OK; | |
524 | } | |
525 | ||
7601dca7 KG |
526 | /* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte] |
527 | * and the bits are interpreted as follows: | |
528 | * | |
529 | * register 0: | |
530 | * bit0 1= idle | |
531 | * bit1 1= writing to sdram | |
532 | * bit2 0= waiting_for_trigger 1=been_triggered | |
533 | * bit3 0= pretrigger_sampling 1=posttrigger_sampling | |
534 | * ...unknown... | |
535 | * register 1: | |
536 | * meaning of bits unknown (but vendor software reads this, so just do the same) | |
537 | * | |
538 | * The run state values occur in this order: | |
539 | * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%) | |
540 | * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously) | |
541 | * 0x85EE: running | |
542 | * 0x85ED: idle | |
f2cd2deb FS |
543 | */ |
544 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
545 | { | |
546 | uint16_t state; | |
84fe94bd | 547 | static uint16_t previous_state = 0; |
f2cd2deb FS |
548 | int ret; |
549 | ||
42f6dd55 | 550 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { |
f2cd2deb FS |
551 | sr_err("failed to read run state!"); |
552 | return ret; | |
553 | } | |
7601dca7 KG |
554 | |
555 | /* This function is called about every 50ms. | |
556 | * To avoid filling the log file with redundant information during long captures, | |
557 | * just print a log message if status has changed. | |
558 | */ | |
559 | ||
84fe94bd | 560 | if (state != previous_state) { |
7601dca7 | 561 | previous_state = state; |
84fe94bd | 562 | if ((state & 0x0003) == 0x01) { |
7601dca7 KG |
563 | sr_dbg("run_state: 0x%04x (%s)", state, "idle"); |
564 | } | |
84fe94bd | 565 | else if ((state & 0x000f) == 0x02) { |
7601dca7 KG |
566 | sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling"); |
567 | } | |
84fe94bd | 568 | else if ((state & 0x000f) == 0x0a) { |
7601dca7 KG |
569 | sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger"); |
570 | } | |
84fe94bd | 571 | else if ((state & 0x000f) == 0x0e) { |
7601dca7 KG |
572 | sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling"); |
573 | } | |
574 | else { | |
575 | sr_dbg("run_state: 0x%04x", state); | |
576 | } | |
577 | } | |
f2cd2deb FS |
578 | |
579 | return state; | |
580 | } | |
581 | ||
582 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) | |
583 | { | |
584 | int ret; | |
585 | ||
42f6dd55 | 586 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { |
f2cd2deb FS |
587 | sr_err("failed to send set-run-mode command %d", fast_blinking); |
588 | return ret; | |
589 | } | |
590 | ||
591 | return SR_OK; | |
592 | } | |
593 | ||
594 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
595 | { | |
596 | struct dev_context *devc; | |
597 | int ret; | |
c3d40037 HK |
598 | uint8_t buf[3 * sizeof(uint32_t)]; |
599 | const uint8_t *rdptr; | |
f2cd2deb FS |
600 | |
601 | devc = sdi->priv; | |
602 | ||
42f6dd55 | 603 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { |
f2cd2deb FS |
604 | sr_err("failed to read capture info!"); |
605 | return ret; | |
606 | } | |
c3d40037 HK |
607 | |
608 | rdptr = buf; | |
609 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
610 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
611 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb FS |
612 | |
613 | sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d", | |
614 | devc->info.n_rep_packets, devc->info.n_rep_packets, | |
615 | devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, | |
616 | devc->info.write_pos, devc->info.write_pos); | |
617 | ||
618 | if (devc->info.n_rep_packets % 5) | |
619 | sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets); | |
620 | ||
621 | return SR_OK; | |
622 | } | |
623 | ||
624 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
625 | { | |
626 | char fw_file[1024]; | |
627 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
40a0b2f4 | 628 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); |
f2cd2deb FS |
629 | } |
630 | ||
631 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
632 | { | |
633 | struct dev_context *devc; | |
634 | int ret; | |
635 | uint8_t cmd; | |
636 | ||
637 | devc = sdi->priv; | |
638 | ||
639 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
640 | if (ret != SR_OK) | |
641 | return ret; | |
642 | ||
643 | cmd = 0; | |
42f6dd55 | 644 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { |
f2cd2deb FS |
645 | sr_err("failed to send stop sampling command"); |
646 | return ret; | |
647 | } | |
648 | ||
649 | ret = set_trigger_config(sdi); | |
650 | if (ret != SR_OK) | |
651 | return ret; | |
652 | ||
653 | ret = set_sample_config(sdi); | |
654 | if (ret != SR_OK) | |
655 | return ret; | |
656 | ||
657 | return SR_OK; | |
658 | } | |
659 | ||
660 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
661 | { | |
662 | return set_run_mode(sdi, 3); | |
663 | } | |
664 | ||
665 | SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi) | |
666 | { | |
667 | return set_run_mode(sdi, 0); | |
668 | } | |
669 | ||
670 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
671 | { | |
672 | return la2016_stop_acquisition(sdi); | |
673 | } | |
674 | ||
675 | SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) | |
676 | { | |
677 | uint16_t state; | |
678 | ||
679 | state = run_state(sdi); | |
680 | ||
681 | return (state & 0x3) == 1; | |
682 | } | |
683 | ||
684 | SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) | |
685 | { | |
686 | struct dev_context *devc; | |
687 | struct sr_usb_dev_inst *usb; | |
688 | int ret; | |
c3d40037 HK |
689 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
690 | uint8_t *wrptr; | |
f2cd2deb FS |
691 | uint32_t to_read; |
692 | uint8_t *buffer; | |
693 | ||
694 | devc = sdi->priv; | |
695 | usb = sdi->conn; | |
696 | ||
697 | if ((ret = get_capture_info(sdi)) != SR_OK) | |
698 | return ret; | |
699 | ||
c3d40037 HK |
700 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
701 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
702 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
703 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
704 | ||
705 | sr_dbg("want to read %d tfer-packets starting from pos %d", | |
706 | devc->n_transfer_packets_to_read, devc->read_pos); | |
707 | ||
00849545 | 708 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
709 | sr_err("failed to reset bulk state"); |
710 | return ret; | |
711 | } | |
f2cd2deb | 712 | sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read); |
c3d40037 HK |
713 | wrptr = wrbuf; |
714 | write_u32le_inc(&wrptr, devc->read_pos); | |
715 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
42f6dd55 | 716 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { |
f2cd2deb FS |
717 | sr_err("failed to send bulk config"); |
718 | return ret; | |
719 | } | |
00849545 | 720 | if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
721 | sr_err("failed to unblock bulk transfers"); |
722 | return ret; | |
723 | } | |
724 | ||
725 | to_read = devc->n_bytes_to_read; | |
e847645b KG |
726 | /* choose a buffer size for all of the usb transfers */ |
727 | if (to_read >= LA2016_USB_BUFSZ) | |
728 | to_read = LA2016_USB_BUFSZ; /* multiple transfers */ | |
729 | else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */ | |
730 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); | |
f2cd2deb FS |
731 | buffer = g_try_malloc(to_read); |
732 | if (!buffer) { | |
733 | sr_err("Failed to allocate %d bytes for bulk transfer", to_read); | |
734 | return SR_ERR_MALLOC; | |
735 | } | |
736 | ||
737 | devc->transfer = libusb_alloc_transfer(0); | |
738 | libusb_fill_bulk_transfer( | |
739 | devc->transfer, usb->devhdl, | |
740 | 0x86, buffer, to_read, | |
741 | cb, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
742 | ||
743 | if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { | |
744 | sr_err("Failed to submit transfer: %s.", libusb_error_name(ret)); | |
745 | libusb_free_transfer(devc->transfer); | |
746 | devc->transfer = NULL; | |
747 | g_free(buffer); | |
748 | return SR_ERR; | |
749 | } | |
750 | ||
751 | return SR_OK; | |
752 | } | |
753 | ||
754 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) | |
755 | { | |
8b172e78 | 756 | struct dev_context *devc; |
f2cd2deb | 757 | uint16_t state; |
9de389b1 KG |
758 | uint8_t buf[8]; |
759 | int16_t purchase_date_bcd[2]; | |
760 | uint8_t magic; | |
761 | int ret; | |
f2cd2deb | 762 | |
8b172e78 KG |
763 | devc = sdi->priv; |
764 | ||
9de389b1 KG |
765 | /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit |
766 | * complemented checksum; e.g. 2004DFFB = 2020-April. | |
767 | * This helps to identify the age of devices if unknown magic numbers occur. | |
768 | */ | |
769 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { | |
770 | sr_err("failed to read eeprom purchase_date_bcd"); | |
771 | } | |
772 | else { | |
773 | sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff); | |
84fe94bd | 774 | if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { |
9de389b1 KG |
775 | sr_err("purchase date: checksum failure"); |
776 | } | |
f2cd2deb | 777 | } |
f2cd2deb | 778 | |
9de389b1 KG |
779 | /* |
780 | * There are four known kingst logic analyser devices which use this same usb vid and pid: | |
781 | * LA2016, LA1016 and the older revision of each of these. They all use the same hardware | |
782 | * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are | |
783 | * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08. | |
784 | * For example; | |
785 | * | |
786 | * magic=0x08 | |
787 | * | ~magic=0xf7 | |
788 | * | | | |
789 | * 08F7000008F710EF | |
790 | * | | | |
791 | * | ~magic-backup | |
792 | * magic-backup | |
793 | * | |
794 | * It seems that only these magic bytes are used, other bytes shown above are 'don't care'. | |
795 | * Changing the magic byte on newer device to older magic causes OEM software to load | |
796 | * the older fpga bitstream. The device then functions but has channels out of order. | |
797 | * It's likely the bitstreams were changed to move input channel pins due to PCB changes. | |
798 | * | |
799 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
800 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
801 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
802 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" | |
803 | * | |
804 | * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing | |
805 | * the vendor software actions, either raising errors or loading specific bitstreams. | |
806 | * | |
807 | * Note: | |
808 | * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream | |
809 | * will not authenticate with ic U10, which has different security coding for each device type. | |
810 | */ | |
811 | ||
812 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { | |
813 | sr_err("failed to read eeprom device identifier bytes"); | |
f2cd2deb FS |
814 | return ret; |
815 | } | |
f2cd2deb | 816 | |
9de389b1 KG |
817 | magic = 0; |
818 | if (buf[0] == (0x0ff & ~buf[1])) { | |
819 | /* primary copy of magic passes complement check */ | |
820 | magic = buf[0]; | |
821 | } | |
822 | else if (buf[4] == (0x0ff & ~buf[5])) { | |
823 | /* backup copy of magic passes complement check */ | |
824 | sr_dbg("device_type: using backup copy of magic number"); | |
825 | magic = buf[4]; | |
f2cd2deb FS |
826 | } |
827 | ||
9de389b1 KG |
828 | sr_dbg("device_type: magic number is %hhu", magic); |
829 | ||
830 | /* select the correct fpga bitstream for this device */ | |
831 | switch (magic) { | |
832 | case 2: | |
833 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); | |
8b172e78 KG |
834 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
835 | break; | |
836 | case 3: | |
837 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016); | |
838 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; | |
9de389b1 KG |
839 | break; |
840 | case 8: | |
841 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); | |
8b172e78 KG |
842 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
843 | break; | |
844 | case 9: | |
845 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A); | |
846 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; | |
9de389b1 KG |
847 | break; |
848 | default: | |
8b172e78 | 849 | sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016"); |
3f48ab02 FS |
850 | return SR_ERR; |
851 | } | |
f2cd2deb | 852 | |
9de389b1 KG |
853 | if (ret != SR_OK) { |
854 | sr_err("failed to upload fpga bitstream"); | |
855 | return ret; | |
856 | } | |
857 | ||
f2cd2deb | 858 | state = run_state(sdi); |
9de389b1 | 859 | if (state != 0x85e9) { |
f2cd2deb | 860 | sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state); |
9de389b1 | 861 | } |
f2cd2deb | 862 | |
00849545 | 863 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
bb706a76 | 864 | sr_err("failed to send CMD_BULK_RESET"); |
f2cd2deb FS |
865 | return ret; |
866 | } | |
9de389b1 | 867 | |
f2cd2deb FS |
868 | sr_dbg("device should be initialized"); |
869 | ||
870 | return set_defaults(sdi); | |
871 | } | |
872 | ||
873 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
874 | { | |
875 | int ret; | |
876 | ||
00849545 | 877 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
878 | sr_err("failed to send deinit command"); |
879 | return ret; | |
880 | } | |
881 | ||
882 | return SR_OK; | |
883 | } |