]>
Commit | Line | Data |
---|---|---|
b9d53092 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
6fcf3f0a | 21 | #ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H |
22 | #define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H | |
23 | ||
b9d53092 BV |
24 | /* Modified protocol commands & flags used by DSLogic */ |
25 | #define DS_CMD_GET_FW_VERSION 0xb0 | |
26 | #define DS_CMD_GET_REVID_VERSION 0xb1 | |
6fcf3f0a | 27 | #define DS_CMD_START 0xb2 |
28 | #define DS_CMD_FPGA_FW 0xb3 | |
29 | #define DS_CMD_CONFIG 0xb4 | |
9803346f | 30 | #define DS_CMD_VTH 0xb8 |
b9d53092 | 31 | |
6fcf3f0a | 32 | #define DS_NUM_TRIGGER_STAGES 16 |
33 | #define DS_START_FLAGS_STOP (1 << 7) | |
34 | #define DS_START_FLAGS_CLK_48MHZ (1 << 6) | |
35 | #define DS_START_FLAGS_SAMPLE_WIDE (1 << 5) | |
62974b23 | 36 | #define DS_START_FLAGS_MODE_LA (1 << 4) |
b9d53092 | 37 | |
9803346f UH |
38 | #define DS_MAX_LOGIC_DEPTH SR_MHZ(16) |
39 | #define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100) | |
a9a9bfaa | 40 | |
b9d53092 BV |
41 | enum dslogic_operation_modes { |
42 | DS_OP_NORMAL, | |
43 | DS_OP_INTERNAL_TEST, | |
44 | DS_OP_EXTERNAL_TEST, | |
45 | DS_OP_LOOPBACK_TEST, | |
46 | }; | |
47 | ||
9803346f UH |
48 | enum { |
49 | DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */ | |
50 | DS_VOLTAGE_RANGE_5_V, /* 5V logic */ | |
3fc3fbe4 DA |
51 | }; |
52 | ||
9803346f | 53 | enum { |
d9a58763 | 54 | DS_EDGE_RISING, |
9803346f | 55 | DS_EDGE_FALLING, |
d9a58763 DA |
56 | }; |
57 | ||
b9d53092 BV |
58 | struct dslogic_version { |
59 | uint8_t major; | |
60 | uint8_t minor; | |
61 | }; | |
62 | ||
63 | struct dslogic_mode { | |
64 | uint8_t flags; | |
65 | uint8_t sample_delay_h; | |
66 | uint8_t sample_delay_l; | |
67 | }; | |
68 | ||
69 | struct dslogic_trigger_pos { | |
70 | uint32_t real_pos; | |
71 | uint32_t ram_saddr; | |
4237fbca DA |
72 | uint32_t remain_cnt; |
73 | uint8_t first_block[500]; | |
b9d53092 BV |
74 | }; |
75 | ||
76 | /* | |
77 | * The FPGA is configured with TLV tuples. Length is specified as the | |
78 | * number of 16-bit words, and the (type, length) header is in some | |
79 | * cases padded with 0xffff. | |
80 | */ | |
81 | #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt) | |
82 | #define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff) | |
3f0ff412 | 83 | #define DS_CFG_START 0xf5a5f5a5 |
6fcf3f0a | 84 | #define DS_CFG_MODE _DS_CFG(0, 1) |
b9d53092 BV |
85 | #define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2) |
86 | #define DS_CFG_COUNT _DS_CFG_PAD(3, 2) | |
87 | #define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2) | |
88 | #define DS_CFG_TRIG_GLB _DS_CFG(7, 1) | |
89 | #define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2) | |
90 | #define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2) | |
91 | #define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16) | |
92 | #define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16) | |
93 | #define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16) | |
94 | #define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16) | |
95 | #define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16) | |
96 | #define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16) | |
97 | #define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16) | |
98 | #define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16) | |
99 | #define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16) | |
100 | #define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16) | |
3f0ff412 | 101 | #define DS_CFG_END 0xfa5afa5a |
b9d53092 BV |
102 | |
103 | struct dslogic_fpga_config { | |
104 | uint32_t sync; | |
105 | uint16_t mode_header; | |
106 | uint16_t mode; | |
107 | uint32_t divider_header; | |
108 | uint32_t divider; | |
109 | uint32_t count_header; | |
110 | uint32_t count; | |
111 | uint32_t trig_pos_header; | |
112 | uint32_t trig_pos; | |
113 | uint16_t trig_glb_header; | |
114 | uint16_t trig_glb; | |
115 | uint32_t trig_adp_header; | |
116 | uint32_t trig_adp; | |
117 | uint32_t trig_sda_header; | |
118 | uint32_t trig_sda; | |
119 | uint32_t trig_mask0_header; | |
120 | uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES]; | |
121 | uint32_t trig_mask1_header; | |
122 | uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES]; | |
123 | uint32_t trig_value0_header; | |
124 | uint16_t trig_value0[DS_NUM_TRIGGER_STAGES]; | |
125 | uint32_t trig_value1_header; | |
126 | uint16_t trig_value1[DS_NUM_TRIGGER_STAGES]; | |
127 | uint32_t trig_edge0_header; | |
128 | uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES]; | |
129 | uint32_t trig_edge1_header; | |
130 | uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES]; | |
131 | uint32_t trig_count0_header; | |
132 | uint16_t trig_count0[DS_NUM_TRIGGER_STAGES]; | |
133 | uint32_t trig_count1_header; | |
134 | uint16_t trig_count1[DS_NUM_TRIGGER_STAGES]; | |
135 | uint32_t trig_logic0_header; | |
136 | uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES]; | |
137 | uint32_t trig_logic1_header; | |
138 | uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES]; | |
139 | uint32_t end_sync; | |
140 | }; | |
141 | ||
8e2d6c9d DE |
142 | SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, |
143 | const char *name); | |
144 | SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi); | |
145 | SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi); | |
146 | SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi); | |
3fc3fbe4 | 147 | SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth); |
9803346f | 148 | SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc); |
6fcf3f0a | 149 | |
150 | #endif |