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dslogic: Fixed buffer size calculation
[libsigrok.git] / src / hardware / dslogic / protocol.c
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <config.h>
4bd770f5 22#include <math.h>
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23#include <glib.h>
24#include <glib/gstdio.h>
25#include "protocol.h"
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26
27#define DS_CMD_GET_FW_VERSION 0xb0
28#define DS_CMD_GET_REVID_VERSION 0xb1
29#define DS_CMD_START 0xb2
30#define DS_CMD_CONFIG 0xb3
31#define DS_CMD_SETTING 0xb4
32#define DS_CMD_CONTROL 0xb5
33#define DS_CMD_STATUS 0xb6
34#define DS_CMD_STATUS_INFO 0xb7
35#define DS_CMD_WR_REG 0xb8
36#define DS_CMD_WR_NVM 0xb9
37#define DS_CMD_RD_NVM 0xba
38#define DS_CMD_RD_NVM_PRE 0xbb
39#define DS_CMD_GET_HW_INFO 0xbc
40
41#define DS_START_FLAGS_STOP (1 << 7)
42#define DS_START_FLAGS_CLK_48MHZ (1 << 6)
43#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
44#define DS_START_FLAGS_MODE_LA (1 << 4)
45
46#define DS_ADDR_COMB 0x68
47#define DS_ADDR_EEWP 0x70
48#define DS_ADDR_VTH 0x78
49
50#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
51#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
52#define DS_MAX_TRIG_PERCENT 90
53
54#define DS_MODE_TRIG_EN (1 << 0)
55#define DS_MODE_CLK_TYPE (1 << 1)
56#define DS_MODE_CLK_EDGE (1 << 2)
57#define DS_MODE_RLE_MODE (1 << 3)
58#define DS_MODE_DSO_MODE (1 << 4)
59#define DS_MODE_HALF_MODE (1 << 5)
60#define DS_MODE_QUAR_MODE (1 << 6)
61#define DS_MODE_ANALOG_MODE (1 << 7)
62#define DS_MODE_FILTER (1 << 8)
63#define DS_MODE_INSTANT (1 << 9)
64#define DS_MODE_STRIG_MODE (1 << 11)
65#define DS_MODE_STREAM_MODE (1 << 12)
66#define DS_MODE_LPB_TEST (1 << 13)
67#define DS_MODE_EXT_TEST (1 << 14)
68#define DS_MODE_INT_TEST (1 << 15)
69
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70#define DSLOGIC_ATOMIC_SAMPLES (sizeof(uint64_t) * 8)
71#define DSLOGIC_ATOMIC_BYTES sizeof(uint64_t)
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72
73/*
74 * The FPGA is configured with TLV tuples. Length is specified as the
75 * number of 16-bit words.
76 */
77#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
78#define DS_CFG_START 0xf5a5f5a5
79#define DS_CFG_MODE _DS_CFG(0, 1)
80#define DS_CFG_DIVIDER _DS_CFG(1, 2)
81#define DS_CFG_COUNT _DS_CFG(3, 2)
82#define DS_CFG_TRIG_POS _DS_CFG(5, 2)
83#define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
84#define DS_CFG_CH_EN _DS_CFG(8, 1)
85#define DS_CFG_TRIG _DS_CFG(64, 160)
86#define DS_CFG_END 0xfa5afa5a
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87
88#pragma pack(push, 1)
89
90struct version_info {
91 uint8_t major;
92 uint8_t minor;
93};
94
95struct cmd_start_acquisition {
96 uint8_t flags;
97 uint8_t sample_delay_h;
98 uint8_t sample_delay_l;
99};
100
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101struct dslogic_fpga_config {
102 uint32_t sync;
103
104 uint16_t mode_header;
105 uint16_t mode;
106 uint16_t divider_header;
107 uint32_t divider;
108 uint16_t count_header;
109 uint32_t count;
110 uint16_t trig_pos_header;
111 uint32_t trig_pos;
112 uint16_t trig_glb_header;
113 uint16_t trig_glb;
114 uint16_t ch_en_header;
115 uint16_t ch_en;
116
117 uint16_t trig_header;
118 uint16_t trig_mask0[NUM_TRIGGER_STAGES];
119 uint16_t trig_mask1[NUM_TRIGGER_STAGES];
120 uint16_t trig_value0[NUM_TRIGGER_STAGES];
121 uint16_t trig_value1[NUM_TRIGGER_STAGES];
122 uint16_t trig_edge0[NUM_TRIGGER_STAGES];
123 uint16_t trig_edge1[NUM_TRIGGER_STAGES];
124 uint16_t trig_logic0[NUM_TRIGGER_STAGES];
125 uint16_t trig_logic1[NUM_TRIGGER_STAGES];
126 uint32_t trig_count[NUM_TRIGGER_STAGES];
127
128 uint32_t end_sync;
129};
130
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131#pragma pack(pop)
132
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133/*
134 * This should be larger than the FPGA bitstream image so that it'll get
135 * uploaded in one big operation. There seem to be issues when uploading
136 * it in chunks.
137 */
138#define FW_BUFSIZE (1024 * 1024)
139
140#define FPGA_UPLOAD_DELAY (10 * 1000)
141
142#define USB_TIMEOUT (3 * 1000)
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143
144static int command_get_fw_version(libusb_device_handle *devhdl,
145 struct version_info *vi)
146{
147 int ret;
148
149 ret = libusb_control_transfer(devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
150 LIBUSB_ENDPOINT_IN, DS_CMD_GET_FW_VERSION, 0x0000, 0x0000,
151 (unsigned char *)vi, sizeof(struct version_info), USB_TIMEOUT);
152
153 if (ret < 0) {
154 sr_err("Unable to get version info: %s.",
155 libusb_error_name(ret));
156 return SR_ERR;
157 }
158
159 return SR_OK;
160}
161
162static int command_get_revid_version(struct sr_dev_inst *sdi, uint8_t *revid)
163{
164 struct sr_usb_dev_inst *usb = sdi->conn;
165 libusb_device_handle *devhdl = usb->devhdl;
166 int ret;
167
168 ret = libusb_control_transfer(devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
169 LIBUSB_ENDPOINT_IN, DS_CMD_GET_REVID_VERSION, 0x0000, 0x0000,
170 revid, 1, USB_TIMEOUT);
171
172 if (ret < 0) {
173 sr_err("Unable to get REVID: %s.", libusb_error_name(ret));
174 return SR_ERR;
175 }
176
177 return SR_OK;
178}
179
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180static int command_start_acquisition(const struct sr_dev_inst *sdi)
181{
182 struct sr_usb_dev_inst *usb;
183 struct dslogic_mode mode;
184 int ret;
185
186 mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
187 mode.sample_delay_h = mode.sample_delay_l = 0;
188
189 usb = sdi->conn;
190 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
191 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
192 (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
193 if (ret < 0) {
194 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
195 return SR_ERR;
196 }
197
198 return SR_OK;
199}
200
201static int command_stop_acquisition(const struct sr_dev_inst *sdi)
202{
203 struct sr_usb_dev_inst *usb;
204 struct dslogic_mode mode;
205 int ret;
206
207 mode.flags = DS_START_FLAGS_STOP;
208 mode.sample_delay_h = mode.sample_delay_l = 0;
209
210 usb = sdi->conn;
211 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
212 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
213 (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
214 if (ret < 0) {
215 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
216 return SR_ERR;
217 }
218
219 return SR_OK;
220}
221
222SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
223{
224 const char *name = NULL;
225 uint64_t sum;
226 struct sr_resource bitstream;
227 struct drv_context *drvc;
228 struct dev_context *devc;
229 struct sr_usb_dev_inst *usb;
230 unsigned char *buf;
231 ssize_t chunksize;
232 int transferred;
233 int result, ret;
234 const uint8_t cmd[3] = {0, 0, 0};
235
236 drvc = sdi->driver->context;
237 devc = sdi->priv;
238 usb = sdi->conn;
239
240 if (!strcmp(devc->profile->model, "DSLogic")) {
241 if (devc->cur_threshold < 1.40)
242 name = DSLOGIC_FPGA_FIRMWARE_3V3;
243 else
244 name = DSLOGIC_FPGA_FIRMWARE_5V;
245 } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
246 name = DSLOGIC_PRO_FPGA_FIRMWARE;
247 } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
248 name = DSLOGIC_PLUS_FPGA_FIRMWARE;
249 } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
250 name = DSLOGIC_BASIC_FPGA_FIRMWARE;
251 } else if (!strcmp(devc->profile->model, "DSCope")) {
252 name = DSCOPE_FPGA_FIRMWARE;
253 } else {
254 sr_err("Failed to select FPGA firmware.");
255 return SR_ERR;
256 }
257
258 sr_dbg("Uploading FPGA firmware '%s'.", name);
259
260 result = sr_resource_open(drvc->sr_ctx, &bitstream,
261 SR_RESOURCE_FIRMWARE, name);
262 if (result != SR_OK)
263 return result;
264
265 /* Tell the device firmware is coming. */
266 if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
267 LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
268 (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
269 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
270 sr_resource_close(drvc->sr_ctx, &bitstream);
271 return SR_ERR;
272 }
273
274 /* Give the FX2 time to get ready for FPGA firmware upload. */
275 g_usleep(FPGA_UPLOAD_DELAY);
276
277 buf = g_malloc(FW_BUFSIZE);
278 sum = 0;
279 result = SR_OK;
280 while (1) {
281 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
282 buf, FW_BUFSIZE);
283 if (chunksize < 0)
284 result = SR_ERR;
285 if (chunksize <= 0)
286 break;
287
288 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
289 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
290 sr_err("Unable to configure FPGA firmware: %s.",
291 libusb_error_name(ret));
292 result = SR_ERR;
293 break;
294 }
295 sum += transferred;
296 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
297 sum, bitstream.size);
298
299 if (transferred != chunksize) {
300 sr_err("Short transfer while uploading FPGA firmware.");
301 result = SR_ERR;
302 break;
303 }
304 }
305 g_free(buf);
306 sr_resource_close(drvc->sr_ctx, &bitstream);
307
308 if (result == SR_OK)
309 sr_dbg("FPGA firmware upload done.");
310
311 return result;
312}
313
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314static unsigned int enabled_channel_count(const struct sr_dev_inst *sdi)
315{
316 unsigned int count = 0;
317 for (const GSList *l = sdi->channels; l; l = l->next) {
318 const struct sr_channel *const probe = (struct sr_channel *)l->data;
319 if (probe->enabled)
320 count++;
321 }
322 return count;
323}
324
325static uint16_t enabled_channel_mask(const struct sr_dev_inst *sdi)
326{
327 unsigned int mask = 0;
328 for (const GSList *l = sdi->channels; l; l = l->next) {
329 const struct sr_channel *const probe = (struct sr_channel *)l->data;
330 if (probe->enabled)
331 mask |= 1 << probe->index;
332 }
333 return mask;
334}
335
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336/*
337 * Get the session trigger and configure the FPGA structure
338 * accordingly.
339 */
340static void set_trigger(const struct sr_dev_inst *sdi,
341 struct dslogic_fpga_config *cfg)
342{
343 struct sr_trigger *trigger;
344 struct sr_trigger_stage *stage;
345 struct sr_trigger_match *match;
346 struct dev_context *devc;
347 const GSList *l, *m;
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348 const unsigned int num_enabled_channels = enabled_channel_count(sdi);
349 int num_trigger_stages = 0;
350
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351 int channelbit, i = 0;
352 uint32_t trigger_point;
353
354 devc = sdi->priv;
355
6dfa2c39 356 cfg->ch_en = enabled_channel_mask(sdi);
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357
358 cfg->trig_mask0[0] = 0xffff;
359 cfg->trig_mask1[0] = 0xffff;
360
361 cfg->trig_value0[0] = 0;
362 cfg->trig_value1[0] = 0;
363
364 cfg->trig_edge0[0] = 0;
365 cfg->trig_edge1[0] = 0;
366
367 cfg->trig_logic0[0] = 2;
368 cfg->trig_logic1[0] = 2;
369
370 cfg->trig_count[0] = 0;
371
372 cfg->trig_glb = num_enabled_channels << 4;
373
374 for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
375 cfg->trig_mask0[i] = 0xffff;
376 cfg->trig_mask1[i] = 0xffff;
377 cfg->trig_value0[i] = 0;
378 cfg->trig_value1[i] = 0;
379 cfg->trig_edge0[i] = 0;
380 cfg->trig_edge1[i] = 0;
381 cfg->trig_logic0[i] = 2;
382 cfg->trig_logic1[i] = 2;
383 cfg->trig_count[i] = 0;
384 }
385
386 trigger_point = (devc->capture_ratio * devc->limit_samples) / 100;
387 if (trigger_point < DSLOGIC_ATOMIC_SAMPLES)
388 trigger_point = DSLOGIC_ATOMIC_SAMPLES;
389 const uint32_t mem_depth = devc->profile->mem_depth;
390 const uint32_t max_trigger_point = devc->continuous_mode ? ((mem_depth * 10) / 100) :
391 ((mem_depth * DS_MAX_TRIG_PERCENT) / 100);
392 if (trigger_point > max_trigger_point)
393 trigger_point = max_trigger_point;
394 cfg->trig_pos = trigger_point & ~(DSLOGIC_ATOMIC_SAMPLES - 1);
395
396 if (!(trigger = sr_session_trigger_get(sdi->session))) {
397 sr_dbg("No session trigger found");
398 return;
399 }
400
401 for (l = trigger->stages; l; l = l->next) {
402 stage = l->data;
403 num_trigger_stages++;
404 for (m = stage->matches; m; m = m->next) {
405 match = m->data;
406 if (!match->channel->enabled)
407 /* Ignore disabled channels with a trigger. */
408 continue;
409 channelbit = 1 << (match->channel->index);
410 /* Simple trigger support (event). */
411 if (match->match == SR_TRIGGER_ONE) {
412 cfg->trig_mask0[0] &= ~channelbit;
413 cfg->trig_mask1[0] &= ~channelbit;
414 cfg->trig_value0[0] |= channelbit;
415 cfg->trig_value1[0] |= channelbit;
416 } else if (match->match == SR_TRIGGER_ZERO) {
417 cfg->trig_mask0[0] &= ~channelbit;
418 cfg->trig_mask1[0] &= ~channelbit;
419 } else if (match->match == SR_TRIGGER_FALLING) {
420 cfg->trig_mask0[0] &= ~channelbit;
421 cfg->trig_mask1[0] &= ~channelbit;
422 cfg->trig_edge0[0] |= channelbit;
423 cfg->trig_edge1[0] |= channelbit;
424 } else if (match->match == SR_TRIGGER_RISING) {
425 cfg->trig_mask0[0] &= ~channelbit;
426 cfg->trig_mask1[0] &= ~channelbit;
427 cfg->trig_value0[0] |= channelbit;
428 cfg->trig_value1[0] |= channelbit;
429 cfg->trig_edge0[0] |= channelbit;
430 cfg->trig_edge1[0] |= channelbit;
431 } else if (match->match == SR_TRIGGER_EDGE) {
432 cfg->trig_edge0[0] |= channelbit;
433 cfg->trig_edge1[0] |= channelbit;
434 }
435 }
436 }
437
438 cfg->trig_glb |= num_trigger_stages;
439
440 return;
441}
442
443static int fpga_configure(const struct sr_dev_inst *sdi)
444{
445 struct dev_context *devc;
446 struct sr_usb_dev_inst *usb;
447 uint8_t c[3];
448 struct dslogic_fpga_config cfg;
449 uint16_t v16;
450 uint32_t v32;
451 int transferred, len, ret;
452
453 sr_dbg("Configuring FPGA.");
454
455 usb = sdi->conn;
456 devc = sdi->priv;
457
458 WL32(&cfg.sync, DS_CFG_START);
459 WL16(&cfg.mode_header, DS_CFG_MODE);
460 WL16(&cfg.divider_header, DS_CFG_DIVIDER);
461 WL16(&cfg.count_header, DS_CFG_COUNT);
462 WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
463 WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
464 WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
465 WL16(&cfg.trig_header, DS_CFG_TRIG);
466 WL32(&cfg.end_sync, DS_CFG_END);
467
468 /* Pass in the length of a fixed-size struct. Really. */
469 len = sizeof(struct dslogic_fpga_config) / 2;
470 c[0] = len & 0xff;
471 c[1] = (len >> 8) & 0xff;
472 c[2] = (len >> 16) & 0xff;
473
474 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
475 LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
476 c, sizeof(c), USB_TIMEOUT);
477 if (ret < 0) {
478 sr_err("Failed to send FPGA configure command: %s.",
479 libusb_error_name(ret));
480 return SR_ERR;
481 }
482
483 v16 = 0x0000;
484
485 if (devc->mode == DS_OP_INTERNAL_TEST)
486 v16 = DS_MODE_INT_TEST;
487 else if (devc->mode == DS_OP_EXTERNAL_TEST)
488 v16 = DS_MODE_EXT_TEST;
489 else if (devc->mode == DS_OP_LOOPBACK_TEST)
490 v16 = DS_MODE_LPB_TEST;
491
492 if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
493 v16 |= DS_MODE_HALF_MODE;
494 else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
495 v16 |= DS_MODE_QUAR_MODE;
496
497 if (devc->continuous_mode)
498 v16 |= DS_MODE_STREAM_MODE;
499 if (devc->external_clock) {
500 v16 |= DS_MODE_CLK_TYPE;
501 if (devc->clock_edge == DS_EDGE_FALLING)
502 v16 |= DS_MODE_CLK_EDGE;
503 }
504 if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
505 ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
506 && !devc->continuous_mode) {
507 /* Enable RLE for long captures.
508 * Without this, captured data present errors.
509 */
510 v16 |= DS_MODE_RLE_MODE;
511 }
512
513 WL16(&cfg.mode, v16);
514 v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
515 WL32(&cfg.divider, v32);
516
517 /* Number of 16-sample units. */
518 WL32(&cfg.count, devc->limit_samples / 16);
519
520 set_trigger(sdi, &cfg);
521
522 len = sizeof(struct dslogic_fpga_config);
523 ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
524 (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
525 if (ret < 0 || transferred != len) {
526 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
527 return SR_ERR;
528 }
529
530 return SR_OK;
531}
532
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533SR_PRIV int dslogic_set_voltage_threshold(const struct sr_dev_inst *sdi, double threshold)
534{
535 int ret;
536 struct dev_context *const devc = sdi->priv;
537 const struct sr_usb_dev_inst *const usb = sdi->conn;
538 const uint8_t value = (threshold / 5.0) * 255;
539 const uint16_t cmd = value | (DS_ADDR_VTH << 8);
540
541 /* Send the control command. */
542 ret = libusb_control_transfer(usb->devhdl,
543 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
544 DS_CMD_WR_REG, 0x0000, 0x0000,
545 (unsigned char *)&cmd, sizeof(cmd), 3000);
546 if (ret < 0) {
547 sr_err("Unable to set voltage-threshold register: %s.",
548 libusb_error_name(ret));
549 return SR_ERR;
550 }
551
552 devc->cur_threshold = threshold;
553
554 return SR_OK;
555}
556
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557SR_PRIV int dslogic_dev_open(struct sr_dev_inst *sdi, struct sr_dev_driver *di)
558{
559 libusb_device **devlist;
560 struct sr_usb_dev_inst *usb;
561 struct libusb_device_descriptor des;
562 struct dev_context *devc;
563 struct drv_context *drvc;
564 struct version_info vi;
565 int ret, i, device_count;
566 uint8_t revid;
567 char connection_id[64];
568
569 drvc = di->context;
570 devc = sdi->priv;
571 usb = sdi->conn;
572
573 if (sdi->status == SR_ST_ACTIVE)
574 /* Device is already in use. */
575 return SR_ERR;
576
577 device_count = libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
578 if (device_count < 0) {
579 sr_err("Failed to get device list: %s.",
580 libusb_error_name(device_count));
581 return SR_ERR;
582 }
583
584 for (i = 0; i < device_count; i++) {
585 libusb_get_device_descriptor(devlist[i], &des);
586
587 if (des.idVendor != devc->profile->vid
588 || des.idProduct != devc->profile->pid)
589 continue;
590
591 if ((sdi->status == SR_ST_INITIALIZING) ||
592 (sdi->status == SR_ST_INACTIVE)) {
593 /*
594 * Check device by its physical USB bus/port address.
595 */
596 usb_get_port_path(devlist[i], connection_id, sizeof(connection_id));
597 if (strcmp(sdi->connection_id, connection_id))
598 /* This is not the one. */
599 continue;
600 }
601
602 if (!(ret = libusb_open(devlist[i], &usb->devhdl))) {
603 if (usb->address == 0xff)
604 /*
605 * First time we touch this device after FW
606 * upload, so we don't know the address yet.
607 */
608 usb->address = libusb_get_device_address(devlist[i]);
609 } else {
610 sr_err("Failed to open device: %s.",
611 libusb_error_name(ret));
612 break;
613 }
614
615 if (libusb_has_capability(LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER)) {
616 if (libusb_kernel_driver_active(usb->devhdl, USB_INTERFACE) == 1) {
617 if ((ret = libusb_detach_kernel_driver(usb->devhdl, USB_INTERFACE)) < 0) {
618 sr_err("Failed to detach kernel driver: %s.",
619 libusb_error_name(ret));
620 return SR_ERR;
621 }
622 }
623 }
624
625 ret = command_get_fw_version(usb->devhdl, &vi);
626 if (ret != SR_OK) {
627 sr_err("Failed to get firmware version.");
628 break;
629 }
630
631 ret = command_get_revid_version(sdi, &revid);
632 if (ret != SR_OK) {
633 sr_err("Failed to get REVID.");
634 break;
635 }
636
637 /*
638 * Changes in major version mean incompatible/API changes, so
639 * bail out if we encounter an incompatible version.
640 * Different minor versions are OK, they should be compatible.
641 */
642 if (vi.major != DSLOGIC_REQUIRED_VERSION_MAJOR) {
643 sr_err("Expected firmware version %d.x, "
644 "got %d.%d.", DSLOGIC_REQUIRED_VERSION_MAJOR,
645 vi.major, vi.minor);
646 break;
647 }
648
649 sdi->status = SR_ST_ACTIVE;
650 sr_info("Opened device on %d.%d (logical) / %s (physical), "
651 "interface %d, firmware %d.%d.",
652 usb->bus, usb->address, connection_id,
653 USB_INTERFACE, vi.major, vi.minor);
654
655 sr_info("Detected REVID=%d, it's a Cypress CY7C68013%s.",
656 revid, (revid != 1) ? " (FX2)" : "A (FX2LP)");
657
658 break;
659 }
660 libusb_free_device_list(devlist, 1);
661
662 if (sdi->status != SR_ST_ACTIVE)
663 return SR_ERR;
664
665 return SR_OK;
666}
667
668SR_PRIV struct dev_context *dslogic_dev_new(void)
669{
670 struct dev_context *devc;
671
672 devc = g_malloc0(sizeof(struct dev_context));
673 devc->profile = NULL;
674 devc->fw_updated = 0;
675 devc->cur_samplerate = 0;
676 devc->limit_samples = 0;
677 devc->capture_ratio = 0;
678 devc->continuous_mode = FALSE;
679 devc->clock_edge = DS_EDGE_RISING;
680
681 return devc;
682}
683
4bd770f5 684static void abort_acquisition(struct dev_context *devc)
adcb9951
JH
685{
686 int i;
687
688 devc->acq_aborted = TRUE;
689
690 for (i = devc->num_transfers - 1; i >= 0; i--) {
691 if (devc->transfers[i])
692 libusb_cancel_transfer(devc->transfers[i]);
693 }
694}
695
696static void finish_acquisition(struct sr_dev_inst *sdi)
697{
698 struct dev_context *devc;
699
700 devc = sdi->priv;
701
702 std_session_send_df_end(sdi);
703
704 usb_source_remove(sdi->session, devc->ctx);
705
706 devc->num_transfers = 0;
707 g_free(devc->transfers);
708}
709
710static void free_transfer(struct libusb_transfer *transfer)
711{
712 struct sr_dev_inst *sdi;
713 struct dev_context *devc;
714 unsigned int i;
715
716 sdi = transfer->user_data;
717 devc = sdi->priv;
718
719 g_free(transfer->buffer);
720 transfer->buffer = NULL;
721 libusb_free_transfer(transfer);
722
723 for (i = 0; i < devc->num_transfers; i++) {
724 if (devc->transfers[i] == transfer) {
725 devc->transfers[i] = NULL;
726 break;
727 }
728 }
729
730 devc->submitted_transfers--;
731 if (devc->submitted_transfers == 0)
732 finish_acquisition(sdi);
733}
734
735static void resubmit_transfer(struct libusb_transfer *transfer)
736{
737 int ret;
738
739 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
740 return;
741
742 sr_err("%s: %s", __func__, libusb_error_name(ret));
743 free_transfer(transfer);
744
745}
746
4bd770f5 747static void send_data(struct sr_dev_inst *sdi,
adcb9951
JH
748 uint8_t *data, size_t length, size_t sample_width)
749{
750 const struct sr_datafeed_logic logic = {
751 .length = length,
752 .unitsize = sample_width,
753 .data = data
754 };
755
756 const struct sr_datafeed_packet packet = {
757 .type = SR_DF_LOGIC,
758 .payload = &logic
759 };
760
761 sr_session_send(sdi, &packet);
762}
763
4bd770f5 764static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
adcb9951
JH
765{
766 struct sr_dev_inst *sdi;
767 struct dev_context *devc;
768 gboolean packet_has_error = FALSE;
769 struct sr_datafeed_packet packet;
770 unsigned int num_samples;
771 int trigger_offset, cur_sample_count;
772 const int unitsize = 2;
773
774 sdi = transfer->user_data;
775 devc = sdi->priv;
776
777 /*
778 * If acquisition has already ended, just free any queued up
779 * transfer that come in.
780 */
781 if (devc->acq_aborted) {
782 free_transfer(transfer);
783 return;
784 }
785
786 sr_dbg("receive_transfer(): status %s received %d bytes.",
787 libusb_error_name(transfer->status), transfer->actual_length);
788
789 /* Save incoming transfer before reusing the transfer struct. */
790 cur_sample_count = transfer->actual_length / unitsize;
791
792 switch (transfer->status) {
793 case LIBUSB_TRANSFER_NO_DEVICE:
4bd770f5 794 abort_acquisition(devc);
adcb9951
JH
795 free_transfer(transfer);
796 return;
797 case LIBUSB_TRANSFER_COMPLETED:
798 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
799 break;
800 default:
801 packet_has_error = TRUE;
802 break;
803 }
804
805 if (transfer->actual_length == 0 || packet_has_error) {
806 devc->empty_transfer_count++;
807 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
808 /*
809 * The FX2 gave up. End the acquisition, the frontend
810 * will work out that the samplecount is short.
811 */
4bd770f5 812 abort_acquisition(devc);
adcb9951
JH
813 free_transfer(transfer);
814 } else {
815 resubmit_transfer(transfer);
816 }
817 return;
818 } else {
819 devc->empty_transfer_count = 0;
820 }
5e7e327a
JH
821
822 if (!devc->limit_samples || devc->sent_samples < devc->limit_samples) {
823 /* Send the incoming transfer to the session bus. */
824 if (devc->limit_samples && devc->sent_samples + cur_sample_count > devc->limit_samples)
825 num_samples = devc->limit_samples - devc->sent_samples;
826 else
827 num_samples = cur_sample_count;
828
829 if (devc->trigger_pos > devc->sent_samples
830 && devc->trigger_pos <= devc->sent_samples + num_samples) {
831 /* DSLogic trigger in this block. Send trigger position. */
832 trigger_offset = devc->trigger_pos - devc->sent_samples;
833 /* Pre-trigger samples. */
834 send_data(sdi, (uint8_t *)transfer->buffer,
835 trigger_offset * unitsize, unitsize);
836 devc->sent_samples += trigger_offset;
837 /* Trigger position. */
838 devc->trigger_pos = 0;
839 packet.type = SR_DF_TRIGGER;
840 packet.payload = NULL;
841 sr_session_send(sdi, &packet);
842 /* Post trigger samples. */
843 num_samples -= trigger_offset;
844 send_data(sdi, (uint8_t *)transfer->buffer
845 + trigger_offset * unitsize, num_samples * unitsize, unitsize);
846 devc->sent_samples += num_samples;
847 } else {
848 send_data(sdi, (uint8_t *)transfer->buffer,
849 num_samples * unitsize, unitsize);
850 devc->sent_samples += num_samples;
adcb9951
JH
851 }
852 }
853
854 if (devc->limit_samples && devc->sent_samples >= devc->limit_samples) {
4bd770f5 855 abort_acquisition(devc);
adcb9951
JH
856 free_transfer(transfer);
857 } else
858 resubmit_transfer(transfer);
859}
860
4bd770f5 861static int receive_data(int fd, int revents, void *cb_data)
adcb9951 862{
4bd770f5
JH
863 struct timeval tv;
864 struct drv_context *drvc;
865
866 (void)fd;
867 (void)revents;
868
869 drvc = (struct drv_context *)cb_data;
870
871 tv.tv_sec = tv.tv_usec = 0;
872 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
873
874 return TRUE;
adcb9951
JH
875}
876
03a0002e 877static size_t to_bytes_per_ms(const struct sr_dev_inst *sdi)
adcb9951 878{
03a0002e
JH
879 const struct dev_context *const devc = sdi->priv;
880 const size_t ch_count = enabled_channel_count(sdi);
881
882 if (devc->continuous_mode)
883 return (devc->cur_samplerate * ch_count) / (1000 * 8);
884
885
886 /* If we're in buffered mode, the transfer rate is not so important,
887 * but we expect to get at least 10% of the high-speed USB bandwidth.
888 */
889 return 35000000 / (1000 * 10);
4bd770f5 890}
adcb9951 891
03a0002e 892static size_t get_buffer_size(const struct sr_dev_inst *sdi)
4bd770f5 893{
adcb9951
JH
894 /*
895 * The buffer should be large enough to hold 10ms of data and
03a0002e 896 * a multiple of the size of a data atom.
adcb9951 897 */
03a0002e
JH
898 const size_t block_size = enabled_channel_count(sdi) * 512;
899 const size_t s = 10 * to_bytes_per_ms(sdi);
900 return ((s + block_size - 1) / block_size) * block_size;
adcb9951
JH
901}
902
03a0002e 903static unsigned int get_number_of_transfers(const struct sr_dev_inst *sdi)
adcb9951 904{
4bd770f5 905 /* Total buffer size should be able to hold about 100ms of data. */
03a0002e
JH
906 const unsigned int s = get_buffer_size(sdi);
907 const unsigned int n = (100 * to_bytes_per_ms(sdi) + s - 1) / s;
908 return (n > NUM_SIMUL_TRANSFERS) ? NUM_SIMUL_TRANSFERS : n;
4bd770f5 909}
adcb9951 910
03a0002e 911static unsigned int get_timeout(const struct sr_dev_inst *sdi)
4bd770f5 912{
03a0002e
JH
913 const size_t total_size = get_buffer_size(sdi) *
914 get_number_of_transfers(sdi);
915 const unsigned int timeout = total_size / to_bytes_per_ms(sdi);
adcb9951
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916 return timeout + timeout / 4; /* Leave a headroom of 25% percent. */
917}
4bd770f5
JH
918
919static int start_transfers(const struct sr_dev_inst *sdi)
920{
03a0002e
JH
921 const size_t size = get_buffer_size(sdi);
922 const unsigned int num_transfers = get_number_of_transfers(sdi);
923 const unsigned int timeout = get_timeout(sdi);
924
4bd770f5
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925 struct dev_context *devc;
926 struct sr_usb_dev_inst *usb;
927 struct libusb_transfer *transfer;
03a0002e
JH
928 unsigned int i;
929 int ret;
4bd770f5 930 unsigned char *buf;
4bd770f5
JH
931
932 devc = sdi->priv;
933 usb = sdi->conn;
934
935 devc->sent_samples = 0;
936 devc->acq_aborted = FALSE;
937 devc->empty_transfer_count = 0;
4bd770f5
JH
938 devc->submitted_transfers = 0;
939
5e23d42f 940 g_free(devc->transfers);
4bd770f5
JH
941 devc->transfers = g_try_malloc0(sizeof(*devc->transfers) * num_transfers);
942 if (!devc->transfers) {
943 sr_err("USB transfers malloc failed.");
944 return SR_ERR_MALLOC;
945 }
946
4bd770f5
JH
947 devc->num_transfers = num_transfers;
948 for (i = 0; i < num_transfers; i++) {
949 if (!(buf = g_try_malloc(size))) {
950 sr_err("USB transfer buffer malloc failed.");
951 return SR_ERR_MALLOC;
952 }
953 transfer = libusb_alloc_transfer(0);
954 libusb_fill_bulk_transfer(transfer, usb->devhdl,
955 6 | LIBUSB_ENDPOINT_IN, buf, size,
956 receive_transfer, (void *)sdi, timeout);
957 sr_info("submitting transfer: %d", i);
958 if ((ret = libusb_submit_transfer(transfer)) != 0) {
959 sr_err("Failed to submit transfer: %s.",
960 libusb_error_name(ret));
961 libusb_free_transfer(transfer);
962 g_free(buf);
963 abort_acquisition(devc);
964 return SR_ERR;
965 }
966 devc->transfers[i] = transfer;
967 devc->submitted_transfers++;
968 }
969
970 std_session_send_df_header(sdi);
971
972 return SR_OK;
973}
974
975static void LIBUSB_CALL trigger_receive(struct libusb_transfer *transfer)
976{
977 const struct sr_dev_inst *sdi;
978 struct dslogic_trigger_pos *tpos;
979 struct dev_context *devc;
980
981 sdi = transfer->user_data;
982 devc = sdi->priv;
983 if (transfer->status == LIBUSB_TRANSFER_CANCELLED) {
984 sr_dbg("Trigger transfer canceled.");
985 /* Terminate session. */
986 std_session_send_df_end(sdi);
987 usb_source_remove(sdi->session, devc->ctx);
988 devc->num_transfers = 0;
989 g_free(devc->transfers);
990 } else if (transfer->status == LIBUSB_TRANSFER_COMPLETED
991 && transfer->actual_length == sizeof(struct dslogic_trigger_pos)) {
992 tpos = (struct dslogic_trigger_pos *)transfer->buffer;
993 sr_info("tpos real_pos %d ram_saddr %d cnt %d", tpos->real_pos,
994 tpos->ram_saddr, tpos->remain_cnt);
995 devc->trigger_pos = tpos->real_pos;
996 g_free(tpos);
997 start_transfers(sdi);
998 }
999 libusb_free_transfer(transfer);
1000}
1001
658caaf0 1002SR_PRIV int dslogic_acquisition_start(const struct sr_dev_inst *sdi)
4bd770f5 1003{
03a0002e
JH
1004 const unsigned int timeout = get_timeout(sdi);
1005
658caaf0
JH
1006 struct sr_dev_driver *di;
1007 struct drv_context *drvc;
1008 struct dev_context *devc;
4bd770f5 1009 struct sr_usb_dev_inst *usb;
4bd770f5 1010 struct dslogic_trigger_pos *tpos;
658caaf0 1011 struct libusb_transfer *transfer;
4bd770f5
JH
1012 int ret;
1013
658caaf0
JH
1014 if (sdi->status != SR_ST_ACTIVE)
1015 return SR_ERR_DEV_CLOSED;
1016
1017 di = sdi->driver;
1018 drvc = di->context;
4bd770f5 1019 devc = sdi->priv;
658caaf0
JH
1020 usb = sdi->conn;
1021
1022 devc->ctx = drvc->sr_ctx;
1023 devc->sent_samples = 0;
1024 devc->empty_transfer_count = 0;
1025 devc->acq_aborted = FALSE;
1026
658caaf0 1027 usb_source_add(sdi->session, devc->ctx, timeout, receive_data, drvc);
4bd770f5
JH
1028
1029 if ((ret = command_stop_acquisition(sdi)) != SR_OK)
1030 return ret;
1031
1032 if ((ret = fpga_configure(sdi)) != SR_OK)
1033 return ret;
1034
1035 if ((ret = command_start_acquisition(sdi)) != SR_OK)
1036 return ret;
1037
1038 sr_dbg("Getting trigger.");
1039 tpos = g_malloc(sizeof(struct dslogic_trigger_pos));
1040 transfer = libusb_alloc_transfer(0);
1041 libusb_fill_bulk_transfer(transfer, usb->devhdl, 6 | LIBUSB_ENDPOINT_IN,
1042 (unsigned char *)tpos, sizeof(struct dslogic_trigger_pos),
1043 trigger_receive, (void *)sdi, 0);
1044 if ((ret = libusb_submit_transfer(transfer)) < 0) {
1045 sr_err("Failed to request trigger: %s.", libusb_error_name(ret));
1046 libusb_free_transfer(transfer);
1047 g_free(tpos);
1048 return SR_ERR;
1049 }
1050
1051 devc->transfers = g_try_malloc0(sizeof(*devc->transfers));
1052 if (!devc->transfers) {
1053 sr_err("USB trigger_pos transfer malloc failed.");
1054 return SR_ERR_MALLOC;
1055 }
1056 devc->num_transfers = 1;
1057 devc->submitted_transfers++;
1058 devc->transfers[0] = transfer;
1059
1060 return ret;
1061}
1062
4bd770f5
JH
1063SR_PRIV int dslogic_acquisition_stop(struct sr_dev_inst *sdi)
1064{
1065 command_stop_acquisition(sdi);
1066 abort_acquisition(sdi->priv);
1067 return SR_OK;
1068}