[libsigrok.git] / src / hardware / dslogic / dslogic.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_DSLOGIC_DSLOGIC_H
#define LIBSIGROK_HARDWARE_DSLOGIC_DSLOGIC_H

/* Modified protocol commands & flags used by DSLogic */
#define DS_CMD_GET_FW_VERSION		0xb0
#define DS_CMD_GET_REVID_VERSION	0xb1
#define DS_CMD_START			0xb2
#define DS_CMD_CONFIG			0xb3
#define DS_CMD_SETTING			0xb4
#define DS_CMD_CONTROL			0xb5
#define DS_CMD_STATUS			0xb6
#define DS_CMD_STATUS_INFO		0xb7
#define DS_CMD_WR_REG			0xb8
#define DS_CMD_WR_NVM			0xb9
#define DS_CMD_RD_NVM			0xba
#define DS_CMD_RD_NVM_PRE		0xbb
#define DS_CMD_GET_HW_INFO		0xbc

#define DS_START_FLAGS_STOP		(1 << 7)
#define DS_START_FLAGS_CLK_48MHZ	(1 << 6)
#define DS_START_FLAGS_SAMPLE_WIDE	(1 << 5)
#define DS_START_FLAGS_MODE_LA		(1 << 4)

#define DS_ADDR_COMB			0x68
#define DS_ADDR_EEWP			0x70
#define DS_ADDR_VTH			0x78

#define DS_MAX_LOGIC_DEPTH		SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE		SR_MHZ(100)

#define DS_MODE_TRIG_EN			(1 << 0)
#define DS_MODE_CLK_TYPE		(1 << 1)
#define DS_MODE_CLK_EDGE		(1 << 2)
#define DS_MODE_RLE_MODE		(1 << 3)
#define DS_MODE_DSO_MODE		(1 << 4)
#define DS_MODE_HALF_MODE		(1 << 5)
#define DS_MODE_QUAR_MODE		(1 << 6)
#define DS_MODE_ANALOG_MODE		(1 << 7)
#define DS_MODE_FILTER			(1 << 8)
#define DS_MODE_INSTANT			(1 << 9)
#define DS_MODE_STRIG_MODE		(1 << 11)
#define DS_MODE_STREAM_MODE		(1 << 12)
#define DS_MODE_LPB_TEST		(1 << 13)
#define DS_MODE_EXT_TEST		(1 << 14)
#define DS_MODE_INT_TEST		(1 << 15)

enum dslogic_operation_modes {
	DS_OP_NORMAL,
	DS_OP_INTERNAL_TEST,
	DS_OP_EXTERNAL_TEST,
	DS_OP_LOOPBACK_TEST,
};

enum {
	DS_VOLTAGE_RANGE_18_33_V,	/* 1.8V and 3.3V logic */
	DS_VOLTAGE_RANGE_5_V,		/* 5V logic */
};

enum {
	DS_EDGE_RISING,
	DS_EDGE_FALLING,
};

struct dslogic_version {
	uint8_t major;
	uint8_t minor;
};

struct dslogic_mode {
	uint8_t flags;
	uint8_t sample_delay_h;
	uint8_t sample_delay_l;
};

struct dslogic_trigger_pos {
	uint32_t real_pos;
	uint32_t ram_saddr;
	uint32_t remain_cnt;
	uint8_t first_block[500];
};

/*
 * The FPGA is configured with TLV tuples. Length is specified as the
 * number of 16-bit words.
 */
#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
#define DS_CFG_START		0xf5a5f5a5
#define DS_CFG_MODE		_DS_CFG(0, 1)
#define DS_CFG_DIVIDER		_DS_CFG(1, 2)
#define DS_CFG_COUNT		_DS_CFG(3, 2)
#define DS_CFG_TRIG_POS		_DS_CFG(5, 2)
#define DS_CFG_TRIG_GLB		_DS_CFG(7, 1)
#define DS_CFG_CH_EN		_DS_CFG(8, 1)
#define DS_CFG_TRIG		_DS_CFG(64, 160)
#define DS_CFG_END		0xfa5afa5a

#pragma pack(push, 1)

struct dslogic_fpga_config {
	uint32_t sync;

	uint16_t mode_header;
	uint16_t mode;
	uint16_t divider_header;
	uint32_t divider;
	uint16_t count_header;
	uint32_t count;
	uint16_t trig_pos_header;
	uint32_t trig_pos;
	uint16_t trig_glb_header;
	uint16_t trig_glb;
	uint16_t ch_en_header;
	uint16_t ch_en;

	uint16_t trig_header;
	uint16_t trig_mask0[NUM_TRIGGER_STAGES];
	uint16_t trig_mask1[NUM_TRIGGER_STAGES];
	uint16_t trig_value0[NUM_TRIGGER_STAGES];
	uint16_t trig_value1[NUM_TRIGGER_STAGES];
	uint16_t trig_edge0[NUM_TRIGGER_STAGES];
	uint16_t trig_edge1[NUM_TRIGGER_STAGES];
	uint16_t trig_logic0[NUM_TRIGGER_STAGES];
	uint16_t trig_logic1[NUM_TRIGGER_STAGES];
	uint32_t trig_count[NUM_TRIGGER_STAGES];

	uint32_t end_sync;
};

#pragma pack(pop)

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);

#endif
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
adcb9951 JH	21	#ifndef LIBSIGROK_HARDWARE_DSLOGIC_DSLOGIC_H
adcb9951 JH	22	#define LIBSIGROK_HARDWARE_DSLOGIC_DSLOGIC_H
6fcf3f0a	23
b9d53092 BV	24	/* Modified protocol commands & flags used by DSLogic */
	25	#define DS_CMD_GET_FW_VERSION 0xb0
	26	#define DS_CMD_GET_REVID_VERSION 0xb1
6fcf3f0a	27	#define DS_CMD_START 0xb2
9d71f815 JH	28	#define DS_CMD_CONFIG 0xb3
	29	#define DS_CMD_SETTING 0xb4
	30	#define DS_CMD_CONTROL 0xb5
	31	#define DS_CMD_STATUS 0xb6
	32	#define DS_CMD_STATUS_INFO 0xb7
	33	#define DS_CMD_WR_REG 0xb8
	34	#define DS_CMD_WR_NVM 0xb9
	35	#define DS_CMD_RD_NVM 0xba
	36	#define DS_CMD_RD_NVM_PRE 0xbb
	37	#define DS_CMD_GET_HW_INFO 0xbc
b9d53092	38
6fcf3f0a	39	#define DS_START_FLAGS_STOP (1 << 7)
	40	#define DS_START_FLAGS_CLK_48MHZ (1 << 6)
	41	#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
62974b23	42	#define DS_START_FLAGS_MODE_LA (1 << 4)
b9d53092	43
ac0facf4 JH	44	#define DS_ADDR_COMB 0x68
	45	#define DS_ADDR_EEWP 0x70
	46	#define DS_ADDR_VTH 0x78
	47
9803346f UH	48	#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
9803346f UH	49	#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
a9a9bfaa	50
cf398cc0 JH	51	#define DS_MODE_TRIG_EN (1 << 0)
	52	#define DS_MODE_CLK_TYPE (1 << 1)
	53	#define DS_MODE_CLK_EDGE (1 << 2)
	54	#define DS_MODE_RLE_MODE (1 << 3)
	55	#define DS_MODE_DSO_MODE (1 << 4)
	56	#define DS_MODE_HALF_MODE (1 << 5)
	57	#define DS_MODE_QUAR_MODE (1 << 6)
	58	#define DS_MODE_ANALOG_MODE (1 << 7)
	59	#define DS_MODE_FILTER (1 << 8)
	60	#define DS_MODE_INSTANT (1 << 9)
	61	#define DS_MODE_STRIG_MODE (1 << 11)
	62	#define DS_MODE_STREAM_MODE (1 << 12)
	63	#define DS_MODE_LPB_TEST (1 << 13)
	64	#define DS_MODE_EXT_TEST (1 << 14)
	65	#define DS_MODE_INT_TEST (1 << 15)
	66
b9d53092 BV	67	enum dslogic_operation_modes {
	68	DS_OP_NORMAL,
	69	DS_OP_INTERNAL_TEST,
	70	DS_OP_EXTERNAL_TEST,
	71	DS_OP_LOOPBACK_TEST,
	72	};
	73
9803346f UH	74	enum {
	75	DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
	76	DS_VOLTAGE_RANGE_5_V, /* 5V logic */
3fc3fbe4 DA	77	};
3fc3fbe4 DA	78
9803346f	79	enum {
d9a58763	80	DS_EDGE_RISING,
9803346f	81	DS_EDGE_FALLING,
d9a58763 DA	82	};
d9a58763 DA	83
b9d53092 BV	84	struct dslogic_version {
	85	uint8_t major;
	86	uint8_t minor;
	87	};
	88
	89	struct dslogic_mode {
	90	uint8_t flags;
	91	uint8_t sample_delay_h;
	92	uint8_t sample_delay_l;
	93	};
	94
	95	struct dslogic_trigger_pos {
	96	uint32_t real_pos;
	97	uint32_t ram_saddr;
4237fbca DA	98	uint32_t remain_cnt;
4237fbca DA	99	uint8_t first_block[500];
b9d53092 BV	100	};
	101
	102	/*
	103	* The FPGA is configured with TLV tuples. Length is specified as the
e40ee26b	104	* number of 16-bit words.
b9d53092 BV	105	*/
b9d53092 BV	106	#define _DS_CFG(variable, wordcnt) ((variable << 8) \| wordcnt)
3f0ff412	107	#define DS_CFG_START 0xf5a5f5a5
6fcf3f0a	108	#define DS_CFG_MODE _DS_CFG(0, 1)
e40ee26b JH	109	#define DS_CFG_DIVIDER _DS_CFG(1, 2)
	110	#define DS_CFG_COUNT _DS_CFG(3, 2)
	111	#define DS_CFG_TRIG_POS _DS_CFG(5, 2)
b9d53092	112	#define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
e40ee26b JH	113	#define DS_CFG_CH_EN _DS_CFG(8, 1)
e40ee26b JH	114	#define DS_CFG_TRIG _DS_CFG(64, 160)
3f0ff412	115	#define DS_CFG_END 0xfa5afa5a
b9d53092	116
e40ee26b JH	117	#pragma pack(push, 1)
e40ee26b JH	118
b9d53092 BV	119	struct dslogic_fpga_config {
b9d53092 BV	120	uint32_t sync;
e40ee26b	121
b9d53092 BV	122	uint16_t mode_header;
b9d53092 BV	123	uint16_t mode;
e40ee26b	124	uint16_t divider_header;
b9d53092	125	uint32_t divider;
e40ee26b	126	uint16_t count_header;
b9d53092	127	uint32_t count;
e40ee26b	128	uint16_t trig_pos_header;
b9d53092 BV	129	uint32_t trig_pos;
	130	uint16_t trig_glb_header;
	131	uint16_t trig_glb;
e40ee26b JH	132	uint16_t ch_en_header;
	133	uint16_t ch_en;
	134
	135	uint16_t trig_header;
adcb9951 JH	136	uint16_t trig_mask0[NUM_TRIGGER_STAGES];
	137	uint16_t trig_mask1[NUM_TRIGGER_STAGES];
	138	uint16_t trig_value0[NUM_TRIGGER_STAGES];
	139	uint16_t trig_value1[NUM_TRIGGER_STAGES];
	140	uint16_t trig_edge0[NUM_TRIGGER_STAGES];
	141	uint16_t trig_edge1[NUM_TRIGGER_STAGES];
	142	uint16_t trig_logic0[NUM_TRIGGER_STAGES];
	143	uint16_t trig_logic1[NUM_TRIGGER_STAGES];
	144	uint32_t trig_count[NUM_TRIGGER_STAGES];
e40ee26b	145
b9d53092 BV	146	uint32_t end_sync;
	147	};
	148
e40ee26b JH	149	#pragma pack(pop)
e40ee26b JH	150
3566348b	151	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi);
8e2d6c9d DE	152	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
	153	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
	154	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
3fc3fbe4	155	SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
9803346f	156	SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
6fcf3f0a	157
6fcf3f0a	158	#endif