[libsigrok.git] / src / hardware / asix-sigma / protocol.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
#define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H

#include <stdint.h>
#include <stdlib.h>
#include <glib.h>
#include <ftdi.h>
#include <string.h>
#include <libsigrok/libsigrok.h>
#include "libsigrok-internal.h"

#define LOG_PREFIX "asix-sigma"

/*
 * Triggers are not working in this implementation. Stop claiming
 * support for the feature which effectively is not available, until
 * the implementation got fixed. Yet keep the code in place and allow
 * developers to turn on this switch during development.
 */
#define ASIX_SIGMA_WITH_TRIGGER	0

/* Experimental support for OMEGA (scan only, operation is ENOIMPL). */
#define ASIX_WITH_OMEGA 0

#define USB_VENDOR_ASIX			0xa600
#define USB_PRODUCT_SIGMA		0xa000
#define USB_PRODUCT_OMEGA		0xa004

enum asix_device_type {
	ASIX_TYPE_NONE,
	ASIX_TYPE_SIGMA,
	ASIX_TYPE_OMEGA,
};

enum sigma_write_register {
	WRITE_CLOCK_SELECT	= 0,
	WRITE_TRIGGER_SELECT	= 1,
	WRITE_TRIGGER_SELECT2	= 2,
	WRITE_MODE		= 3,
	WRITE_MEMROW		= 4,
	WRITE_POST_TRIGGER	= 5,
	WRITE_TRIGGER_OPTION	= 6,
	WRITE_PIN_VIEW		= 7,
	/* Unassigned register locations. */
	WRITE_TEST		= 15,
};

enum sigma_read_register {
	READ_ID			= 0,
	READ_TRIGGER_POS_LOW	= 1,
	READ_TRIGGER_POS_HIGH	= 2,
	READ_TRIGGER_POS_UP	= 3,
	READ_STOP_POS_LOW	= 4,
	READ_STOP_POS_HIGH	= 5,
	READ_STOP_POS_UP	= 6,
	READ_MODE		= 7,
	READ_PIN_CHANGE_LOW	= 8,
	READ_PIN_CHANGE_HIGH	= 9,
	READ_BLOCK_LAST_TS_LOW	= 10,
	READ_BLOCK_LAST_TS_HIGH	= 11,
	READ_BLOCK_TS_OVERRUN	= 12,
	READ_PIN_VIEW		= 13,
	/* Unassigned register location. */
	READ_TEST		= 15,
};

/*
 * FPGA commands are 8bits wide. The upper nibble is a command opcode,
 * the lower nibble can carry operand values. 8bit register addresses
 * and 8bit data values get communicated in two steps.
 */

/* Register access. */
#define REG_ADDR_LOW		(0x0 << 4)
#define REG_ADDR_HIGH		(0x1 << 4)
#define REG_DATA_LOW		(0x2 << 4)
#define REG_DATA_HIGH_WRITE	(0x3 << 4)
#define REG_READ_ADDR		(0x4 << 4)
#define REG_ADDR_ADJUST		(1 << 0) /* Auto adjust register address. */
#define REG_ADDR_DOWN		(1 << 1) /* 1 decrement, 0 increment. */
#define REG_ADDR_INC		(REG_ADDR_ADJUST)
#define REG_ADDR_DEC		(REG_ADDR_ADJUST | REG_ADDR_DOWN)

/* Sample memory access. */
#define REG_DRAM_WAIT_ACK	(0x5 << 4) /* Wait for completion. */
#define REG_DRAM_BLOCK		(0x6 << 4) /* DRAM to BRAM, plus bank select. */
#define REG_DRAM_BLOCK_BEGIN	(0x8 << 4) /* Read first BRAM bytes. */
#define REG_DRAM_BLOCK_DATA	(0xa << 4) /* Read full BRAM block. */
#define REG_DRAM_SEL_N		(0x1 << 4) /* Bank select, added to 6/8/a. */
#define REG_DRAM_SEL_BOOL(b)	((b) ? REG_DRAM_SEL_N : 0)

#define LEDSEL0			6
#define LEDSEL1			7


#define EVENTS_PER_CLUSTER	7

#define CHUNK_SIZE		1024

/* WRITE_MODE register fields. */
#define WMR_SDRAMWRITEEN	(1 << 0)
#define WMR_SDRAMREADEN		(1 << 1)
#define WMR_TRGRES		(1 << 2)
#define WMR_TRGEN		(1 << 3)
#define WMR_FORCESTOP		(1 << 4)
#define WMR_TRGSW		(1 << 5)
/* not used: bit position 6 */
#define WMR_SDRAMINIT		(1 << 7)

/* READ_MODE register fields. */
#define RMR_SDRAMWRITEEN	(1 << 0)
#define RMR_SDRAMREADEN		(1 << 1)
/* not used: bit position 2 */
#define RMR_TRGEN		(1 << 3)
#define RMR_ROUND		(1 << 4)
#define RMR_TRIGGERED		(1 << 5)
#define RMR_POSTTRIGGERED	(1 << 6)
/* not used: bit position 7 */

/*
 * Layout of the sample data DRAM, which will be downloaded to the PC:
 *
 * Sigma memory is organized in 32K rows. Each row contains 64 clusters.
 * Each cluster contains a timestamp (16bit) and 7 samples (16bits each).
 * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit).
 *
 * Sample data is represented in 16bit quantities. The first sample in
 * the cluster corresponds to the cluster's timestamp. Each next sample
 * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
 * one sample period, according to the samplerate). In the absence of
 * pin level changes, no data is provided (RLE compression). A cluster
 * is enforced for each 64K ticks of the timestamp, to reliably handle
 * rollover and determination of the next timestamp of the next cluster.
 *
 * For samplerates of 100MHz, there is one 16 bit entity for each 20ns
 * period (50MHz rate). The 16 bit memory contains 2 samples of up to
 * 8 channels. Bits of multiple samples are interleaved. For samplerates
 * of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
 * each 5ns apart.
 *
 * Memory addresses (sample count, trigger position) are kept in 24bit
 * entities. The upper 15 bit refer to the "row", the lower 9 bit refer
 * to the "event" within the row. Because there is one timestamp for
 * seven samples each, one memory row can hold up to 64x7 == 448 samples.
 */

/* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
struct sigma_dram_cluster {
	uint8_t		timestamp_lo;
	uint8_t		timestamp_hi;
	struct {
		uint8_t	sample_hi;
		uint8_t	sample_lo;
	}		samples[7];
};

/* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
struct sigma_dram_line {
	struct sigma_dram_cluster	cluster[64];
};

struct clockselect_50 {
	uint8_t async;
	uint8_t fraction;
	uint16_t disabled_channels;
};

/* The effect of all these are still a bit unclear. */
struct triggerinout {
	uint8_t trgout_resistor_enable : 1;
	uint8_t trgout_resistor_pullup : 1;
	uint8_t reserved1 : 1;
	uint8_t trgout_bytrigger : 1;
	uint8_t trgout_byevent : 1;
	uint8_t trgout_bytriggerin : 1;
	uint8_t reserved2 : 2;

	/* Should be set same as the first two */
	uint8_t trgout_resistor_enable2 : 1;
	uint8_t trgout_resistor_pullup2 : 1;

	uint8_t reserved3 : 1;
	uint8_t trgout_long : 1;
	uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
	uint8_t trgin_negate : 1;
	uint8_t trgout_enable : 1;
	uint8_t trgin_enable : 1;
};

struct triggerlut {
	/* The actual LUTs. */
	uint16_t m0d[4], m1d[4], m2d[4];
	uint16_t m3, m3s, m4;

	/* Parameters should be sent as a single register write. */
	struct {
		uint8_t selc : 2;
		uint8_t selpresc : 6;

		uint8_t selinc : 2;
		uint8_t selres : 2;
		uint8_t sela : 2;
		uint8_t selb : 2;

		uint16_t cmpb;
		uint16_t cmpa;
	} params;
};

/* Trigger configuration */
struct sigma_trigger {
	/* Only two channels can be used in mask. */
	uint16_t risingmask;
	uint16_t fallingmask;

	/* Simple trigger support (<= 50 MHz). */
	uint16_t simplemask;
	uint16_t simplevalue;

	/* TODO: Advanced trigger support (boolean expressions). */
};

/* Events for trigger operation. */
enum triggerop {
	OP_LEVEL = 1,
	OP_NOT,
	OP_RISE,
	OP_FALL,
	OP_RISEFALL,
	OP_NOTRISE,
	OP_NOTFALL,
	OP_NOTRISEFALL,
};

/* Logical functions for trigger operation. */
enum triggerfunc {
	FUNC_AND = 1,
	FUNC_NAND,
	FUNC_OR,
	FUNC_NOR,
	FUNC_XOR,
	FUNC_NXOR,
};

struct sigma_state {
	enum {
		SIGMA_UNINITIALIZED = 0,
		SIGMA_IDLE,
		SIGMA_CAPTURE,
		SIGMA_STOPPING,
		SIGMA_DOWNLOAD,
	} state;
	uint16_t lastts;
	uint16_t lastsample;
};

struct dev_context {
	struct {
		uint16_t vid, pid;
		uint32_t serno;
		uint16_t prefix;
		enum asix_device_type type;
	} id;
	struct ftdi_context ftdic;
	uint64_t cur_samplerate;
	uint64_t limit_msec;
	uint64_t limit_samples;
	uint64_t sent_samples;
	uint64_t start_time;
	int cur_firmware;
	int num_channels;
	int cur_channels;
	int samples_per_event;
	uint64_t capture_ratio;
	struct sigma_trigger trigger;
	int use_triggers;
	struct sigma_state state;
};

extern SR_PRIV const uint64_t samplerates[];
extern SR_PRIV const size_t samplerates_count;

SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
				 struct dev_context *devc);
SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc);
SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc);
SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
					     uint64_t limit_samples);
SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);
SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc);

#endif
Commit	Line	Data
204b1629	1	/*
50985c20	2	* This file is part of the libsigrok project.
204b1629	3	*
3ba56876	4	* Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
204b1629 UH	5	* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
	6	* Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
3ba56876	22	#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
	23	#define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
	24
	25	#include <stdint.h>
4154a516	26	#include <stdlib.h>
3ba56876	27	#include <glib.h>
	28	#include <ftdi.h>
	29	#include <string.h>
	30	#include <libsigrok/libsigrok.h>
	31	#include "libsigrok-internal.h"
28a35d8a	32
f272d7dd UH	33	#define LOG_PREFIX "asix-sigma"
f272d7dd UH	34
de3f7acb GS	35	/*
	36	* Triggers are not working in this implementation. Stop claiming
	37	* support for the feature which effectively is not available, until
	38	* the implementation got fixed. Yet keep the code in place and allow
	39	* developers to turn on this switch during development.
	40	*/
	41	#define ASIX_SIGMA_WITH_TRIGGER 0
	42
53a939ab GS	43	/* Experimental support for OMEGA (scan only, operation is ENOIMPL). */
	44	#define ASIX_WITH_OMEGA 0
	45
	46	#define USB_VENDOR_ASIX 0xa600
	47	#define USB_PRODUCT_SIGMA 0xa000
	48	#define USB_PRODUCT_OMEGA 0xa004
	49
	50	enum asix_device_type {
	51	ASIX_TYPE_NONE,
	52	ASIX_TYPE_SIGMA,
	53	ASIX_TYPE_OMEGA,
	54	};
3ba56876	55
fefa1800	56	enum sigma_write_register {
28a35d8a	57	WRITE_CLOCK_SELECT = 0,
9fb4c632 GS	58	WRITE_TRIGGER_SELECT = 1,
9fb4c632 GS	59	WRITE_TRIGGER_SELECT2 = 2,
28a35d8a HE	60	WRITE_MODE = 3,
	61	WRITE_MEMROW = 4,
	62	WRITE_POST_TRIGGER = 5,
	63	WRITE_TRIGGER_OPTION = 6,
	64	WRITE_PIN_VIEW = 7,
9fb4c632	65	/* Unassigned register locations. */
fefa1800	66	WRITE_TEST = 15,
28a35d8a HE	67	};
28a35d8a HE	68
fefa1800	69	enum sigma_read_register {
28a35d8a HE	70	READ_ID = 0,
	71	READ_TRIGGER_POS_LOW = 1,
	72	READ_TRIGGER_POS_HIGH = 2,
	73	READ_TRIGGER_POS_UP = 3,
	74	READ_STOP_POS_LOW = 4,
	75	READ_STOP_POS_HIGH = 5,
	76	READ_STOP_POS_UP = 6,
	77	READ_MODE = 7,
	78	READ_PIN_CHANGE_LOW = 8,
	79	READ_PIN_CHANGE_HIGH = 9,
	80	READ_BLOCK_LAST_TS_LOW = 10,
	81	READ_BLOCK_LAST_TS_HIGH = 11,
9fb4c632 GS	82	READ_BLOCK_TS_OVERRUN = 12,
	83	READ_PIN_VIEW = 13,
	84	/* Unassigned register location. */
fefa1800	85	READ_TEST = 15,
28a35d8a HE	86	};
28a35d8a HE	87
07411a60 GS	88	/*
	89	* FPGA commands are 8bits wide. The upper nibble is a command opcode,
	90	* the lower nibble can carry operand values. 8bit register addresses
	91	* and 8bit data values get communicated in two steps.
	92	*/
	93
	94	/* Register access. */
1c2736f9 MV	95	#define REG_ADDR_LOW (0x0 << 4)
	96	#define REG_ADDR_HIGH (0x1 << 4)
	97	#define REG_DATA_LOW (0x2 << 4)
	98	#define REG_DATA_HIGH_WRITE (0x3 << 4)
	99	#define REG_READ_ADDR (0x4 << 4)
07411a60 GS	100	#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */
	101	#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */
	102	#define REG_ADDR_INC (REG_ADDR_ADJUST)
	103	#define REG_ADDR_DEC (REG_ADDR_ADJUST \| REG_ADDR_DOWN)
	104
	105	/* Sample memory access. */
	106	#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */
	107	#define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */
	108	#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */
	109	#define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */
	110	#define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */
	111	#define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0)
28a35d8a	112
57bbf56b HE	113	#define LEDSEL0 6
	114	#define LEDSEL1 7
	115
28a35d8a HE	116
	117	#define EVENTS_PER_CLUSTER 7
	118
	119	#define CHUNK_SIZE 1024
	120
22f64ed8 GS	121	/* WRITE_MODE register fields. */
	122	#define WMR_SDRAMWRITEEN (1 << 0)
	123	#define WMR_SDRAMREADEN (1 << 1)
	124	#define WMR_TRGRES (1 << 2)
	125	#define WMR_TRGEN (1 << 3)
	126	#define WMR_FORCESTOP (1 << 4)
	127	#define WMR_TRGSW (1 << 5)
	128	/* not used: bit position 6 */
	129	#define WMR_SDRAMINIT (1 << 7)
	130
	131	/* READ_MODE register fields. */
	132	#define RMR_SDRAMWRITEEN (1 << 0)
	133	#define RMR_SDRAMREADEN (1 << 1)
	134	/* not used: bit position 2 */
	135	#define RMR_TRGEN (1 << 3)
	136	#define RMR_ROUND (1 << 4)
	137	#define RMR_TRIGGERED (1 << 5)
	138	#define RMR_POSTTRIGGERED (1 << 6)
	139	/* not used: bit position 7 */
	140
fd830beb	141	/*
5b1d15ef GS	142	* Layout of the sample data DRAM, which will be downloaded to the PC:
	143	*
	144	* Sigma memory is organized in 32K rows. Each row contains 64 clusters.
	145	* Each cluster contains a timestamp (16bit) and 7 samples (16bits each).
	146	* Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit).
	147	*
	148	* Sample data is represented in 16bit quantities. The first sample in
	149	* the cluster corresponds to the cluster's timestamp. Each next sample
	150	* corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
	151	* one sample period, according to the samplerate). In the absence of
	152	* pin level changes, no data is provided (RLE compression). A cluster
	153	* is enforced for each 64K ticks of the timestamp, to reliably handle
	154	* rollover and determination of the next timestamp of the next cluster.
	155	*
	156	* For samplerates of 100MHz, there is one 16 bit entity for each 20ns
	157	* period (50MHz rate). The 16 bit memory contains 2 samples of up to
	158	* 8 channels. Bits of multiple samples are interleaved. For samplerates
	159	* of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
	160	* each 5ns apart.
	161	*
	162	* Memory addresses (sample count, trigger position) are kept in 24bit
	163	* entities. The upper 15 bit refer to the "row", the lower 9 bit refer
	164	* to the "event" within the row. Because there is one timestamp for
	165	* seven samples each, one memory row can hold up to 64x7 == 448 samples.
fd830beb MV	166	*/
	167
	168	/* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
	169	struct sigma_dram_cluster {
	170	uint8_t timestamp_lo;
	171	uint8_t timestamp_hi;
	172	struct {
	173	uint8_t sample_hi;
	174	uint8_t sample_lo;
	175	} samples[7];
	176	};
	177
	178	/* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
	179	struct sigma_dram_line {
	180	struct sigma_dram_cluster cluster[64];
	181	};
	182
edca2c5c HE	183	struct clockselect_50 {
	184	uint8_t async;
	185	uint8_t fraction;
ba7dd8bb	186	uint16_t disabled_channels;
edca2c5c HE	187	};
edca2c5c HE	188
57bbf56b HE	189	/* The effect of all these are still a bit unclear. */
	190	struct triggerinout {
	191	uint8_t trgout_resistor_enable : 1;
	192	uint8_t trgout_resistor_pullup : 1;
	193	uint8_t reserved1 : 1;
	194	uint8_t trgout_bytrigger : 1;
	195	uint8_t trgout_byevent : 1;
	196	uint8_t trgout_bytriggerin : 1;
	197	uint8_t reserved2 : 2;
	198
	199	/* Should be set same as the first two */
	200	uint8_t trgout_resistor_enable2 : 1;
	201	uint8_t trgout_resistor_pullup2 : 1;
	202
	203	uint8_t reserved3 : 1;
	204	uint8_t trgout_long : 1;
	205	uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
	206	uint8_t trgin_negate : 1;
	207	uint8_t trgout_enable : 1;
	208	uint8_t trgin_enable : 1;
	209	};
	210
ee492173 HE	211	struct triggerlut {
	212	/* The actual LUTs. */
	213	uint16_t m0d[4], m1d[4], m2d[4];
	214	uint16_t m3, m3s, m4;
	215
f3f19d11	216	/* Parameters should be sent as a single register write. */
ee492173 HE	217	struct {
	218	uint8_t selc : 2;
	219	uint8_t selpresc : 6;
	220
	221	uint8_t selinc : 2;
	222	uint8_t selres : 2;
	223	uint8_t sela : 2;
	224	uint8_t selb : 2;
	225
	226	uint16_t cmpb;
	227	uint16_t cmpa;
	228	} params;
	229	};
	230
c53d793f HE	231	/* Trigger configuration */
c53d793f HE	232	struct sigma_trigger {
ba7dd8bb	233	/* Only two channels can be used in mask. */
a42aec7f HE	234	uint16_t risingmask;
a42aec7f HE	235	uint16_t fallingmask;
c53d793f HE	236
	237	/* Simple trigger support (<= 50 MHz). */
	238	uint16_t simplemask;
	239	uint16_t simplevalue;
	240
c53d793f HE	241	/* TODO: Advanced trigger support (boolean expressions). */
	242	};
	243
	244	/* Events for trigger operation. */
	245	enum triggerop {
	246	OP_LEVEL = 1,
	247	OP_NOT,
	248	OP_RISE,
	249	OP_FALL,
	250	OP_RISEFALL,
	251	OP_NOTRISE,
	252	OP_NOTFALL,
	253	OP_NOTRISEFALL,
	254	};
	255
	256	/* Logical functions for trigger operation. */
	257	enum triggerfunc {
	258	FUNC_AND = 1,
	259	FUNC_NAND,
	260	FUNC_OR,
	261	FUNC_NOR,
	262	FUNC_XOR,
	263	FUNC_NXOR,
	264	};
	265
6aac7737 HE	266	struct sigma_state {
	267	enum {
	268	SIGMA_UNINITIALIZED = 0,
	269	SIGMA_IDLE,
	270	SIGMA_CAPTURE,
dde0175d	271	SIGMA_STOPPING,
6aac7737 HE	272	SIGMA_DOWNLOAD,
6aac7737 HE	273	} state;
6aac7737 HE	274	uint16_t lastts;
6aac7737 HE	275	uint16_t lastsample;
6aac7737 HE	276	};
6aac7737 HE	277
0e1357e8	278	struct dev_context {
53a939ab GS	279	struct {
	280	uint16_t vid, pid;
	281	uint32_t serno;
	282	uint16_t prefix;
	283	enum asix_device_type type;
	284	} id;
99965709 HE	285	struct ftdi_context ftdic;
99965709 HE	286	uint64_t cur_samplerate;
94ba4bd6	287	uint64_t limit_msec;
2f7e529c	288	uint64_t limit_samples;
735ed8a1	289	uint64_t sent_samples;
2f425a56	290	uint64_t start_time;
99965709	291	int cur_firmware;
ba7dd8bb	292	int num_channels;
5fc01191	293	int cur_channels;
99965709	294	int samples_per_event;
efad7ccc	295	uint64_t capture_ratio;
99965709	296	struct sigma_trigger trigger;
5b5ea7c6	297	int use_triggers;
99965709	298	struct sigma_state state;
99965709 HE	299	};
99965709 HE	300
3ba56876	301	extern SR_PRIV const uint64_t samplerates[];
4154a516	302	extern SR_PRIV const size_t samplerates_count;
3ba56876	303
176d785d	304	SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
3ba56876	305	struct dev_context *devc);
	306	SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc);
	307	SR_PRIV int sigma_write_trigger_lut(struct triggerlut lut, struct dev_context devc);
9a0a606a GS	308	SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
9a0a606a GS	309	uint64_t limit_samples);
3ba56876	310	SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
	311	SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
	312	SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);
	313	SR_PRIV int sigma_build_basic_trigger(struct triggerlut lut, struct dev_context devc);
	314
204b1629	315	#endif