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Commit | Line | Data |
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fb21eed8 JH |
1 | ------------------------------------------------------------------------------- |
2 | I2S Master 2-channel 16-bit 16-kHz | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
47cd3c8f | 5 | This is an example of an I2S master playing a recording of the BBC |
fb21eed8 JH |
6 | shipping forecast through one channel, and the other channel disconnected. |
7 | ||
8 | Logic analyzer setup | |
9 | -------------------- | |
10 | ||
47cd3c8f | 11 | The logic analyzer used was an EE Electronics ESLA201A (at 16MHz): |
fb21eed8 | 12 | |
47cd3c8f UH |
13 | Probe I2S pin |
14 | ------------------- | |
fb21eed8 JH |
15 | 0 Clock |
16 | 1 Frame Select | |
17 | 2 Data | |
01e11948 | 18 |