[libsigrok.git] / hardware / sysclk-lwla / protocol.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H

/* Message logging helpers with subsystem-specific prefix string. */
#define LOG_PREFIX "sysclk-lwla"

#include "lwla.h"
#include "libsigrok.h"
#include "libsigrok-internal.h"
#include <stdint.h>
#include <glib.h>

/* For now, only the LWLA1034 is supported.
 */
#define VENDOR_NAME	"SysClk"
#define MODEL_NAME	"LWLA1034"

#define USB_VID_PID	"2961.6689"
#define USB_INTERFACE	0
#define USB_TIMEOUT	3000 /* ms */

#define NUM_PROBES	34
#define TRIGGER_TYPES	"01fr"

/* Bit mask covering all 34 channels.
 */
#define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1)

/** Unit and packet size for the sigrok logic datafeed.
 */
#define UNIT_SIZE	((NUM_PROBES + 7) / 8)
#define PACKET_LENGTH	10000	/* units */

/** Size of the acquisition buffer in device memory units.
 */
#define MEMORY_DEPTH	(256 * 1024)	/* 256k x 36 bit */

/** Number of device memory units (36 bit) to read at a time.  Slices of 8
 * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
 * length should be a multiple of 8 to ensure alignment to slice boundaries.
 *
 * Experimentation has shown that reading chunks larger than about 1024 bytes
 * is unreliable.  The threshold seems to relate to the buffer size on the FX2
 * USB chip:  The configured endpoint buffer size is 512, and with double or
 * triple buffering enabled a multiple of 512 bytes can be kept in fly.
 *
 * The vendor software limits reads to 120 words (15 slices, 540 bytes) at
 * a time.  So far, it appears safe to increase this to 224 words (28 slices,
 * 1008 bytes), thus making the most of two 512 byte buffers.
 */
#define READ_CHUNK_LEN	(28 * 8)

/** Calculate the required buffer size in 32-bit units for reading a given
 * number of device memory words.  Rounded to a multiple of 8 device words.
 */
#define LWLA1034_MEMBUF_LEN(count) (((count) + 7) / 8 * 9)

/** Maximum number of 16-bit words sent at a time during acquisition.
 * Used for allocating the libusb transfer buffer.
 */
#define MAX_ACQ_SEND_WORDS	8 /* 5 for memory read request plus stuffing */

/** Maximum number of 32-bit words received at a time during acquisition.
 * Round to the next multiple of the endpoint buffer size to avoid nasty
 * transfer overflow conditions on hiccups.
 */
#define MAX_ACQ_RECV_LEN	((READ_CHUNK_LEN / 8 * 9 + 127) / 128 * 128)

/** Maximum length of a register write sequence.
 */
#define MAX_REG_WRITE_SEQ_LEN   5

/** Default configured samplerate.
 */
#define DEFAULT_SAMPLERATE	SR_MHZ(125)

/** Maximum configurable sample count limit.
 */
#define MAX_LIMIT_SAMPLES	(UINT64_C(1) << 48)

/** Maximum configurable capture duration in milliseconds.
 */
#define MAX_LIMIT_MSEC		(UINT64_C(1) << 32)

/** LWLA1034 FPGA clock configurations.
 */
enum clock_config {
	CONF_CLOCK_NONE,
	CONF_CLOCK_INT,
	CONF_CLOCK_EXT_RISE,
	CONF_CLOCK_EXT_FALL,
};

/** Available clock sources.
 */
enum clock_source {
	CLOCK_INTERNAL,
	CLOCK_EXT_CLK,
};

/** Available trigger sources.
 */
enum trigger_source {
	TRIGGER_CHANNELS = 0,
	TRIGGER_EXT_TRG,
};

/** Available edge choices for the external clock and trigger inputs.
 */
enum signal_edge {
	EDGE_POSITIVE = 0,
	EDGE_NEGATIVE,
};

/** LWLA device states.
 */
enum device_state {
	STATE_IDLE = 0,

	STATE_START_CAPTURE,

	STATE_STATUS_WAIT,
	STATE_STATUS_REQUEST,
	STATE_STATUS_RESPONSE,

	STATE_STOP_CAPTURE,

	STATE_LENGTH_REQUEST,
	STATE_LENGTH_RESPONSE,

	STATE_READ_PREPARE,
	STATE_READ_REQUEST,
	STATE_READ_RESPONSE,
	STATE_READ_END,
};

/** LWLA run-length encoding states.
 */
enum rle_state {
	RLE_STATE_DATA,
	RLE_STATE_LEN
};

/** LWLA sample acquisition and decompression state.
 */
struct acquisition_state {
	uint64_t sample;
	uint64_t run_len;

	/** Maximum number of samples to process. */
	uint64_t samples_max;
	/** Number of samples sent to the session bus. */
	uint64_t samples_done;

	/** Maximum duration of capture, in milliseconds. */
	uint64_t duration_max;
	/** Running capture duration since trigger event. */
	uint64_t duration_now;

	/** Capture memory fill level. */
	size_t mem_addr_fill;

	size_t mem_addr_done;
	size_t mem_addr_next;
	size_t mem_addr_stop;

	size_t out_index;

	struct libusb_transfer *xfer_in;
	struct libusb_transfer *xfer_out;

	unsigned int capture_flags;

	enum rle_state rle;

	/** Whether to bypass the clock divider. */
	gboolean bypass_clockdiv;

	/* Payload data buffers for incoming and outgoing transfers. */
	uint32_t xfer_buf_in[MAX_ACQ_RECV_LEN];
	uint16_t xfer_buf_out[MAX_ACQ_SEND_WORDS];

	/* Payload buffer for sigrok logic packets. */
	uint8_t out_packet[PACKET_LENGTH * UNIT_SIZE];
};

/** Private, per-device-instance driver context.
 */
struct dev_context {
	/** The samplerate selected by the user. */
	uint64_t samplerate;

	/** The maximimum sampling duration, in milliseconds. */
	uint64_t limit_msec;

	/** The maximimum number of samples to acquire. */
	uint64_t limit_samples;

	/** Channels to use. */
	uint64_t channel_mask;

	uint64_t trigger_mask;
	uint64_t trigger_edge_mask;
	uint64_t trigger_values;

	struct acquisition_state *acquisition;

	struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
	int reg_write_pos;
	int reg_write_len;

	enum device_state state;

	/** The currently active clock configuration of the device. */
	enum clock_config cur_clock_config;

	/** Clock source configuration setting. */
	enum clock_source cfg_clock_source;
	/** Clock edge configuration setting. */
	enum signal_edge cfg_clock_edge;

	/** Trigger source configuration setting. */
	enum trigger_source cfg_trigger_source;
	/** Trigger slope configuration setting. */
	enum signal_edge cfg_trigger_slope;

	/* Indicates that stopping the acquisition is currently in progress. */
	gboolean stopping_in_progress;

	/* Indicates whether a transfer failed. */
	gboolean transfer_error;
};

SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);

SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_abort_acquisition(const struct sr_dev_inst *sdi);

SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data);

#endif /* !LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H */
Commit	Line	Data
aeaad0b0 DE	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
	21	#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
	22
5874e88d DE	23	/* Message logging helpers with subsystem-specific prefix string. */
	24	#define LOG_PREFIX "sysclk-lwla"
	25
	26	#include "lwla.h"
aeaad0b0 DE	27	#include "libsigrok.h"
aeaad0b0 DE	28	#include "libsigrok-internal.h"
5874e88d DE	29	#include <stdint.h>
5874e88d DE	30	#include <glib.h>
aeaad0b0	31
5874e88d DE	32	/* For now, only the LWLA1034 is supported.
	33	*/
	34	#define VENDOR_NAME "SysClk"
	35	#define MODEL_NAME "LWLA1034"
	36
	37	#define USB_VID_PID "2961.6689"
	38	#define USB_INTERFACE 0
	39	#define USB_TIMEOUT 3000 /* ms */
	40
	41	#define NUM_PROBES 34
	42	#define TRIGGER_TYPES "01fr"
	43
43db3436 DE	44	/* Bit mask covering all 34 channels.
	45	*/
	46	#define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1)
	47
5874e88d DE	48	/** Unit and packet size for the sigrok logic datafeed.
	49	*/
	50	#define UNIT_SIZE ((NUM_PROBES + 7) / 8)
2cfd16a3	51	#define PACKET_LENGTH 10000 /* units */
5874e88d DE	52
	53	/** Size of the acquisition buffer in device memory units.
	54	*/
	55	#define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */
	56
	57	/** Number of device memory units (36 bit) to read at a time. Slices of 8
	58	* consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
	59	* length should be a multiple of 8 to ensure alignment to slice boundaries.
	60	*
	61	* Experimentation has shown that reading chunks larger than about 1024 bytes
	62	* is unreliable. The threshold seems to relate to the buffer size on the FX2
	63	* USB chip: The configured endpoint buffer size is 512, and with double or
	64	* triple buffering enabled a multiple of 512 bytes can be kept in fly.
	65	*
	66	* The vendor software limits reads to 120 words (15 slices, 540 bytes) at
	67	* a time. So far, it appears safe to increase this to 224 words (28 slices,
	68	* 1008 bytes), thus making the most of two 512 byte buffers.
	69	*/
	70	#define READ_CHUNK_LEN (28 * 8)
	71
e0df15d4	72	/** Calculate the required buffer size in 32-bit units for reading a given
5874e88d DE	73	* number of device memory words. Rounded to a multiple of 8 device words.
5874e88d DE	74	*/
e0df15d4	75	#define LWLA1034_MEMBUF_LEN(count) (((count) + 7) / 8 * 9)
5874e88d DE	76
	77	/** Maximum number of 16-bit words sent at a time during acquisition.
	78	* Used for allocating the libusb transfer buffer.
	79	*/
	80	#define MAX_ACQ_SEND_WORDS 8 /* 5 for memory read request plus stuffing */
	81
e0df15d4	82	/** Maximum number of 32-bit words received at a time during acquisition.
5874e88d DE	83	* Round to the next multiple of the endpoint buffer size to avoid nasty
	84	* transfer overflow conditions on hiccups.
	85	*/
e0df15d4	86	#define MAX_ACQ_RECV_LEN ((READ_CHUNK_LEN / 8 * 9 + 127) / 128 * 128)
5874e88d DE	87
	88	/** Maximum length of a register write sequence.
	89	*/
	90	#define MAX_REG_WRITE_SEQ_LEN 5
	91
	92	/** Default configured samplerate.
	93	*/
	94	#define DEFAULT_SAMPLERATE SR_MHZ(125)
	95
29d58767 DE	96	/** Maximum configurable sample count limit.
	97	*/
	98	#define MAX_LIMIT_SAMPLES (UINT64_C(1) << 48)
	99
	100	/** Maximum configurable capture duration in milliseconds.
	101	*/
	102	#define MAX_LIMIT_MSEC (UINT64_C(1) << 32)
	103
6358f0a9 DE	104	/** LWLA1034 FPGA clock configurations.
	105	*/
	106	enum clock_config {
	107	CONF_CLOCK_NONE,
	108	CONF_CLOCK_INT,
	109	CONF_CLOCK_EXT_RISE,
	110	CONF_CLOCK_EXT_FALL,
	111	};
	112
	113	/** Available clock sources.
5874e88d DE	114	*/
5874e88d DE	115	enum clock_source {
6358f0a9 DE	116	CLOCK_INTERNAL,
6358f0a9 DE	117	CLOCK_EXT_CLK,
5874e88d DE	118	};
5874e88d DE	119
e6e54bd2 DE	120	/** Available trigger sources.
	121	*/
	122	enum trigger_source {
	123	TRIGGER_CHANNELS = 0,
	124	TRIGGER_EXT_TRG,
	125	};
	126
6358f0a9	127	/** Available edge choices for the external clock and trigger inputs.
e6e54bd2	128	*/
6358f0a9 DE	129	enum signal_edge {
	130	EDGE_POSITIVE = 0,
	131	EDGE_NEGATIVE,
e6e54bd2 DE	132	};
e6e54bd2 DE	133
5874e88d DE	134	/** LWLA device states.
	135	*/
	136	enum device_state {
	137	STATE_IDLE = 0,
	138
	139	STATE_START_CAPTURE,
	140
	141	STATE_STATUS_WAIT,
	142	STATE_STATUS_REQUEST,
	143	STATE_STATUS_RESPONSE,
	144
	145	STATE_STOP_CAPTURE,
	146
	147	STATE_LENGTH_REQUEST,
	148	STATE_LENGTH_RESPONSE,
	149
	150	STATE_READ_PREPARE,
	151	STATE_READ_REQUEST,
	152	STATE_READ_RESPONSE,
	153	STATE_READ_END,
	154	};
	155
	156	/** LWLA run-length encoding states.
	157	*/
	158	enum rle_state {
	159	RLE_STATE_DATA,
	160	RLE_STATE_LEN
	161	};
	162
	163	/** LWLA sample acquisition and decompression state.
	164	*/
	165	struct acquisition_state {
	166	uint64_t sample;
	167	uint64_t run_len;
	168
29d58767 DE	169	/** Maximum number of samples to process. */
29d58767 DE	170	uint64_t samples_max;
5874e88d	171	/** Number of samples sent to the session bus. */
29d58767 DE	172	uint64_t samples_done;
	173
	174	/** Maximum duration of capture, in milliseconds. */
	175	uint64_t duration_max;
	176	/** Running capture duration since trigger event. */
	177	uint64_t duration_now;
5874e88d DE	178
	179	/** Capture memory fill level. */
	180	size_t mem_addr_fill;
aeaad0b0	181
5874e88d DE	182	size_t mem_addr_done;
	183	size_t mem_addr_next;
	184	size_t mem_addr_stop;
	185
2cfd16a3	186	size_t out_index;
5874e88d DE	187
	188	struct libusb_transfer *xfer_in;
	189	struct libusb_transfer *xfer_out;
	190
	191	unsigned int capture_flags;
	192
	193	enum rle_state rle;
	194
29d58767 DE	195	/** Whether to bypass the clock divider. */
	196	gboolean bypass_clockdiv;
	197
e0df15d4 DE	198	/* Payload data buffers for incoming and outgoing transfers. */
e0df15d4 DE	199	uint32_t xfer_buf_in[MAX_ACQ_RECV_LEN];
5874e88d	200	uint16_t xfer_buf_out[MAX_ACQ_SEND_WORDS];
5874e88d DE	201
5874e88d DE	202	/* Payload buffer for sigrok logic packets. */
2cfd16a3	203	uint8_t out_packet[PACKET_LENGTH * UNIT_SIZE];
5874e88d DE	204	};
	205
	206	/** Private, per-device-instance driver context.
	207	*/
aeaad0b0	208	struct dev_context {
5874e88d DE	209	/** The samplerate selected by the user. */
	210	uint64_t samplerate;
	211
29d58767 DE	212	/** The maximimum sampling duration, in milliseconds. */
	213	uint64_t limit_msec;
	214
5874e88d DE	215	/** The maximimum number of samples to acquire. */
	216	uint64_t limit_samples;
	217
	218	/** Channels to use. */
	219	uint64_t channel_mask;
	220
	221	uint64_t trigger_mask;
	222	uint64_t trigger_edge_mask;
	223	uint64_t trigger_values;
aeaad0b0	224
5874e88d	225	struct acquisition_state *acquisition;
aeaad0b0	226
5874e88d DE	227	struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
	228	int reg_write_pos;
	229	int reg_write_len;
aeaad0b0	230
5874e88d	231	enum device_state state;
aeaad0b0	232
6358f0a9 DE	233	/** The currently active clock configuration of the device. */
	234	enum clock_config cur_clock_config;
	235
	236	/** Clock source configuration setting. */
	237	enum clock_source cfg_clock_source;
	238	/** Clock edge configuration setting. */
	239	enum signal_edge cfg_clock_edge;
5874e88d	240
e6e54bd2 DE	241	/** Trigger source configuration setting. */
	242	enum trigger_source cfg_trigger_source;
	243	/** Trigger slope configuration setting. */
6358f0a9	244	enum signal_edge cfg_trigger_slope;
e6e54bd2	245
5874e88d DE	246	/* Indicates that stopping the acquisition is currently in progress. */
	247	gboolean stopping_in_progress;
	248
	249	/* Indicates whether a transfer failed. */
	250	gboolean transfer_error;
aeaad0b0 DE	251	};
aeaad0b0 DE	252
5874e88d DE	253	SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
	254	SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);
	255
	256	SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
6358f0a9	257	SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi);
5874e88d DE	258	SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
	259	SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
	260	SR_PRIV int lwla_abort_acquisition(const struct sr_dev_inst *sdi);
	261
	262	SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data);
aeaad0b0	263
5874e88d	264	#endif /* !LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H */