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c463dcf0 MC |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
fec7aa6a MC |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
c463dcf0 MC |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
23 | ||
15abcf0f MC |
24 | #include <stdint.h> |
25 | #include <string.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <stdio.h> | |
29 | #include <errno.h> | |
30 | #include <math.h> | |
31 | #include "libsigrok.h" | |
32 | #include "libsigrok-internal.h" | |
33 | ||
34 | #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream" | |
35 | #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream" | |
36 | ||
7b5daad4 MC |
37 | #define MAX_SAMPLE_RATE SR_MHZ(100) |
38 | #define MAX_4CH_SAMPLE_RATE SR_MHZ(50) | |
39 | #define MAX_7CH_SAMPLE_RATE SR_MHZ(40) | |
40 | #define MAX_8CH_SAMPLE_RATE SR_MHZ(32) | |
41 | #define MAX_10CH_SAMPLE_RATE SR_MHZ(25) | |
42 | #define MAX_13CH_SAMPLE_RATE SR_MHZ(16) | |
43 | ||
44 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
45 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
46 | ||
15abcf0f MC |
47 | #define COMMAND_START_ACQUISITION 1 |
48 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
49 | #define COMMAND_WRITE_EEPROM 6 | |
50 | #define COMMAND_READ_EEPROM 7 | |
51 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
52 | #define COMMAND_SET_LED_MODE 0x7b | |
53 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
54 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
55 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
56 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
57 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
58 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
59 | #define COMMAND_GET_REVID 0x82 | |
60 | ||
61 | #define WRITE_EEPROM_COOKIE1 0x42 | |
62 | #define WRITE_EEPROM_COOKIE2 0x55 | |
63 | #define READ_EEPROM_COOKIE1 0x33 | |
64 | #define READ_EEPROM_COOKIE2 0x81 | |
65 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
66 | ||
7b5daad4 MC |
67 | #define MAX_EMPTY_TRANSFERS 64 |
68 | ||
15abcf0f MC |
69 | |
70 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
71 | { | |
72 | uint8_t state1 = 0x9b, state2 = 0x54; | |
73 | int i; | |
74 | ||
75 | for (i=0; i<cnt; i++) { | |
76 | uint8_t t, v = src[i]; | |
77 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; | |
78 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
79 | dest[i] = state2 = t; | |
80 | state1 = v; | |
81 | } | |
82 | } | |
83 | ||
84 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
85 | { | |
86 | uint8_t state1 = 0x9b, state2 = 0x54; | |
87 | int i; | |
88 | for (i=0; i<cnt; i++) { | |
89 | uint8_t t, v = src[i]; | |
90 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; | |
91 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
92 | dest[i] = state1 = t; | |
93 | state2 = v; | |
94 | } | |
95 | } | |
96 | ||
97 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
98 | const uint8_t *command, uint8_t cmd_len, | |
99 | uint8_t *reply, uint8_t reply_len) | |
100 | { | |
101 | uint8_t buf[64]; | |
102 | struct sr_usb_dev_inst *usb; | |
103 | int ret, xfer; | |
104 | ||
105 | usb = sdi->conn; | |
106 | ||
107 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
108 | command == NULL || (reply_len > 0 && reply == NULL)) | |
109 | return SR_ERR_ARG; | |
110 | ||
111 | encrypt(buf, command, cmd_len); | |
112 | ||
113 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
114 | if (ret != 0) { | |
115 | sr_dbg("Failed to send EP1 command 0x%02x: %s", | |
116 | command[0], libusb_error_name(ret)); | |
117 | return SR_ERR; | |
118 | } | |
119 | if (xfer != cmd_len) { | |
120 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length %d != %d", | |
121 | xfer, cmd_len); | |
122 | return SR_ERR; | |
123 | } | |
124 | ||
125 | if (reply_len == 0) | |
126 | return SR_OK; | |
127 | ||
128 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, &xfer, 1000); | |
129 | if (ret != 0) { | |
130 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s", | |
131 | command[0], libusb_error_name(ret)); | |
132 | return SR_ERR; | |
133 | } | |
134 | if (xfer != reply_len) { | |
135 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: incorrect length %d != %d", | |
136 | xfer, reply_len); | |
137 | return SR_ERR; | |
138 | } | |
139 | ||
140 | decrypt(reply, buf, reply_len); | |
141 | ||
142 | return SR_OK; | |
143 | } | |
144 | ||
145 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
146 | uint8_t address, uint8_t length, uint8_t *buf) | |
147 | { | |
148 | uint8_t command[5] = { | |
149 | COMMAND_READ_EEPROM, | |
150 | READ_EEPROM_COOKIE1, | |
151 | READ_EEPROM_COOKIE2, | |
152 | address, | |
153 | length, | |
154 | }; | |
155 | ||
156 | return do_ep1_command(sdi, command, 5, buf, length); | |
157 | } | |
158 | ||
159 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
160 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
161 | { | |
162 | uint8_t command[64]; | |
163 | int ret; | |
164 | ||
165 | if (cnt < 1 || cnt+offset > 64 || table == NULL) | |
166 | return SR_ERR_ARG; | |
167 | ||
168 | while (cnt > 0) { | |
169 | uint8_t chunk = (cnt > 32? 32 : cnt); | |
170 | ||
171 | command[0] = COMMAND_WRITE_LED_TABLE; | |
172 | command[1] = offset; | |
173 | command[2] = chunk; | |
174 | memcpy(command+3, table, chunk); | |
175 | ||
176 | if ((ret = do_ep1_command(sdi, command, 3+chunk, NULL, 0)) != SR_OK) | |
177 | return ret; | |
178 | ||
179 | table += chunk; | |
180 | offset += chunk; | |
181 | cnt -= chunk; | |
182 | } | |
183 | ||
184 | return SR_OK; | |
185 | } | |
186 | ||
187 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
188 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
189 | uint8_t repeat) | |
190 | { | |
191 | uint8_t command[6] = { | |
192 | COMMAND_SET_LED_MODE, | |
193 | animate, | |
194 | t2reload&0xff, | |
195 | t2reload>>8, | |
196 | div, | |
197 | repeat, | |
198 | }; | |
199 | ||
200 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
201 | } | |
202 | ||
203 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
204 | uint8_t address, uint8_t *value) | |
205 | { | |
206 | uint8_t command[3] = { | |
207 | COMMAND_FPGA_READ_REGISTER, | |
208 | 1, | |
209 | address, | |
210 | }; | |
211 | ||
212 | return do_ep1_command(sdi, command, 3, value, 1); | |
213 | } | |
214 | ||
215 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
216 | uint8_t (*regs)[2], uint8_t cnt) | |
217 | { | |
218 | uint8_t command[64]; | |
219 | int i; | |
220 | ||
221 | if (cnt < 1 || cnt > 31) | |
222 | return SR_ERR_ARG; | |
223 | ||
224 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
225 | command[1] = cnt; | |
226 | for (i=0; i<cnt; i++) { | |
227 | command[2+2*i] = regs[i][0]; | |
228 | command[3+2*i] = regs[i][1]; | |
229 | } | |
230 | ||
231 | return do_ep1_command(sdi, command, 2*(cnt+1), NULL, 0); | |
232 | } | |
233 | ||
234 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
235 | uint8_t address, uint8_t value) | |
236 | { | |
237 | uint8_t regs[2] = { address, value }; | |
238 | return write_fpga_registers(sdi, ®s, 1); | |
239 | } | |
240 | ||
241 | ||
242 | static uint8_t map_eeprom_data(uint8_t v) | |
243 | { | |
244 | /* ??? */ | |
245 | switch (v) { | |
246 | case 0x00: return 0x7a; | |
247 | case 0x01: return 0x79; | |
248 | case 0x05: return 0x85; | |
249 | case 0x10: return 0x6a; | |
250 | case 0x11: return 0x69; | |
251 | case 0x14: return 0x76; | |
252 | case 0x15: return 0x75; | |
253 | case 0x41: return 0x39; | |
254 | case 0x50: return 0x2a; | |
255 | case 0x51: return 0x29; | |
256 | case 0x55: return 0x35; | |
257 | default: | |
258 | sr_err("No mapping of 0x%02x defined", v); | |
259 | return 0xff; | |
260 | } | |
261 | } | |
262 | ||
263 | static int prime_fpga(const struct sr_dev_inst *sdi) | |
264 | { | |
265 | uint8_t eeprom_data[16]; | |
266 | uint8_t old_reg_10, status; | |
267 | uint8_t regs[8][2] = { | |
268 | {10, 0x00}, | |
269 | {10, 0x40}, | |
270 | {12, 0}, | |
271 | {10, 0xc0}, | |
272 | {10, 0x40}, | |
273 | { 6, 0}, | |
274 | { 7, 1}, | |
275 | { 7, 0} | |
276 | }; | |
277 | int i, ret; | |
278 | ||
279 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
280 | return ret; | |
281 | ||
282 | if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK) | |
283 | return ret; | |
284 | ||
285 | for (i=0; i<16; i++) { | |
286 | regs[2][1] = eeprom_data[i]; | |
287 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
288 | if (i) | |
289 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
290 | else | |
291 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
292 | if (ret != SR_OK) | |
293 | return ret; | |
294 | } | |
295 | ||
296 | if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK) | |
297 | return ret; | |
298 | ||
299 | if ((ret = read_fpga_register(sdi, 0, &status)) != SR_OK) | |
300 | return ret; | |
301 | ||
302 | if (status != 0x10) { | |
303 | sr_err("Invalid FPGA status: 0x%02x != 0x10", status); | |
304 | return SR_ERR; | |
305 | } | |
306 | ||
307 | return SR_OK; | |
308 | } | |
309 | ||
310 | static void make_heartbeat(uint8_t *table, int len) | |
311 | { | |
312 | int i, j; | |
313 | ||
314 | memset(table, 0, len); | |
315 | len >>= 3; | |
316 | for (i=0; i<2; i++) | |
317 | for (j=0; j<len; j++) | |
318 | *table++ = sin(j*M_PI/len)*255; | |
319 | } | |
320 | ||
321 | static int configure_led(const struct sr_dev_inst *sdi) | |
322 | { | |
323 | uint8_t table[64]; | |
324 | int ret; | |
325 | ||
326 | make_heartbeat(table, 64); | |
327 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
328 | return ret; | |
329 | ||
330 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
331 | } | |
332 | ||
333 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
334 | enum voltage_range vrange) | |
335 | { | |
336 | struct dev_context *devc; | |
337 | int offset, chunksize, ret; | |
338 | const char *filename; | |
339 | FILE *fw; | |
340 | unsigned char buf[256*62]; | |
341 | ||
342 | devc = sdi->priv; | |
343 | ||
344 | if (devc->cur_voltage_range == vrange) | |
345 | return SR_OK; | |
346 | ||
347 | switch (vrange) { | |
348 | case VOLTAGE_RANGE_18_33_V: | |
349 | filename = FPGA_FIRMWARE_18; | |
350 | break; | |
351 | case VOLTAGE_RANGE_5_V: | |
352 | filename = FPGA_FIRMWARE_33; | |
353 | break; | |
354 | default: | |
355 | sr_err("Unsupported voltage range"); | |
356 | return SR_ERR; | |
357 | } | |
358 | ||
359 | sr_info("Uploading FPGA bitstream at %s", filename); | |
360 | if ((fw = g_fopen(filename, "rb")) == NULL) { | |
361 | sr_err("Unable to open bitstream file %s for reading: %s", | |
362 | filename, strerror(errno)); | |
363 | return SR_ERR; | |
364 | } | |
365 | ||
366 | buf[0] = COMMAND_FPGA_UPLOAD_INIT; | |
367 | if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) { | |
368 | fclose(fw); | |
369 | return ret; | |
370 | } | |
371 | ||
372 | while (1) { | |
373 | chunksize = fread(buf, 1, sizeof(buf), fw); | |
374 | if (chunksize == 0) | |
375 | break; | |
376 | ||
377 | for (offset = 0; offset < chunksize; offset += 62) { | |
378 | uint8_t command[64]; | |
379 | uint8_t len = (offset + 62 > chunksize? | |
380 | chunksize - offset : 62); | |
381 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; | |
382 | command[1] = len; | |
383 | memcpy(command+2, buf+offset, len); | |
384 | if ((ret = do_ep1_command(sdi, command, len+2, NULL, 0)) != SR_OK) { | |
385 | fclose(fw); | |
386 | return ret; | |
387 | } | |
388 | } | |
389 | ||
390 | sr_info("Uploaded %d bytes", chunksize); | |
391 | } | |
392 | fclose(fw); | |
393 | sr_info("FPGA bitstream upload done"); | |
394 | ||
395 | if ((ret = prime_fpga(sdi)) != SR_OK) | |
396 | return ret; | |
397 | ||
398 | if ((ret = configure_led(sdi)) != SR_OK) | |
399 | return ret; | |
400 | ||
15abcf0f MC |
401 | devc->cur_voltage_range = vrange; |
402 | return SR_OK; | |
403 | } | |
404 | ||
7b5daad4 | 405 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) |
15abcf0f MC |
406 | { |
407 | static const uint8_t command[2] = { | |
408 | COMMAND_ABORT_ACQUISITION_SYNC, | |
409 | ABORT_ACQUISITION_SYNC_PATTERN, | |
410 | }; | |
411 | uint8_t reply, expected_reply; | |
412 | int ret; | |
413 | ||
414 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
415 | return ret; | |
416 | ||
417 | expected_reply = ~command[1]; | |
418 | if (reply != expected_reply) { | |
419 | sr_err("Invalid response for abort acquisition command: " | |
420 | "0x%02x != 0x%02x", reply, expected_reply); | |
421 | return SR_ERR; | |
422 | } | |
423 | ||
424 | return SR_OK; | |
425 | } | |
426 | ||
7b5daad4 MC |
427 | SR_PRIV int saleae_logic16_setup_acquisition(const struct sr_dev_inst *sdi, |
428 | uint64_t samplerate, | |
429 | uint16_t channels) | |
430 | { | |
431 | uint8_t clock_select, reg1, reg10; | |
432 | uint64_t div; | |
433 | int i, ret, nchan = 0; | |
db11d7d2 MC |
434 | struct dev_context *devc; |
435 | ||
436 | devc = sdi->priv; | |
7b5daad4 MC |
437 | |
438 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
439 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
440 | return SR_ERR; | |
441 | } | |
442 | ||
443 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
444 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
445 | clock_select = 0; | |
446 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
447 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
448 | clock_select = 1; | |
449 | } else { | |
450 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
451 | return SR_ERR; | |
452 | } | |
453 | ||
454 | for (i=0; i<16; i++) | |
455 | if (channels & (1U<<i)) | |
456 | nchan++; | |
457 | ||
458 | if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) || | |
459 | (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) || | |
460 | (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) || | |
461 | (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) || | |
462 | (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) { | |
463 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
464 | "with this many channels.", samplerate); | |
465 | return SR_ERR; | |
466 | } | |
467 | ||
db11d7d2 MC |
468 | if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK) |
469 | return ret; | |
470 | ||
7b5daad4 MC |
471 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) |
472 | return ret; | |
473 | ||
474 | if (reg1 != 0x08) { | |
475 | sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08", reg1); | |
476 | return SR_ERR; | |
477 | } | |
478 | ||
479 | if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) | |
480 | return ret; | |
481 | ||
482 | if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK) | |
483 | return ret; | |
484 | ||
485 | if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div-1))) != SR_OK) | |
486 | return ret; | |
487 | ||
488 | if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK) | |
489 | return ret; | |
490 | ||
491 | if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK) | |
492 | return ret; | |
493 | ||
494 | if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK) | |
495 | return ret; | |
496 | ||
497 | if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) | |
498 | return ret; | |
499 | ||
500 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
501 | return ret; | |
502 | ||
503 | if (reg1 != 0x48) { | |
504 | sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48", reg1); | |
505 | return SR_ERR; | |
506 | } | |
507 | ||
508 | if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK) | |
509 | return ret; | |
510 | ||
511 | if (reg10 != clock_select) { | |
512 | sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x", | |
513 | reg10, (unsigned)clock_select); | |
514 | return SR_ERR; | |
515 | } | |
516 | ||
517 | return SR_OK; | |
518 | } | |
519 | ||
520 | SR_PRIV int saleae_logic16_start_acquisition(const struct sr_dev_inst *sdi) | |
521 | { | |
522 | static const uint8_t command[1] = { | |
523 | COMMAND_START_ACQUISITION, | |
524 | }; | |
525 | int ret; | |
526 | ||
527 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
528 | return ret; | |
529 | ||
530 | return write_fpga_register(sdi, 1, 0x41); | |
531 | } | |
532 | ||
533 | SR_PRIV int saleae_logic16_abort_acquisition(const struct sr_dev_inst *sdi) | |
534 | { | |
535 | static const uint8_t command[1] = { | |
536 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
537 | }; | |
538 | int ret; | |
539 | uint8_t reg1, reg8, reg9; | |
540 | ||
541 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
542 | return ret; | |
543 | ||
544 | if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK) | |
545 | return ret; | |
546 | ||
547 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
548 | return ret; | |
549 | ||
550 | if (reg1 != 0x08) { | |
551 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08", reg1); | |
552 | return SR_ERR; | |
553 | } | |
554 | ||
555 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
556 | return ret; | |
557 | ||
558 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
559 | return ret; | |
560 | ||
561 | return SR_OK; | |
562 | } | |
563 | ||
15abcf0f MC |
564 | SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi) |
565 | { | |
566 | struct dev_context *devc; | |
567 | int ret; | |
568 | ||
569 | devc = sdi->priv; | |
570 | ||
571 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
572 | ||
7b5daad4 | 573 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) |
15abcf0f MC |
574 | return ret; |
575 | ||
576 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
577 | return ret; | |
578 | ||
db11d7d2 | 579 | if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK) |
15abcf0f MC |
580 | return ret; |
581 | ||
582 | return SR_OK; | |
583 | } | |
584 | ||
7b5daad4 MC |
585 | static void finish_acquisition(struct dev_context *devc) |
586 | { | |
587 | struct sr_datafeed_packet packet; | |
588 | int i; | |
589 | ||
590 | /* Terminate session. */ | |
591 | packet.type = SR_DF_END; | |
592 | sr_session_send(devc->cb_data, &packet); | |
593 | ||
594 | /* Remove fds from polling. */ | |
595 | if (devc->usbfd != NULL) { | |
596 | for (i = 0; devc->usbfd[i] != -1; i++) | |
597 | sr_source_remove(devc->usbfd[i]); | |
598 | g_free(devc->usbfd); | |
599 | } | |
600 | ||
601 | devc->num_transfers = 0; | |
602 | g_free(devc->transfers); | |
603 | g_free(devc->convbuffer); | |
604 | } | |
605 | ||
606 | static void free_transfer(struct libusb_transfer *transfer) | |
607 | { | |
608 | struct dev_context *devc; | |
609 | unsigned int i; | |
610 | ||
611 | devc = transfer->user_data; | |
612 | ||
613 | g_free(transfer->buffer); | |
614 | transfer->buffer = NULL; | |
615 | libusb_free_transfer(transfer); | |
616 | ||
617 | for (i = 0; i < devc->num_transfers; i++) { | |
618 | if (devc->transfers[i] == transfer) { | |
619 | devc->transfers[i] = NULL; | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
624 | devc->submitted_transfers--; | |
625 | if (devc->submitted_transfers == 0) | |
626 | finish_acquisition(devc); | |
627 | } | |
628 | ||
629 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
630 | { | |
631 | int ret; | |
632 | ||
633 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
634 | return; | |
635 | ||
636 | free_transfer(transfer); | |
637 | /* TODO: Stop session? */ | |
638 | ||
639 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
640 | } | |
641 | ||
642 | static size_t convert_sample_data(struct dev_context *devc, | |
643 | uint8_t *dest, size_t destcnt, | |
644 | const uint8_t *src, size_t srccnt) | |
c463dcf0 | 645 | { |
7b5daad4 MC |
646 | uint16_t *channel_data; |
647 | int i, cur_channel; | |
648 | size_t ret = 0; | |
649 | ||
650 | srccnt /= 2; | |
651 | ||
652 | channel_data = devc->channel_data; | |
653 | cur_channel = devc->cur_channel; | |
654 | ||
655 | while(srccnt--) { | |
656 | uint16_t sample, channel_mask; | |
657 | ||
658 | sample = src[0] | (src[1] << 8); | |
659 | src += 2; | |
660 | ||
661 | channel_mask = devc->channel_masks[cur_channel]; | |
662 | ||
663 | for (i=15; i>=0; --i, sample >>= 1) | |
664 | if (sample & 1) | |
665 | channel_data[i] |= channel_mask; | |
666 | ||
667 | if (++cur_channel == devc->num_channels) { | |
668 | cur_channel = 0; | |
669 | if (destcnt < 16*2) { | |
670 | sr_err("Conversion buffer too small!"); | |
671 | break; | |
672 | } | |
673 | memcpy(dest, channel_data, 16*2); | |
674 | memset(channel_data, 0, 16*2); | |
675 | dest += 16*2; | |
676 | ret += 16*2; | |
677 | destcnt -= 16*2; | |
678 | } | |
679 | } | |
680 | ||
681 | devc->cur_channel = cur_channel; | |
c463dcf0 | 682 | |
7b5daad4 MC |
683 | return ret; |
684 | } | |
685 | ||
686 | SR_PRIV void saleae_logic16_receive_transfer(struct libusb_transfer *transfer) | |
687 | { | |
688 | gboolean packet_has_error = FALSE; | |
689 | struct sr_datafeed_packet packet; | |
690 | struct sr_datafeed_logic logic; | |
c463dcf0 | 691 | struct dev_context *devc; |
7b5daad4 MC |
692 | size_t converted_length; |
693 | ||
694 | devc = transfer->user_data; | |
695 | ||
696 | /* | |
697 | * If acquisition has already ended, just free any queued up | |
698 | * transfer that come in. | |
699 | */ | |
700 | if (devc->num_samples < 0) { | |
701 | free_transfer(transfer); | |
702 | return; | |
703 | } | |
704 | ||
705 | sr_info("receive_transfer(): status %d received %d bytes.", | |
706 | transfer->status, transfer->actual_length); | |
707 | ||
708 | switch (transfer->status) { | |
709 | case LIBUSB_TRANSFER_NO_DEVICE: | |
710 | devc->num_samples = -2; | |
711 | free_transfer(transfer); | |
712 | return; | |
713 | case LIBUSB_TRANSFER_COMPLETED: | |
714 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
715 | break; | |
716 | default: | |
717 | packet_has_error = TRUE; | |
718 | break; | |
719 | } | |
c463dcf0 | 720 | |
7b5daad4 MC |
721 | if (transfer->actual_length & 1) { |
722 | sr_err("Got an odd number of bytes from the device. This should not happen."); | |
723 | /* Bail out right away */ | |
724 | packet_has_error = TRUE; | |
725 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
726 | } | |
c463dcf0 | 727 | |
7b5daad4 MC |
728 | if (transfer->actual_length == 0 || packet_has_error) { |
729 | devc->empty_transfer_count++; | |
730 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
731 | /* | |
732 | * The FX2 gave up. End the acquisition, the frontend | |
733 | * will work out that the samplecount is short. | |
734 | */ | |
735 | devc->num_samples = -2; | |
736 | free_transfer(transfer); | |
737 | } else { | |
738 | resubmit_transfer(transfer); | |
739 | } | |
740 | return; | |
741 | } else { | |
742 | devc->empty_transfer_count = 0; | |
743 | } | |
c463dcf0 | 744 | |
7b5daad4 MC |
745 | converted_length = |
746 | convert_sample_data(devc, | |
747 | devc->convbuffer, devc->convbuffer_size, | |
748 | transfer->buffer, transfer->actual_length); | |
749 | ||
750 | if (converted_length > 0) { | |
751 | /* Send the incoming transfer to the session bus. */ | |
752 | packet.type = SR_DF_LOGIC; | |
753 | packet.payload = &logic; | |
754 | logic.length = converted_length; | |
755 | logic.unitsize = 2; | |
756 | logic.data = devc->convbuffer; | |
757 | sr_session_send(devc->cb_data, &packet); | |
758 | ||
759 | devc->num_samples += converted_length / 2; | |
760 | if (devc->limit_samples && | |
761 | (uint64_t)devc->num_samples > devc->limit_samples) { | |
762 | devc->num_samples = -2; | |
763 | free_transfer(transfer); | |
764 | return; | |
765 | } | |
c463dcf0 MC |
766 | } |
767 | ||
7b5daad4 | 768 | resubmit_transfer(transfer); |
c463dcf0 | 769 | } |