projects / libsigrok.git / blame
| Commit | Line | Data |
|---|---|---|
| 01cf8814 DR |
1 | /* |
| 2 | * This file is part of the sigrok project. | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> | |
| 5 | * | |
| 6 | * This program is free software: you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation, either version 3 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef LINK_MSO19_H | |
| 13 | #define LINK_MSO19_H | |
| 14 | ||
| 15 | /* our private per-instance data */ | |
| 16 | struct mso { | |
| 17 | /* info */ | |
| 18 | uint8_t hwmodel; | |
| 19 | uint8_t hwrev; | |
| 20 | uint32_t serial; | |
| 21 | // uint8_t num_sample_rates; | |
| 22 | /* calibration */ | |
| 23 | double vbit; | |
| 24 | uint16_t dac_offset; | |
| 25 | uint16_t offset_range; | |
| 26 | /* register cache */ | |
| 27 | uint8_t ctlbase; | |
| 28 | uint8_t slowmode; | |
| 29 | /* state */ | |
| 30 | uint8_t la_threshold; | |
| 31 | uint64_t cur_rate; | |
| 32 | uint8_t dso_probe_attn; | |
| 33 | uint8_t trigger_chan; | |
| 34 | uint8_t trigger_slope; | |
| 35 | uint8_t trigger_spimode; | |
| 36 | uint8_t trigger_outsrc; | |
| 37 | uint8_t trigger_state; | |
| 38 | uint8_t la_trigger; | |
| 39 | uint8_t la_trigger_mask; | |
| 40 | double dso_trigger_voltage; | |
| 41 | uint16_t dso_trigger_width; | |
| 42 | gpointer session_id; | |
| 43 | uint16_t buffer_n; | |
| 44 | char buffer[4096]; | |
| 45 | }; | |
| 46 | ||
| 47 | /* serial protocol */ | |
| 48 | #define mso_trans(a, v) \ | |
| 49 | (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \ | |
| 50 | ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7)) | |
| 51 | ||
| 52 | const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e }; | |
| 53 | const char mso_foot[] = { 0x7e }; | |
| 54 | ||
| 55 | /* registers */ | |
| 56 | #define REG_BUFFER 1 | |
| 57 | #define REG_TRIGGER 2 | |
| 58 | #define REG_CLKRATE1 9 | |
| 59 | #define REG_CLKRATE2 10 | |
| 60 | #define REG_DAC1 12 | |
| 61 | #define REG_DAC2 13 | |
| 62 | #define REG_CTL 14 | |
| 63 | ||
| 64 | /* bits */ | |
| 65 | #define BIT_CTL_RESETFSM (1 << 0) | |
| 66 | #define BIT_CTL_ARM (1 << 1) | |
| 67 | #define BIT_CTL_ADC_UNKNOWN4 (1 << 4) /* adc enable? */ | |
| 68 | #define BIT_CTL_RESETADC (1 << 6) | |
| 69 | #define BIT_CTL_LED (1 << 7) | |
| 70 | ||
| 71 | struct rate_map { | |
| 72 | uint32_t rate; | |
| 73 | uint16_t val; | |
| 74 | uint8_t slowmode; | |
| 75 | }; | |
| 76 | ||
| 77 | static struct rate_map rate_map[] = { | |
| 78 | { MHZ(200), 0x0205, 0 }, | |
| 79 | { MHZ(100), 0x0105, 0 }, | |
| 80 | { MHZ(50), 0x0005, 0 }, | |
| 81 | { MHZ(20), 0x0303, 0 }, | |
| 82 | { MHZ(10), 0x0308, 0 }, | |
| 83 | { MHZ(5), 0x030c, 0 }, | |
| 84 | { MHZ(2), 0x0330, 0 }, | |
| 85 | { MHZ(1), 0x0362, 0 }, | |
| 86 | { KHZ(500), 0x03c6, 0 }, | |
| 87 | { KHZ(200), 0x07f2, 0 }, | |
| 88 | { KHZ(100), 0x0fe6, 0 }, | |
| 89 | { KHZ(50), 0x1fce, 0 }, | |
| 90 | { KHZ(20), 0x4f86, 0 }, | |
| 91 | { KHZ(10), 0x9f0e, 0 }, | |
| 92 | { KHZ(5), 0x03c7, 0x20 }, | |
| 93 | { KHZ(2), 0x07f3, 0x20 }, | |
| 94 | { KHZ(1), 0x0fe7, 0x20 }, | |
| 95 | { 500, 0x1fcf, 0x20 }, | |
| 96 | { 200, 0x4f87, 0x20 }, | |
| 97 | { 100, 0x9f0f, 0x20 }, | |
| 98 | }; | |
| 99 | ||
| 100 | /* FIXME: Determine corresponding voltages */ | |
| 101 | uint16_t la_threshold_map[] = { | |
| 102 | 0x8600, | |
| 103 | 0x8770, | |
| 104 | 0x88ff, | |
| 105 | 0x8c70, | |
| 106 | 0x8eff, | |
| 107 | 0x8fff, | |
| 108 | }; | |
| 109 | #endif | |
| 110 |