]>
Commit | Line | Data |
---|---|---|
d4026957 | 1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com> | |
6 | ## Copyright (C) 2014 alberink <alberink@stampfini.org> | |
7 | ## | |
8 | ## This program is free software; you can redistribute it and/or modify | |
9 | ## it under the terms of the GNU General Public License as published by | |
10 | ## the Free Software Foundation; either version 2 of the License, or | |
11 | ## (at your option) any later version. | |
12 | ## | |
13 | ## This program is distributed in the hope that it will be useful, | |
14 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ## GNU General Public License for more details. | |
17 | ## | |
18 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 19 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
d4026957 | 20 | ## |
21 | ||
22 | import sigrokdecode as srd | |
23 | ||
24 | class Decoder(srd.Decoder): | |
b197383c | 25 | api_version = 3 |
d4026957 | 26 | id = 'tca6408a' |
98c47d11 UH |
27 | name = 'TI TCA6408A' |
28 | longname = 'Texas Instruments TCA6408A' | |
d4026957 | 29 | desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.' |
30 | license = 'gplv2+' | |
31 | inputs = ['i2c'] | |
6cbba91f | 32 | outputs = [] |
d6d8a8a4 | 33 | tags = ['Embedded/industrial', 'IC'] |
d4026957 | 34 | annotations = ( |
35 | ('register', 'Register type'), | |
36 | ('value', 'Register value'), | |
37 | ('warnings', 'Warning messages'), | |
38 | ) | |
39 | annotation_rows = ( | |
40 | ('regs', 'Registers', (0, 1)), | |
41 | ('warnings', 'Warnings', (2,)), | |
42 | ) | |
43 | ||
92b7b49f | 44 | def __init__(self): |
10aeb8ea GS |
45 | self.reset() |
46 | ||
47 | def reset(self): | |
d4026957 | 48 | self.state = 'IDLE' |
49 | self.chip = -1 | |
50 | ||
51 | def start(self): | |
52 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
53 | ||
54 | def putx(self, data): | |
55 | self.put(self.ss, self.es, self.out_ann, data) | |
56 | ||
57 | def handle_reg_0x00(self, b): | |
58 | self.putx([1, ['State of inputs: %02X' % b]]) | |
59 | ||
60 | def handle_reg_0x01(self, b): | |
61 | self.putx([1, ['Outputs set: %02X' % b ]]) | |
62 | ||
63 | def handle_reg_0x02(self, b): | |
64 | self.putx([1, ['Polarity inverted: %02X' % b]]) | |
65 | ||
66 | def handle_reg_0x03(self, b): | |
67 | self.putx([1, ['Configuration: %02X' % b]]) | |
68 | ||
69 | def handle_write_reg(self, b): | |
70 | if b == 0: | |
71 | self.putx([0, ['Input port', 'In', 'I']]) | |
72 | elif b == 1: | |
73 | self.putx([0, ['Output port', 'Out', 'O']]) | |
74 | elif b == 2: | |
75 | self.putx([0, ['Polarity inversion register', 'Pol', 'P']]) | |
76 | elif b == 3: | |
77 | self.putx([0, ['Configuration register', 'Conf', 'C']]) | |
78 | ||
79 | def check_correct_chip(self, addr): | |
80 | if addr not in (0x20, 0x21): | |
81 | self.putx([2, ['Warning: I²C slave 0x%02X not a TCA6408A ' | |
82 | 'compatible chip.' % addr]]) | |
83 | self.state = 'IDLE' | |
84 | ||
85 | def decode(self, ss, es, data): | |
86 | cmd, databyte = data | |
87 | ||
88 | # Store the start/end samples of this I²C packet. | |
89 | self.ss, self.es = ss, es | |
90 | ||
91 | # State machine. | |
92 | if self.state == 'IDLE': | |
93 | # Wait for an I²C START condition. | |
94 | if cmd != 'START': | |
95 | return | |
96 | self.state = 'GET SLAVE ADDR' | |
d4026957 | 97 | elif self.state == 'GET SLAVE ADDR': |
18101a31 | 98 | self.chip = databyte |
d4026957 | 99 | self.state = 'GET REG ADDR' |
100 | elif self.state == 'GET REG ADDR': | |
101 | # Wait for a data write (master selects the slave register). | |
102 | if cmd in ('ADDRESS READ', 'ADDRESS WRITE'): | |
103 | self.check_correct_chip(databyte) | |
104 | if cmd != 'DATA WRITE': | |
105 | return | |
106 | self.reg = databyte | |
107 | self.handle_write_reg(self.reg) | |
108 | self.state = 'WRITE IO REGS' | |
109 | elif self.state == 'WRITE IO REGS': | |
110 | # If we see a Repeated Start here, the master wants to read. | |
111 | if cmd == 'START REPEAT': | |
112 | self.state = 'READ IO REGS' | |
113 | return | |
114 | # Otherwise: Get data bytes until a STOP condition occurs. | |
115 | if cmd == 'DATA WRITE': | |
116 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
117 | handle_reg(databyte) | |
118 | elif cmd == 'STOP': | |
119 | self.state = 'IDLE' | |
120 | self.chip = -1 | |
121 | elif self.state == 'READ IO REGS': | |
122 | # Wait for an address read operation. | |
123 | if cmd == 'ADDRESS READ': | |
124 | self.state = 'READ IO REGS2' | |
125 | self.chip = databyte | |
126 | return | |
127 | elif self.state == 'READ IO REGS2': | |
128 | if cmd == 'DATA READ': | |
129 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
130 | handle_reg(databyte) | |
131 | elif cmd == 'STOP': | |
132 | self.state = 'IDLE' |