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1a751158 DS |
1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2016 Daniel Schulte <trilader@schroedingers-bit.net> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
1a751158 DS |
18 | ## |
19 | ||
20 | import sigrokdecode as srd | |
37a2cca9 | 21 | from collections import namedtuple |
1a751158 DS |
22 | |
23 | class Ann: | |
37a2cca9 UH |
24 | BIT, START, STOP, PARITY_OK, PARITY_ERR, DATA, WORD = range(7) |
25 | ||
26 | Bit = namedtuple('Bit', 'val ss es') | |
1a751158 DS |
27 | |
28 | class Decoder(srd.Decoder): | |
29 | api_version = 2 | |
30 | id = 'ps2' | |
31 | name = 'PS/2' | |
32 | longname = 'PS/2' | |
33 | desc = 'PS/2 keyboard/mouse interface.' | |
34 | license = 'gplv2+' | |
35 | inputs = ['logic'] | |
36 | outputs = ['ps2'] | |
f90269a3 | 37 | channels = ( |
1a751158 DS |
38 | {'id': 'clk', 'name': 'Clock', 'desc': 'Clock line'}, |
39 | {'id': 'data', 'name': 'Data', 'desc': 'Data line'}, | |
40 | ) | |
41 | annotations = ( | |
37a2cca9 | 42 | ('bit', 'Bit'), |
1a751158 DS |
43 | ('start-bit', 'Start bit'), |
44 | ('stop-bit', 'Stop bit'), | |
37a2cca9 UH |
45 | ('parity-ok', 'Parity OK bit'), |
46 | ('parity-err', 'Parity error bit'), | |
47 | ('data-bit', 'Data bit'), | |
48 | ('word', 'Word'), | |
49 | ) | |
50 | annotation_rows = ( | |
51 | ('bits', 'Bits', (0,)), | |
52 | ('fields', 'Fields', (1, 2, 3, 4, 5, 6)), | |
1a751158 DS |
53 | ) |
54 | ||
55 | def __init__(self): | |
56 | self.bits = [] | |
57 | self.prev_pins = None | |
58 | self.prev_clock = None | |
59 | self.samplenum = 0 | |
1a751158 | 60 | self.clock_was_high = False |
37a2cca9 | 61 | self.bitcount = 0 |
1a751158 DS |
62 | |
63 | def start(self): | |
64 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
65 | ||
37a2cca9 UH |
66 | def putb(self, bit, ann_idx): |
67 | b = self.bits[bit] | |
68 | self.put(b.ss, b.es, self.out_ann, [ann_idx, [str(b.val)]]) | |
69 | ||
70 | def putx(self, bit, ann): | |
71 | self.put(self.bits[bit].ss, self.bits[bit].es, self.out_ann, ann) | |
72 | ||
1a751158 DS |
73 | def handle_bits(self, datapin): |
74 | # Ignore non start condition bits (useful during keyboard init). | |
37a2cca9 | 75 | if self.bitcount == 0 and datapin == 1: |
1a751158 DS |
76 | return |
77 | ||
37a2cca9 UH |
78 | # Store individual bits and their start/end samplenumbers. |
79 | self.bits.append(Bit(datapin, self.samplenum, self.samplenum)) | |
1a751158 | 80 | |
37a2cca9 UH |
81 | # Fix up end sample numbers of the bits. |
82 | if self.bitcount > 0: | |
83 | b = self.bits[self.bitcount - 1] | |
84 | self.bits[self.bitcount - 1] = Bit(b.val, b.ss, self.samplenum) | |
85 | if self.bitcount == 11: | |
86 | self.bitwidth = self.bits[1].es - self.bits[2].es | |
87 | b = self.bits[-1] | |
88 | self.bits[-1] = Bit(b.val, b.ss, b.es + self.bitwidth) | |
1a751158 DS |
89 | |
90 | # Find all 11 bits. Start + 8 data + odd parity + stop. | |
37a2cca9 UH |
91 | if self.bitcount < 11: |
92 | self.bitcount += 1 | |
1a751158 DS |
93 | return |
94 | ||
95 | # Extract data word. | |
96 | word = 0 | |
97 | for i in range(8): | |
37a2cca9 UH |
98 | word |= (self.bits[i + 1].val << i) |
99 | ||
100 | # Calculate parity. | |
101 | parity_ok = (bin(word).count('1') + self.bits[9].val) % 2 == 1 | |
102 | ||
103 | # Emit annotations. | |
104 | for i in range(11): | |
105 | self.putb(i, Ann.BIT) | |
106 | self.putx(0, [Ann.START, ['Start bit', 'Start', 'S']]) | |
107 | self.put(self.bits[1].ss, self.bits[8].es, self.out_ann, [Ann.WORD, | |
108 | ['Data: %02x' % word, 'D: %02x' % word, '%02x' % word]]) | |
109 | if parity_ok: | |
110 | self.putx(9, [Ann.PARITY_OK, ['Parity OK', 'Par OK', 'P']]) | |
1a751158 | 111 | else: |
37a2cca9 UH |
112 | self.putx(9, [Ann.PARITY_ERR, ['Parity error', 'Par err', 'PE']]) |
113 | self.putx(10, [Ann.STOP, ['Stop bit', 'Stop', 'St', 'T']]) | |
1a751158 | 114 | |
37a2cca9 | 115 | self.bits, self.bitcount = [], 0 |
1a751158 DS |
116 | |
117 | def find_clk_edge(self, clock_pin, data_pin): | |
118 | # Ignore sample if the clock pin hasn't changed. | |
119 | if clock_pin == self.prev_clock: | |
120 | return | |
121 | self.prev_clock = clock_pin | |
122 | ||
123 | # Sample on falling clock edge. | |
124 | if clock_pin == 1: | |
125 | return | |
126 | ||
127 | # Found the correct clock edge, now get the bits. | |
128 | self.handle_bits(data_pin) | |
129 | ||
130 | def decode(self, ss, es, data): | |
131 | for (self.samplenum, pins) in data: | |
132 | clock_pin, data_pin = pins[0], pins[1] | |
133 | ||
134 | # Ignore identical samples. | |
135 | if self.prev_pins == pins: | |
136 | continue | |
137 | self.prev_pins = pins | |
138 | ||
139 | if clock_pin == 0 and not self.clock_was_high: | |
140 | continue | |
141 | self.clock_was_high = True | |
142 | ||
143 | self.find_clk_edge(clock_pin, data_pin) |