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25e1418a UH |
1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
8eb06a59 | 4 | ## Copyright (C) 2013-2016 Uwe Hermann <uwe@hermann-uwe.de> |
25e1418a UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
25e1418a UH |
18 | ## |
19 | ||
25e1418a UH |
20 | import sigrokdecode as srd |
21 | ||
22 | ''' | |
c515eed7 | 23 | OUTPUT_PYTHON format: |
25e1418a UH |
24 | |
25 | Packet: | |
26 | [<ptype>, <pdata>] | |
27 | ||
28 | <ptype>, <pdata> | |
29 | - 'ITEM', [<item>, <itembitsize>] | |
30 | - 'WORD', [<word>, <wordbitsize>, <worditemcount>] | |
31 | ||
32 | <item>: | |
33 | - A single item (a number). It can be of arbitrary size. The max. number | |
34 | of bits in this item is specified in <itembitsize>. | |
35 | ||
36 | <itembitsize>: | |
37 | - The size of an item (in bits). For a 4-bit parallel bus this is 4, | |
38 | for a 16-bit parallel bus this is 16, and so on. | |
39 | ||
40 | <word>: | |
41 | - A single word (a number). It can be of arbitrary size. The max. number | |
42 | of bits in this word is specified in <wordbitsize>. The (exact) number | |
43 | of items in this word is specified in <worditemcount>. | |
44 | ||
45 | <wordbitsize>: | |
46 | - The size of a word (in bits). For a 2-item word with 8-bit items | |
47 | <wordbitsize> is 16, for a 3-item word with 4-bit items <wordbitsize> | |
48 | is 12, and so on. | |
49 | ||
50 | <worditemcount>: | |
51 | - The size of a word (in number of items). For a 4-item word (no matter | |
52 | how many bits each item consists of) <worditemcount> is 4, for a 7-item | |
53 | word <worditemcount> is 7, and so on. | |
54 | ''' | |
55 | ||
6a15597a | 56 | def channel_list(num_channels): |
8eafa261 | 57 | l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}] |
6a15597a | 58 | for i in range(num_channels): |
25e1418a UH |
59 | d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i} |
60 | l.append(d) | |
da9bcbd9 | 61 | return tuple(l) |
25e1418a | 62 | |
a573d394 UH |
63 | class ChannelError(Exception): |
64 | pass | |
65 | ||
8eb06a59 UH |
66 | NUM_CHANNELS = 8 |
67 | ||
25e1418a | 68 | class Decoder(srd.Decoder): |
8eb06a59 | 69 | api_version = 3 |
25e1418a UH |
70 | id = 'parallel' |
71 | name = 'Parallel' | |
72 | longname = 'Parallel sync bus' | |
73 | desc = 'Generic parallel synchronous bus.' | |
74 | license = 'gplv2+' | |
75 | inputs = ['logic'] | |
76 | outputs = ['parallel'] | |
8eb06a59 | 77 | optional_channels = channel_list(NUM_CHANNELS) |
84c1c0b5 BV |
78 | options = ( |
79 | {'id': 'clock_edge', 'desc': 'Clock edge to sample on', | |
80 | 'default': 'rising', 'values': ('rising', 'falling')}, | |
b0918d40 UH |
81 | {'id': 'wordsize', 'desc': 'Data wordsize', 'default': 1}, |
82 | {'id': 'endianness', 'desc': 'Data endianness', | |
84c1c0b5 BV |
83 | 'default': 'little', 'values': ('little', 'big')}, |
84 | ) | |
da9bcbd9 BV |
85 | annotations = ( |
86 | ('items', 'Items'), | |
87 | ('words', 'Words'), | |
88 | ) | |
25e1418a UH |
89 | |
90 | def __init__(self): | |
25e1418a UH |
91 | self.items = [] |
92 | self.itemcount = 0 | |
93 | self.saved_item = None | |
25e1418a UH |
94 | self.ss_item = self.es_item = None |
95 | self.first = True | |
8eb06a59 | 96 | self.num_channels = 0 |
25e1418a | 97 | |
b098b820 | 98 | def start(self): |
c515eed7 | 99 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
be465111 | 100 | self.out_ann = self.register(srd.OUTPUT_ANN) |
25e1418a | 101 | |
8eb06a59 UH |
102 | # Assume that the initial pin state of all pins is logic 1. |
103 | self.initial_pins = [1] * (NUM_CHANNELS + 1) | |
104 | ||
25e1418a | 105 | def putpb(self, data): |
c515eed7 | 106 | self.put(self.ss_item, self.es_item, self.out_python, data) |
25e1418a UH |
107 | |
108 | def putb(self, data): | |
109 | self.put(self.ss_item, self.es_item, self.out_ann, data) | |
110 | ||
111 | def putpw(self, data): | |
c515eed7 | 112 | self.put(self.ss_word, self.es_word, self.out_python, data) |
25e1418a UH |
113 | |
114 | def putw(self, data): | |
115 | self.put(self.ss_word, self.es_word, self.out_ann, data) | |
116 | ||
117 | def handle_bits(self, datapins): | |
118 | # If this is the first item in a word, save its sample number. | |
119 | if self.itemcount == 0: | |
120 | self.ss_word = self.samplenum | |
121 | ||
122 | # Get the bits for this item. | |
8eb06a59 | 123 | item, used_pins = 0, datapins.count(1) + datapins.count(0) |
25e1418a UH |
124 | for i in range(used_pins): |
125 | item |= datapins[i] << i | |
126 | ||
127 | self.items.append(item) | |
128 | self.itemcount += 1 | |
129 | ||
35b380b1 | 130 | if self.first: |
25e1418a UH |
131 | # Save the start sample and item for later (no output yet). |
132 | self.ss_item = self.samplenum | |
133 | self.first = False | |
134 | self.saved_item = item | |
135 | else: | |
136 | # Output the saved item (from the last CLK edge to the current). | |
137 | self.es_item = self.samplenum | |
138 | self.putpb(['ITEM', self.saved_item]) | |
139 | self.putb([0, ['%X' % self.saved_item]]) | |
140 | self.ss_item = self.samplenum | |
141 | self.saved_item = item | |
142 | ||
143 | endian, ws = self.options['endianness'], self.options['wordsize'] | |
144 | ||
145 | # Get as many items as the configured wordsize says. | |
146 | if self.itemcount < ws: | |
147 | return | |
148 | ||
c515eed7 | 149 | # Output annotations/python for a word (a collection of items). |
25e1418a UH |
150 | word = 0 |
151 | for i in range(ws): | |
152 | if endian == 'little': | |
153 | word |= self.items[i] << ((ws - 1 - i) * used_pins) | |
154 | elif endian == 'big': | |
155 | word |= self.items[i] << (i * used_pins) | |
156 | ||
157 | self.es_word = self.samplenum | |
158 | # self.putpw(['WORD', word]) | |
159 | # self.putw([1, ['%X' % word]]) | |
160 | self.ss_word = self.samplenum | |
161 | ||
162 | self.itemcount, self.items = 0, [] | |
163 | ||
8eb06a59 UH |
164 | def decode(self): |
165 | for i in range(len(self.optional_channels)): | |
166 | if self.has_channel(i): | |
167 | self.num_channels += 1 | |
168 | ||
169 | if self.num_channels == 0: | |
170 | raise ChannelError('At least one channel has to be supplied.') | |
171 | ||
172 | if not self.has_channel(0): | |
173 | # CLK was not supplied, sample on ANY edge of ANY of the pins | |
174 | # (but only of those pins that were actually supplied). | |
175 | conds = [] | |
176 | for i in range(1, len(self.optional_channels)): | |
177 | if self.has_channel(i): | |
178 | conds.append({i: 'e'}) | |
179 | while True: | |
fcd5d23a | 180 | self.handle_bits(self.wait(conds)[1:]) |
8eb06a59 UH |
181 | else: |
182 | # Sample on the rising or falling CLK edge (depends on config). | |
183 | while True: | |
184 | pins = self.wait({0: self.options['clock_edge'][0]}) | |
e28f7aee | 185 | self.handle_bits(pins[1:]) |