[libsigrokdecode.git] / decoders / onewire / onewire.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# 1-Wire protocol decoder

import sigrokdecode as srd

# Annotation feed formats
ANN_ASCII = 0
ANN_DEC = 1
ANN_HEX = 2
ANN_OCT = 3
ANN_BITS = 4

class Decoder(srd.Decoder):
    api_version = 1
    id = 'onewire'
    name = '1-Wire'
    longname = ''
    desc = '1-Wire bus and MicroLan'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['onewire']
    probes = [
        {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
    ]
    optional_probes = [
        {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
    ]
    options = {
        'overdrive': ['Overdrive', 0],
    }
    annotations = [
        ['ASCII', 'Data bytes as ASCII characters'],
        ['Decimal', 'Databytes as decimal, integer values'],
        ['Hex', 'Data bytes in hex format'],
        ['Octal', 'Data bytes as octal numbers'],
        ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
    ]

    def putx(self, data):
        self.put(self.startsample, self.samplenum - 1, self.out_ann, data)

    def __init__(self, **kwargs):
        # Common variables
        self.samplenum = 0
        # Link layer variables
        self.lnk_state = 'WAIT FOR EVENT'
        self.lnk_event = 'NONE'
        self.lnk_start = -1
        self.lnk_bit   = -1
        self.lnk_cnt   = 0
        self.lnk_byte  = -1
        # Network layer variables
        self.net_state = 'WAIT FOR EVENT'
        self.net_event = 'NONE'
        self.net_command = -1
        # Transport layer variables
        self.trn_state = 'WAIT FOR EVENT'
        self.trn_event = 'NONE'

        self.data_sample = -1
        self.cur_data_bit = 0
        self.databyte = 0
        self.startsample = -1

    def start(self, metadata):
        self.samplerate = metadata['samplerate']
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')

        # The width of the 1-Wire time base (30us) in number of samples.
        # TODO: optimize this value
        self.time_base = float(self.samplerate) / float(0.000030)

    def report(self):
        pass

    def get_data_sample(self, owr):
        # Skip samples until we're in the middle of the start bit.
        if not self.reached_data_sample():
            return

        self.data_sample = owr

        self.cur_data_bit = 0
        self.databyte = 0
        self.startsample = -1

        self.state = 'GET DATA BITS'

        self.put(self.cycle_start, self.samplenum, self.out_proto,
                 ['STARTBIT', self.startbit])
        self.put(self.cycle_start, self.samplenum, self.out_ann,
                 [ANN_ASCII, ['Start bit', 'Start', 'S']])

    def get_data_bits(self, owr):
        # Skip samples until we're in the middle of the desired data bit.
        if not self.reached_bit(self.cur_data_bit + 1):
            return

        # Save the sample number where the data byte starts.
        if self.startsample == -1:
            self.startsample = self.samplenum

        # Get the next data bit in LSB-first or MSB-first fashion.
        if self.options['bit_order'] == 'lsb-first':
            self.databyte >>= 1
            self.databyte |= \
                (owr << (self.options['num_data_bits'] - 1))
        elif self.options['bit_order'] == 'msb-first':
            self.databyte <<= 1
            self.databyte |= (owr << 0)
        else:
            raise Exception('Invalid bit order value: %s',
                            self.options['bit_order'])

        # Return here, unless we already received all data bits.
        # TODO? Off-by-one?
        if self.cur_data_bit < self.options['num_data_bits'] - 1:
            self.cur_data_bit += 1
            return

        self.state = 'GET PARITY BIT'

        self.put(self.startsample, self.samplenum - 1, self.out_proto,
                 ['DATA', self.databyte])

        self.putx([ANN_ASCII, [chr(self.databyte)]])
        self.putx([ANN_DEC,   [str(self.databyte)]])
        self.putx([ANN_HEX,   [hex(self.databyte),
                               hex(self.databyte)[2:]]])
        self.putx([ANN_OCT,   [oct(self.databyte),
                               oct(self.databyte)[2:]]])
        self.putx([ANN_BITS,  [bin(self.databyte),
                               bin(self.databyte)[2:]]])

    def decode(self, ss, es, data):
        for (self.samplenum, owr) in data:

            # First sample: Save OWR value.
            if self.oldbit == None:
                self.oldbit = owr
                continue

            # Data link layer
            if self.lnk_state == 'WAIT FOR FALLING EDGE':
                # The start of a cycle is a falling edge.
                if (old_owr == 1 and owr == 0):
                    # Save the sample number where the start bit begins.
                    self.lnk_start = self.samplenum
                    # Go to waiting for sample time
                    self.lnk_state = 'WAIT FOR SAMPLE'
            elif self.lnk_state == 'WAIT FOR SAMPLE':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum == self.lnk_start + self.time_base):
                    self.lnk_bit  = owr & 0x1
                    self.lnk_cnt  = self.lnk_cnt + 1
                    self.lnk_byte = (self.lnk_byte << 1) & self.lnk_bit
                    self.lnk_state = 'WAIT FOR RISING EDGE'
            elif self.lnk_state == 'WAIT FOR RISING EDGE':
                # The end of a cycle is a rising edge.
                if (old_owr == 0 and owr == 1):
                    # Data bit cycle length should be between 2*T and 
                    if (self.samplenum < self.lnk_start + 2*self.time_base):
                        if (self.lnk_cnt == 8)
                            self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
                            self.lnk_cnt = 0
                    if (self.samplenum == self.lnk_start + 8*self.time_base):
                        self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
                    
                    # Go to waiting for sample time
                    self.lnk_state = 'WAIT FOR SAMPLE'

            elif self.state_lnk == 'GET DATA BITS'   : self.get_data_bits(owr)
            else                                     : raise Exception('Invalid state: %d' % self.state)

            # Save current RX/TX values for the next round.
            self.oldbit = owr
Commit	Line	Data
51990c45 IJ	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# 1-Wire protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# Annotation feed formats
	26	ANN_ASCII = 0
	27	ANN_DEC = 1
	28	ANN_HEX = 2
	29	ANN_OCT = 3
	30	ANN_BITS = 4
	31
	32	class Decoder(srd.Decoder):
	33	api_version = 1
	34	id = 'onewire'
	35	name = '1-Wire'
	36	longname = ''
	37	desc = '1-Wire bus and MicroLan'
	38	license = 'gplv2+'
	39	inputs = ['logic']
	40	outputs = ['onewire']
	41	probes = [
	42	{'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
	43	]
	44	optional_probes = [
	45	{'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
	46	]
	47	options = {
	48	'overdrive': ['Overdrive', 0],
	49	}
	50	annotations = [
	51	['ASCII', 'Data bytes as ASCII characters'],
	52	['Decimal', 'Databytes as decimal, integer values'],
	53	['Hex', 'Data bytes in hex format'],
	54	['Octal', 'Data bytes as octal numbers'],
	55	['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
	56	]
	57
	58	def putx(self, data):
	59	self.put(self.startsample, self.samplenum - 1, self.out_ann, data)
	60
	61	def __init__(self, **kwargs):
	62	# Common variables
	63	self.samplenum = 0
	64	# Link layer variables
65	self.lnk_state = 'WAIT FOR EVENT'
66	self.lnk_event = 'NONE'
67	self.lnk_start = -1
68	self.lnk_bit = -1
69	self.lnk_cnt = 0
70	self.lnk_byte = -1
71	# Network layer variables
72	self.net_state = 'WAIT FOR EVENT'
73	self.net_event = 'NONE'
74	self.net_command = -1
75	# Transport layer variables
76	self.trn_state = 'WAIT FOR EVENT'
77	self.trn_event = 'NONE'
78
79	self.data_sample = -1
80	self.cur_data_bit = 0
81	self.databyte = 0
82	self.startsample = -1
83
84	def start(self, metadata):
85	self.samplerate = metadata['samplerate']
86	self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
87	self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')
88
89	# The width of the 1-Wire time base (30us) in number of samples.
90	# TODO: optimize this value
91	self.time_base = float(self.samplerate) / float(0.000030)
92
93	def report(self):
94	pass
95
96	def get_data_sample(self, owr):
97	# Skip samples until we're in the middle of the start bit.
98	if not self.reached_data_sample():
99	return
100
101	self.data_sample = owr
102
103	self.cur_data_bit = 0
104	self.databyte = 0
105	self.startsample = -1
106
107	self.state = 'GET DATA BITS'
108
109	self.put(self.cycle_start, self.samplenum, self.out_proto,
110	['STARTBIT', self.startbit])
111	self.put(self.cycle_start, self.samplenum, self.out_ann,
112	[ANN_ASCII, ['Start bit', 'Start', 'S']])
113
114	def get_data_bits(self, owr):
115	# Skip samples until we're in the middle of the desired data bit.
116	if not self.reached_bit(self.cur_data_bit + 1):
117	return
118
119	# Save the sample number where the data byte starts.
120	if self.startsample == -1:
121	self.startsample = self.samplenum
122
123	# Get the next data bit in LSB-first or MSB-first fashion.
124	if self.options['bit_order'] == 'lsb-first':
125	self.databyte >>= 1
126	self.databyte \|= \
127	(owr << (self.options['num_data_bits'] - 1))
128	elif self.options['bit_order'] == 'msb-first':
129	self.databyte <<= 1
130	self.databyte \|= (owr << 0)
131	else:
132	raise Exception('Invalid bit order value: %s',
133	self.options['bit_order'])
134
135	# Return here, unless we already received all data bits.
136	# TODO? Off-by-one?
137	if self.cur_data_bit < self.options['num_data_bits'] - 1:
138	self.cur_data_bit += 1
139	return
140
141	self.state = 'GET PARITY BIT'
142
143	self.put(self.startsample, self.samplenum - 1, self.out_proto,
144	['DATA', self.databyte])
145
146	self.putx([ANN_ASCII, [chr(self.databyte)]])
147	self.putx([ANN_DEC, [str(self.databyte)]])
148	self.putx([ANN_HEX, [hex(self.databyte),
149	hex(self.databyte)[2:]]])
150	self.putx([ANN_OCT, [oct(self.databyte),
151	oct(self.databyte)[2:]]])
152	self.putx([ANN_BITS, [bin(self.databyte),
153	bin(self.databyte)[2:]]])
154
155	def decode(self, ss, es, data):
156	for (self.samplenum, owr) in data:
157
158	# First sample: Save OWR value.
159	if self.oldbit == None:
160	self.oldbit = owr
161	continue
162
163	# Data link layer
164	if self.lnk_state == 'WAIT FOR FALLING EDGE':
165	# The start of a cycle is a falling edge.
166	if (old_owr == 1 and owr == 0):
167	# Save the sample number where the start bit begins.
168	self.lnk_start = self.samplenum
169	# Go to waiting for sample time
170	self.lnk_state = 'WAIT FOR SAMPLE'
171	elif self.lnk_state == 'WAIT FOR SAMPLE':
172	# Data should be sample one 'time unit' after a falling edge
173	if (self.samplenum == self.lnk_start + self.time_base):
174	self.lnk_bit = owr & 0x1
175	self.lnk_cnt = self.lnk_cnt + 1
176	self.lnk_byte = (self.lnk_byte << 1) & self.lnk_bit
177	self.lnk_state = 'WAIT FOR RISING EDGE'
178	elif self.lnk_state == 'WAIT FOR RISING EDGE':
179	# The end of a cycle is a rising edge.
180	if (old_owr == 0 and owr == 1):
181	# Data bit cycle length should be between 2*T and
182	if (self.samplenum < self.lnk_start + 2*self.time_base):
183	if (self.lnk_cnt == 8)
184	self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
185	self.lnk_cnt = 0
186	if (self.samplenum == self.lnk_start + 8*self.time_base):
187	self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
188
189	# Go to waiting for sample time
190	self.lnk_state = 'WAIT FOR SAMPLE'
191
192	elif self.state_lnk == 'GET DATA BITS' : self.get_data_bits(owr)
193	else : raise Exception('Invalid state: %d' % self.state)
194
195	# Save current RX/TX values for the next round.
196	self.oldbit = owr
197