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271acd3b | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
271acd3b | 3 | ## |
edc6c8fd | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
271acd3b UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
271acd3b UH |
18 | ## |
19 | ||
271acd3b UH |
20 | import sigrokdecode as srd |
21 | ||
271acd3b UH |
22 | # ... |
23 | fields = { | |
2002229d UH |
24 | # START field (indicates start or stop of a transaction) |
25 | 'START': { | |
271acd3b UH |
26 | 0b0000: 'Start of cycle for a target', |
27 | 0b0001: 'Reserved', | |
28 | 0b0010: 'Grant for bus master 0', | |
29 | 0b0011: 'Grant for bus master 1', | |
30 | 0b0100: 'Reserved', | |
31 | 0b0101: 'Reserved', | |
32 | 0b0110: 'Reserved', | |
33 | 0b0111: 'Reserved', | |
34 | 0b1000: 'Reserved', | |
35 | 0b1001: 'Reserved', | |
36 | 0b1010: 'Reserved', | |
37 | 0b1011: 'Reserved', | |
38 | 0b1100: 'Reserved', | |
39 | 0b1101: 'Start of cycle for a Firmware Memory Read cycle', | |
40 | 0b1110: 'Start of cycle for a Firmware Memory Write cycle', | |
2002229d | 41 | 0b1111: 'Stop/abort (end of a cycle for a target)', |
271acd3b | 42 | }, |
2002229d UH |
43 | # Cycle type / direction field |
44 | # Bit 0 (LAD[0]) is unused, should always be 0. | |
45 | # Neither host nor peripheral are allowed to drive 0b11x0. | |
46 | 'CT_DR': { | |
271acd3b UH |
47 | 0b0000: 'I/O read', |
48 | 0b0010: 'I/O write', | |
49 | 0b0100: 'Memory read', | |
50 | 0b0110: 'Memory write', | |
51 | 0b1000: 'DMA read', | |
52 | 0b1010: 'DMA write', | |
2002229d UH |
53 | 0b1100: 'Reserved / not allowed', |
54 | 0b1110: 'Reserved / not allowed', | |
55 | }, | |
56 | # SIZE field (determines how many bytes are to be transferred) | |
57 | # Bits[3:2] are reserved, must be driven to 0b00. | |
58 | # Neither host nor peripheral are allowed to drive 0b0010. | |
59 | 'SIZE': { | |
60 | 0b0000: '8 bits (1 byte)', | |
61 | 0b0001: '16 bits (2 bytes)', | |
62 | 0b0010: 'Reserved / not allowed', | |
63 | 0b0011: '32 bits (4 bytes)', | |
64 | }, | |
65 | # CHANNEL field (bits[2:0] contain the DMA channel number) | |
66 | 'CHANNEL': { | |
67 | 0b0000: '0', | |
68 | 0b0001: '1', | |
69 | 0b0010: '2', | |
70 | 0b0011: '3', | |
71 | 0b0100: '4', | |
72 | 0b0101: '5', | |
73 | 0b0110: '6', | |
74 | 0b0111: '7', | |
271acd3b | 75 | }, |
2002229d | 76 | # SYNC field (used to add wait states) |
271acd3b UH |
77 | 'SYNC': { |
78 | 0b0000: 'Ready', | |
79 | 0b0001: 'Reserved', | |
80 | 0b0010: 'Reserved', | |
81 | 0b0011: 'Reserved', | |
82 | 0b0100: 'Reserved', | |
83 | 0b0101: 'Short wait', | |
84 | 0b0110: 'Long wait', | |
85 | 0b0111: 'Reserved', | |
86 | 0b1000: 'Reserved', | |
87 | 0b1001: 'Ready more (DMA only)', | |
88 | 0b1010: 'Error', | |
89 | 0b1011: 'Reserved', | |
90 | 0b1100: 'Reserved', | |
91 | 0b1101: 'Reserved', | |
92 | 0b1110: 'Reserved', | |
93 | 0b1111: 'Reserved', | |
94 | }, | |
95 | } | |
96 | ||
97 | class Decoder(srd.Decoder): | |
12851357 | 98 | api_version = 2 |
271acd3b UH |
99 | id = 'lpc' |
100 | name = 'LPC' | |
101 | longname = 'Low-Pin-Count' | |
a465436e | 102 | desc = 'Protocol for low-bandwidth devices on PC mainboards.' |
271acd3b UH |
103 | license = 'gplv2+' |
104 | inputs = ['logic'] | |
105 | outputs = ['lpc'] | |
6a15597a | 106 | channels = ( |
847e488b UH |
107 | {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'}, |
108 | {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'}, | |
109 | {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'}, | |
110 | {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'}, | |
111 | {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'}, | |
112 | {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'}, | |
da9bcbd9 | 113 | ) |
6a15597a | 114 | optional_channels = ( |
847e488b UH |
115 | {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'}, |
116 | {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'}, | |
117 | {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'}, | |
118 | {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'Clock run'}, | |
119 | {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'}, | |
120 | {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'}, | |
121 | {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'}, | |
da9bcbd9 BV |
122 | ) |
123 | annotations = ( | |
124 | ('warnings', 'Warnings'), | |
125 | ('start', 'Start'), | |
126 | ('cycle-type', 'Cycle-type/direction'), | |
127 | ('addr', 'Address'), | |
128 | ('tar1', 'Turn-around cycle 1'), | |
129 | ('sync', 'Sync'), | |
130 | ('data', 'Data'), | |
131 | ('tar2', 'Turn-around cycle 2'), | |
132 | ) | |
58e7e508 UH |
133 | annotation_rows = ( |
134 | ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)), | |
135 | ('warnings', 'Warnings', (0,)), | |
136 | ) | |
271acd3b | 137 | |
92b7b49f | 138 | def __init__(self): |
271acd3b UH |
139 | self.state = 'IDLE' |
140 | self.oldlclk = -1 | |
141 | self.samplenum = 0 | |
142 | self.clocknum = 0 | |
143 | self.lad = -1 | |
144 | self.addr = 0 | |
145 | self.cur_nibble = 0 | |
146 | self.cycle_type = -1 | |
cded73ba UH |
147 | self.databyte = 0 |
148 | self.tarcount = 0 | |
149 | self.synccount = 0 | |
59d3200c | 150 | self.oldpins = None |
63374ad8 | 151 | self.ss_block = self.es_block = None |
271acd3b | 152 | |
8915b346 | 153 | def start(self): |
be465111 | 154 | self.out_ann = self.register(srd.OUTPUT_ANN) |
271acd3b | 155 | |
edc6c8fd | 156 | def putb(self, data): |
63374ad8 | 157 | self.put(self.ss_block, self.es_block, self.out_ann, data) |
edc6c8fd | 158 | |
cded73ba | 159 | def handle_get_start(self, lad, lad_bits, lframe): |
271acd3b UH |
160 | # LAD[3:0]: START field (1 clock cycle). |
161 | ||
162 | # The last value of LAD[3:0] before LFRAME# gets de-asserted is what | |
163 | # the peripherals must use. However, the host can keep LFRAME# asserted | |
164 | # multiple clocks, and we output all START fields that occur, even | |
165 | # though the peripherals are supposed to ignore all but the last one. | |
63374ad8 UH |
166 | self.es_block = self.samplenum |
167 | self.putb([1, [fields['START'][lad], 'START', 'St', 'S']]) | |
168 | self.ss_block = self.samplenum | |
271acd3b UH |
169 | |
170 | # Output a warning if LAD[3:0] changes while LFRAME# is low. | |
171 | # TODO | |
172 | if (self.lad != -1 and self.lad != lad): | |
f7aa0719 | 173 | self.putb([0, ['LAD[3:0] changed while LFRAME# was asserted']]) |
271acd3b UH |
174 | |
175 | # LFRAME# is asserted (low). Wait until it gets de-asserted again | |
176 | # (the host is allowed to keep it asserted multiple clocks). | |
177 | if lframe != 1: | |
178 | return | |
179 | ||
180 | self.start_field = self.lad | |
181 | self.state = 'GET CT/DR' | |
182 | ||
183 | def handle_get_ct_dr(self, lad, lad_bits): | |
184 | # LAD[3:0]: Cycle type / direction field (1 clock cycle). | |
185 | ||
186 | self.cycle_type = fields['CT_DR'][lad] | |
187 | ||
188 | # TODO: Warning/error on invalid cycle types. | |
189 | if self.cycle_type == 'Reserved': | |
f7aa0719 | 190 | self.putb([0, ['Invalid cycle type (%s)' % lad_bits]]) |
271acd3b | 191 | |
63374ad8 | 192 | self.es_block = self.samplenum |
f7aa0719 | 193 | self.putb([2, ['Cycle type: %s' % self.cycle_type]]) |
63374ad8 | 194 | self.ss_block = self.samplenum |
271acd3b UH |
195 | |
196 | self.state = 'GET ADDR' | |
197 | self.addr = 0 | |
198 | self.cur_nibble = 0 | |
199 | ||
200 | def handle_get_addr(self, lad, lad_bits): | |
201 | # LAD[3:0]: ADDR field (4/8/0 clock cycles). | |
202 | ||
203 | # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks. | |
204 | # DMA cycles: no ADDR clocks at all. | |
205 | if self.cycle_type in ('I/O read', 'I/O write'): | |
206 | addr_nibbles = 4 # Address is 16bits. | |
207 | elif self.cycle_type in ('Memory read', 'Memory write'): | |
208 | addr_nibbles = 8 # Address is 32bits. | |
209 | else: | |
210 | addr_nibbles = 0 # TODO: How to handle later on? | |
211 | ||
cded73ba | 212 | # Addresses are driven MSN-first. |
271acd3b UH |
213 | offset = ((addr_nibbles - 1) - self.cur_nibble) * 4 |
214 | self.addr |= (lad << offset) | |
215 | ||
216 | # Continue if we haven't seen all ADDR cycles, yet. | |
271acd3b UH |
217 | if (self.cur_nibble < addr_nibbles - 1): |
218 | self.cur_nibble += 1 | |
219 | return | |
220 | ||
63374ad8 | 221 | self.es_block = self.samplenum |
cded73ba | 222 | s = 'Address: 0x%%0%dx' % addr_nibbles |
f7aa0719 | 223 | self.putb([3, [s % self.addr]]) |
63374ad8 | 224 | self.ss_block = self.samplenum |
271acd3b UH |
225 | |
226 | self.state = 'GET TAR' | |
227 | self.tar_count = 0 | |
228 | ||
229 | def handle_get_tar(self, lad, lad_bits): | |
230 | # LAD[3:0]: First TAR (turn-around) field (2 clock cycles). | |
231 | ||
63374ad8 | 232 | self.es_block = self.samplenum |
f7aa0719 | 233 | self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]]) |
63374ad8 | 234 | self.ss_block = self.samplenum |
271acd3b UH |
235 | |
236 | # On the first TAR clock cycle LAD[3:0] is driven to 1111 by | |
237 | # either the host or peripheral. On the second clock cycle, | |
238 | # the host or peripheral tri-states LAD[3:0], but its value | |
239 | # should still be 1111, due to pull-ups on the LAD lines. | |
240 | if lad_bits != '1111': | |
f7aa0719 | 241 | self.putb([0, ['TAR, cycle %d: %s (expected 1111)' % \ |
edc6c8fd | 242 | (self.tarcount, lad_bits)]]) |
271acd3b | 243 | |
cded73ba | 244 | if (self.tarcount != 1): |
271acd3b UH |
245 | self.tarcount += 1 |
246 | return | |
247 | ||
cded73ba | 248 | self.tarcount = 0 |
271acd3b UH |
249 | self.state = 'GET SYNC' |
250 | ||
251 | def handle_get_sync(self, lad, lad_bits): | |
252 | # LAD[3:0]: SYNC field (1-n clock cycles). | |
253 | ||
254 | self.sync_val = lad_bits | |
255 | self.cycle_type = fields['SYNC'][lad] | |
256 | ||
257 | # TODO: Warnings if reserved value are seen? | |
258 | if self.cycle_type == 'Reserved': | |
f7aa0719 | 259 | self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \ |
edc6c8fd | 260 | (self.synccount, self.sync_val)]]) |
271acd3b | 261 | |
63374ad8 | 262 | self.es_block = self.samplenum |
f7aa0719 | 263 | self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]]) |
63374ad8 | 264 | self.ss_block = self.samplenum |
271acd3b UH |
265 | |
266 | # TODO | |
267 | ||
271acd3b | 268 | self.cycle_count = 0 |
cded73ba | 269 | self.state = 'GET DATA' |
271acd3b UH |
270 | |
271 | def handle_get_data(self, lad, lad_bits): | |
272 | # LAD[3:0]: DATA field (2 clock cycles). | |
273 | ||
cded73ba | 274 | # Data is driven LSN-first. |
271acd3b UH |
275 | if (self.cycle_count == 0): |
276 | self.databyte = lad | |
277 | elif (self.cycle_count == 1): | |
278 | self.databyte |= (lad << 4) | |
279 | else: | |
cded73ba | 280 | raise Exception('Invalid cycle_count: %d' % self.cycle_count) |
271acd3b | 281 | |
cded73ba | 282 | if (self.cycle_count != 1): |
271acd3b UH |
283 | self.cycle_count += 1 |
284 | return | |
285 | ||
63374ad8 | 286 | self.es_block = self.samplenum |
f7aa0719 | 287 | self.putb([6, ['DATA: 0x%02x' % self.databyte]]) |
63374ad8 | 288 | self.ss_block = self.samplenum |
cded73ba UH |
289 | |
290 | self.cycle_count = 0 | |
271acd3b UH |
291 | self.state = 'GET TAR2' |
292 | ||
293 | def handle_get_tar2(self, lad, lad_bits): | |
294 | # LAD[3:0]: Second TAR field (2 clock cycles). | |
295 | ||
63374ad8 | 296 | self.es_block = self.samplenum |
f7aa0719 | 297 | self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]]) |
63374ad8 | 298 | self.ss_block = self.samplenum |
271acd3b UH |
299 | |
300 | # On the first TAR clock cycle LAD[3:0] is driven to 1111 by | |
301 | # either the host or peripheral. On the second clock cycle, | |
302 | # the host or peripheral tri-states LAD[3:0], but its value | |
303 | # should still be 1111, due to pull-ups on the LAD lines. | |
304 | if lad_bits != '1111': | |
edc6c8fd UH |
305 | self.putb([0, ['Warning: TAR, cycle %d: %s (expected 1111)' |
306 | % (self.tarcount, lad_bits)]]) | |
271acd3b | 307 | |
cded73ba | 308 | if (self.tarcount != 1): |
271acd3b UH |
309 | self.tarcount += 1 |
310 | return | |
311 | ||
cded73ba UH |
312 | self.tarcount = 0 |
313 | self.state = 'IDLE' | |
271acd3b | 314 | |
271acd3b | 315 | def decode(self, ss, es, data): |
63374ad8 | 316 | for (self.samplenum, pins) in data: |
271acd3b UH |
317 | |
318 | # If none of the pins changed, there's nothing to do. | |
319 | if self.oldpins == pins: | |
320 | continue | |
321 | ||
322 | # Store current pin values for the next round. | |
323 | self.oldpins = pins | |
324 | ||
325 | # Get individual pin values into local variables. | |
6554fbc9 UH |
326 | (lframe, lclk, lad0, lad1, lad2, lad3) = pins[:6] |
327 | (lreset, ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[6:] | |
271acd3b | 328 | |
1cb84473 UH |
329 | # Only look at the signals upon rising LCLK edges. The LPC clock |
330 | # is the same as the PCI clock (which is sampled at rising edges). | |
331 | if not (self.oldlclk == 0 and lclk == 1): | |
332 | self.oldlclk = lclk | |
333 | continue | |
271acd3b UH |
334 | |
335 | # Store LAD[3:0] bit values (one nibble) in local variables. | |
2002229d | 336 | # Most (but not all) states need this. |
271acd3b UH |
337 | if self.state != 'IDLE': |
338 | lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0 | |
cded73ba | 339 | lad_bits = bin(lad)[2:].zfill(4) |
edc6c8fd | 340 | # self.putb([0, ['LAD: %s' % lad_bits]]) |
cded73ba UH |
341 | |
342 | # TODO: Only memory read/write is currently supported/tested. | |
271acd3b UH |
343 | |
344 | # State machine | |
345 | if self.state == 'IDLE': | |
346 | # A valid LPC cycle starts with LFRAME# being asserted (low). | |
271acd3b | 347 | if lframe != 0: |
35b380b1 | 348 | continue |
63374ad8 | 349 | self.ss_block = self.samplenum |
271acd3b UH |
350 | self.state = 'GET START' |
351 | self.lad = -1 | |
352 | # self.clocknum = 0 | |
353 | elif self.state == 'GET START': | |
cded73ba | 354 | self.handle_get_start(lad, lad_bits, lframe) |
271acd3b | 355 | elif self.state == 'GET CT/DR': |
cded73ba | 356 | self.handle_get_ct_dr(lad, lad_bits) |
271acd3b | 357 | elif self.state == 'GET ADDR': |
cded73ba | 358 | self.handle_get_addr(lad, lad_bits) |
271acd3b | 359 | elif self.state == 'GET TAR': |
cded73ba | 360 | self.handle_get_tar(lad, lad_bits) |
271acd3b | 361 | elif self.state == 'GET SYNC': |
cded73ba | 362 | self.handle_get_sync(lad, lad_bits) |
271acd3b | 363 | elif self.state == 'GET DATA': |
cded73ba | 364 | self.handle_get_data(lad, lad_bits) |
271acd3b | 365 | elif self.state == 'GET TAR2': |
cded73ba | 366 | self.handle_get_tar2(lad, lad_bits) |