[libsigrokdecode.git] / decoders / enc28j60 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
##
## Permission is hereby granted, free of charge, to any person obtaining a copy
## of this software and associated documentation files (the "Software"), to deal
## in the Software without restriction, including without limitation the rights
## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
## copies of the Software, and to permit persons to whom the Software is
## furnished to do so, subject to the following conditions:
##
## The above copyright notice and this permission notice shall be included in all
## copies or substantial portions of the Software.
##
## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
## SOFTWARE.

import sigrokdecode as srd

OPCODE_MASK = 0b11100000
REG_ADDR_MASK = 0b00011111

OPCODE_HANDLERS = {
    0b00000000: '_process_rcr',
    0b00100000: '_process_rbm',
    0b01000000: '_process_wcr',
    0b01100000: '_process_wbm',
    0b10000000: '_process_bfs',
    0b10100000: '_process_bfc',
    0b11100000: '_process_src',
}

ANN_RCR = 0
ANN_RBM = 1
ANN_WCR = 2
ANN_WBM = 3
ANN_BFS = 4
ANN_BFC = 5
ANN_SRC = 6

ANN_DATA = 7
ANN_REG_ADDR = 8

ANN_WARNING = 9

REG_ADDR_ECON1 = 0x1F
BIT_ECON1_BSEL0 = 0b00000001
BIT_ECON1_BSEL1 = 0b00000010

REGS = [
    [
        'ERDPTL',
        'ERDPTH',
        'EWRPTL',
        'EWRPTH',
        'ETXSTL',
        'ETXSTH',
        'ETXNDL',
        'ETXNDH',
        'ERXSTL',
        'ERXSTH',
        'ERXNDL',
        'ERXNDH',
        'ERXRDPTL',
        'ERXRDPTH',
        'ERXWRPTL',
        'ERXWRPTH',
        'EDMASTL',
        'EDMASTH',
        'EDMANDL',
        'EDMANDH',
        'EDMADSTL',
        'EDMADSTH',
        'EDMACSL',
        'EDMACSH',
        '—',
        '—',
        'Reserved',
        'EIE',
        'EIR',
        'ESTAT',
        'ECON2',
        'ECON1',
    ],
    [
        'EHT0',
        'EHT1',
        'EHT2',
        'EHT3',
        'EHT4',
        'EHT5',
        'EHT6',
        'EHT7',
        'EPMM0',
        'EPMM1',
        'EPMM2',
        'EPMM3',
        'EPMM4',
        'EPMM5',
        'EPMM6',
        'EPMM7',
        'EPMCSL',
        'EPMCSH',
        '—',
        '—',
        'EPMOL',
        'EPMOH',
        'Reserved',
        'Reserved',
        'ERXFCON',
        'EPKTCNT',
        'Reserved',
        'EIE',
        'EIR',
        'ESTAT',
        'ECON2',
        'ECON1',
    ],
    [
        'MACON1',
        'Reserved',
        'MACON3',
        'MACON4',
        'MABBIPG',
        '—',
        'MAIPGL',
        'MAIPGH',
        'MACLCON1',
        'MACLCON2',
        'MAMXFLL',
        'MAMXFLH',
        'Reserved',
        'Reserved',
        'Reserved',
        '—',
        'Reserved',
        'Reserved',
        'MICMD',
        '—',
        'MIREGADR',
        'Reserved',
        'MIWRL',
        'MIWRH',
        'MIRDL',
        'MIRDH',
        'Reserved',
        'EIE',
        'EIR',
        'ESTAT',
        'ECON2',
        'ECON1',
    ],
    [
        'MAADR5',
        'MAADR6',
        'MAADR3',
        'MAADR4',
        'MAADR1',
        'MAADR2',
        'EBSTSD',
        'EBSTCON',
        'EBSTCSL',
        'EBSTCSH',
        'MISTAT',
        '—',
        '—',
        '—',
        '—',
        '—',
        '—',
        '—',
        'EREVID',
        '—',
        '—',
        'ECOCON',
        'Reserved',
        'EFLOCON',
        'EPAUSL',
        'EPAUSH',
        'Reserved',
        'EIE',
        'EIR',
        'ESTAT',
        'ECON2',
        'ECON1',
    ],
]

class Decoder(srd.Decoder):
    api_version = 3
    id = 'enc28j60'
    name = 'ENC28J60'
    longname = 'Microchip ENC28J60'
    desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
    license = 'mit'
    inputs = ['spi']
    outputs = ['enc28j60']
    tags = ['Embedded/industrial', 'Networking']
    annotations = (
        ('rcr', 'Read Control Register'),
        ('rbm', 'Read Buffer Memory'),
        ('wcr', 'Write Control Register'),
        ('wbm', 'Write Buffer Memory'),
        ('bfs', 'Bit Field Set'),
        ('bfc', 'Bit Field Clear'),
        ('src', 'System Reset Command'),
        ('data', 'Data'),
        ('reg-addr', 'Register Address'),
        ('warning', 'Warning'),
    )
    annotation_rows = (
        ('commands', 'Commands',
            (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
        ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
        ('warnings', 'Warnings', (ANN_WARNING,)),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.mosi = []
        self.miso = []
        self.ranges = []
        self.command_start = None
        self.command_end = None
        self.active = False
        self.bsel0 = None
        self.bsel1 = None

    def start(self):
        self.ann = self.register(srd.OUTPUT_ANN)

    def _process_command(self):
        if len(self.mosi) == 0:
            self.active = False
            return

        header = self.mosi[0]
        opcode = header & OPCODE_MASK

        if opcode not in OPCODE_HANDLERS:
            self._put_command_warning("Unknown opcode.")
            self.active = False
            return

        getattr(self, OPCODE_HANDLERS[opcode])()

        self.active = False

    def _get_register_name(self, reg_addr):
        if (self.bsel0 is None) or (self.bsel1 is None):
            # We don't know the bank we're in yet.
            return None
        else:
            bank = (self.bsel1 << 1) + self.bsel0
            return REGS[bank][reg_addr]

    def _put_register_header(self):
        reg_addr = self.mosi[0] & REG_ADDR_MASK
        reg_name = self._get_register_name(reg_addr)

        if reg_name is None:
            # We don't know the bank we're in yet.
            self.put(self.command_start, self.ranges[1][0], self.ann, [
                     ANN_REG_ADDR,
                     [
                        'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
                        '?:{0:02X}'.format(reg_addr),
                     ]])
            self.put(self.command_start, self.ranges[1][0], self.ann, [
                     ANN_WARNING,
                     [
                        'Warning: Register bank not known yet.',
                        'Warning',
                     ]])
        else:
            self.put(self.command_start, self.ranges[1][0], self.ann, [
                     ANN_REG_ADDR,
                     [
                        'Reg {0}'.format(reg_name),
                        '{0}'.format(reg_name),
                     ]])

            if (reg_name == '-') or (reg_name == 'Reserved'):
                self.put(self.command_start, self.ranges[1][0], self.ann, [
                         ANN_WARNING,
                         [
                            'Warning: Invalid register accessed.',
                            'Warning',
                         ]])

    def _put_data_byte(self, data, byte_index, binary=False):
        if byte_index == len(self.mosi) - 1:
            end_sample = self.command_end
        else:
            end_sample = self.ranges[byte_index + 1][0]

        if binary:
            self.put(self.ranges[byte_index][0], end_sample, self.ann, [
                     ANN_DATA,
                     [
                        'Data 0b{0:08b}'.format(data),
                        '{0:08b}'.format(data),
                     ]])
        else:
            self.put(self.ranges[byte_index][0], end_sample, self.ann, [
                     ANN_DATA,
                     [
                        'Data 0x{0:02X}'.format(data),
                        '{0:02X}'.format(data),
                     ]])

    def _put_command_warning(self, reason):
        self.put(self.command_start, self.command_end, self.ann, [
                 ANN_WARNING,
                 [
                    'Warning: {0}'.format(reason),
                    'Warning',
                 ]])

    def _process_rcr(self):
        self.put(self.command_start, self.command_end,
                 self.ann, [ANN_RCR, ['Read Control Register', 'RCR']])

        if (len(self.mosi) != 2) and (len(self.mosi) != 3):
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()

        reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
        if reg_name is None:
            # We can't tell if we're accessing MAC/MII registers or not
            # Let's trust the user in this case.
            pass
        else:
            if (reg_name[0] == 'M') and (len(self.mosi) != 3):
                self._put_command_warning('Attempting to read a MAC/MII '
                    + 'register without using the dummy byte.')
                return

            if (reg_name[0] != 'M') and (len(self.mosi) != 2):
                self._put_command_warning('Attempting to read a non-MAC/MII '
                                          + 'register using the dummy byte.')
                return

        if len(self.mosi) == 2:
            self._put_data_byte(self.miso[1], 1)
        else:
            self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [
                     ANN_DATA,
                     [
                        'Dummy Byte',
                        'Dummy',
                     ]])
            self._put_data_byte(self.miso[2], 2)

    def _process_rbm(self):
        if self.mosi[0] != 0b00111010:
            self._put_command_warning('Invalid header byte.')
            return

        self.put(self.command_start, self.command_end, self.ann, [
                 ANN_RBM,
                 [
                    'Read Buffer Memory: Length {0}'.format(
                        len(self.mosi) - 1),
                    'RBM',
                 ]])

        for i in range(1, len(self.miso)):
            self._put_data_byte(self.miso[i], i)

    def _process_wcr(self):
        self.put(self.command_start, self.command_end,
                 self.ann, [ANN_WCR, ['Write Control Register', 'WCR']])

        if len(self.mosi) != 2:
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()
        self._put_data_byte(self.mosi[1], 1)

        if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
            self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
            self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1

    def _process_wbm(self):
        if self.mosi[0] != 0b01111010:
            self._put_command_warning('Invalid header byte.')
            return

        self.put(self.command_start, self.command_end, self.ann, [
                 ANN_WBM,
                 [
                    'Write Buffer Memory: Length {0}'.format(
                        len(self.mosi) - 1),
                    'WBM',
                 ]])

        for i in range(1, len(self.mosi)):
            self._put_data_byte(self.mosi[i], i)

    def _process_bfc(self):
        self.put(self.command_start, self.command_end,
                 self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']])

        if len(self.mosi) != 2:
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()
        self._put_data_byte(self.mosi[1], 1, True)

        if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
            if self.mosi[1] & BIT_ECON1_BSEL0:
                self.bsel0 = 0
            if self.mosi[1] & BIT_ECON1_BSEL1:
                self.bsel1 = 0

    def _process_bfs(self):
        self.put(self.command_start, self.command_end,
                 self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']])

        if len(self.mosi) != 2:
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()
        self._put_data_byte(self.mosi[1], 1, True)

        if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
            if self.mosi[1] & BIT_ECON1_BSEL0:
                self.bsel0 = 1
            if self.mosi[1] & BIT_ECON1_BSEL1:
                self.bsel1 = 1

    def _process_src(self):
        self.put(self.command_start, self.command_end,
                 self.ann, [ANN_SRC, ['System Reset Command', 'SRC']])

        if len(self.mosi) != 1:
            self._put_command_warning('Invalid command length.')
            return

        self.bsel0 = 0
        self.bsel1 = 0

    def decode(self, ss, es, data):
        ptype, data1, data2 = data

        if ptype == 'CS-CHANGE':
            new_cs = data2

            if new_cs == 0:
                self.active = True
                self.command_start = ss
                self.mosi = []
                self.miso = []
                self.ranges = []
            elif new_cs == 1:
                if self.active:
                    self.command_end = es
                    self._process_command()
        elif ptype == 'DATA':
            mosi, miso = data1, data2

            self.mosi.append(mosi)
            self.miso.append(miso)
            self.ranges.append((ss, es))
Commit	Line	Data
a7df1ee4 JL	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
	5	##
	6	## Permission is hereby granted, free of charge, to any person obtaining a copy
	7	## of this software and associated documentation files (the "Software"), to deal
	8	## in the Software without restriction, including without limitation the rights
	9	## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	## copies of the Software, and to permit persons to whom the Software is
	11	## furnished to do so, subject to the following conditions:
	12	##
	13	## The above copyright notice and this permission notice shall be included in all
	14	## copies or substantial portions of the Software.
	15	##
	16	## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	19	## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	22	## SOFTWARE.
	23
	24	import sigrokdecode as srd
	25
	26	OPCODE_MASK = 0b11100000
	27	REG_ADDR_MASK = 0b00011111
	28
	29	OPCODE_HANDLERS = {
	30	0b00000000: '_process_rcr',
	31	0b00100000: '_process_rbm',
	32	0b01000000: '_process_wcr',
	33	0b01100000: '_process_wbm',
	34	0b10000000: '_process_bfs',
	35	0b10100000: '_process_bfc',
	36	0b11100000: '_process_src',
	37	}
	38
	39	ANN_RCR = 0
	40	ANN_RBM = 1
	41	ANN_WCR = 2
	42	ANN_WBM = 3
	43	ANN_BFS = 4
	44	ANN_BFC = 5
	45	ANN_SRC = 6
	46
	47	ANN_DATA = 7
	48	ANN_REG_ADDR = 8
	49
	50	ANN_WARNING = 9
	51
	52	REG_ADDR_ECON1 = 0x1F
	53	BIT_ECON1_BSEL0 = 0b00000001
	54	BIT_ECON1_BSEL1 = 0b00000010
	55
	56	REGS = [
	57	[
	58	'ERDPTL',
	59	'ERDPTH',
	60	'EWRPTL',
	61	'EWRPTH',
	62	'ETXSTL',
	63	'ETXSTH',
	64	'ETXNDL',
65	'ETXNDH',
66	'ERXSTL',
67	'ERXSTH',
68	'ERXNDL',
69	'ERXNDH',
70	'ERXRDPTL',
71	'ERXRDPTH',
72	'ERXWRPTL',
73	'ERXWRPTH',
74	'EDMASTL',
75	'EDMASTH',
76	'EDMANDL',
77	'EDMANDH',
78	'EDMADSTL',
79	'EDMADSTH',
80	'EDMACSL',
81	'EDMACSH',
82	'—',
83	'—',
84	'Reserved',
85	'EIE',
86	'EIR',
87	'ESTAT',
88	'ECON2',
89	'ECON1',
90	],
91	[
92	'EHT0',
93	'EHT1',
94	'EHT2',
95	'EHT3',
96	'EHT4',
97	'EHT5',
98	'EHT6',
99	'EHT7',
100	'EPMM0',
101	'EPMM1',
102	'EPMM2',
103	'EPMM3',
104	'EPMM4',
105	'EPMM5',
106	'EPMM6',
107	'EPMM7',
108	'EPMCSL',
109	'EPMCSH',
110	'—',
111	'—',
112	'EPMOL',
113	'EPMOH',
114	'Reserved',
115	'Reserved',
116	'ERXFCON',
117	'EPKTCNT',
118	'Reserved',
119	'EIE',
120	'EIR',
121	'ESTAT',
122	'ECON2',
123	'ECON1',
124	],
125	[
126	'MACON1',
127	'Reserved',
128	'MACON3',
129	'MACON4',
130	'MABBIPG',
131	'—',
132	'MAIPGL',
133	'MAIPGH',
134	'MACLCON1',
135	'MACLCON2',
136	'MAMXFLL',
137	'MAMXFLH',
138	'Reserved',
139	'Reserved',
140	'Reserved',
141	'—',
142	'Reserved',
143	'Reserved',
144	'MICMD',
145	'—',
146	'MIREGADR',
147	'Reserved',
148	'MIWRL',
149	'MIWRH',
150	'MIRDL',
151	'MIRDH',
152	'Reserved',
153	'EIE',
154	'EIR',
155	'ESTAT',
156	'ECON2',
157	'ECON1',
158	],
159	[
160	'MAADR5',
161	'MAADR6',
162	'MAADR3',
163	'MAADR4',
164	'MAADR1',
165	'MAADR2',
166	'EBSTSD',
167	'EBSTCON',
168	'EBSTCSL',
169	'EBSTCSH',
170	'MISTAT',
171	'—',
172	'—',
173	'—',
174	'—',
175	'—',
176	'—',
177	'—',
178	'EREVID',
179	'—',
180	'—',
181	'ECOCON',
182	'Reserved',
183	'EFLOCON',
184	'EPAUSL',
185	'EPAUSH',
186	'Reserved',
187	'EIE',
188	'EIR',
189	'ESTAT',
190	'ECON2',
191	'ECON1',
192	],
193	]
194
195	class Decoder(srd.Decoder):
196	api_version = 3
197	id = 'enc28j60'
198	name = 'ENC28J60'
199	longname = 'Microchip ENC28J60'
200	desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
201	license = 'mit'
202	inputs = ['spi']
203	outputs = ['enc28j60']
2df02753	204	tags = ['Embedded/industrial', 'Networking']
a7df1ee4 JL	205	annotations = (
	206	('rcr', 'Read Control Register'),
	207	('rbm', 'Read Buffer Memory'),
	208	('wcr', 'Write Control Register'),
	209	('wbm', 'Write Buffer Memory'),
	210	('bfs', 'Bit Field Set'),
	211	('bfc', 'Bit Field Clear'),
	212	('src', 'System Reset Command'),
	213	('data', 'Data'),
	214	('reg-addr', 'Register Address'),
	215	('warning', 'Warning'),
	216	)
	217	annotation_rows = (
	218	('commands', 'Commands',
	219	(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
	220	('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
	221	('warnings', 'Warnings', (ANN_WARNING,)),
	222	)
	223
	224	def __init__(self):
	225	self.reset()
	226
	227	def reset(self):
	228	self.mosi = []
	229	self.miso = []
	230	self.ranges = []
	231	self.command_start = None
	232	self.command_end = None
	233	self.active = False
	234	self.bsel0 = None
	235	self.bsel1 = None
	236
	237	def start(self):
	238	self.ann = self.register(srd.OUTPUT_ANN)
	239
	240	def _process_command(self):
	241	if len(self.mosi) == 0:
	242	self.active = False
	243	return
	244
	245	header = self.mosi[0]
	246	opcode = header & OPCODE_MASK
	247
	248	if opcode not in OPCODE_HANDLERS:
	249	self._put_command_warning("Unknown opcode.")
	250	self.active = False
	251	return
	252
	253	getattr(self, OPCODE_HANDLERS[opcode])()
	254
	255	self.active = False
	256
	257	def _get_register_name(self, reg_addr):
	258	if (self.bsel0 is None) or (self.bsel1 is None):
	259	# We don't know the bank we're in yet.
	260	return None
	261	else:
	262	bank = (self.bsel1 << 1) + self.bsel0
	263	return REGS[bank][reg_addr]
	264
	265	def _put_register_header(self):
	266	reg_addr = self.mosi[0] & REG_ADDR_MASK
	267	reg_name = self._get_register_name(reg_addr)
	268
269	if reg_name is None:
270	# We don't know the bank we're in yet.
271	self.put(self.command_start, self.ranges[1][0], self.ann, [
272	ANN_REG_ADDR,
273	[
274	'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
275	'?:{0:02X}'.format(reg_addr),
276	]])
277	self.put(self.command_start, self.ranges[1][0], self.ann, [
278	ANN_WARNING,
279	[
280	'Warning: Register bank not known yet.',
281	'Warning',
282	]])
283	else:
284	self.put(self.command_start, self.ranges[1][0], self.ann, [
285	ANN_REG_ADDR,
286	[
287	'Reg {0}'.format(reg_name),
288	'{0}'.format(reg_name),
289	]])
290
291	if (reg_name == '-') or (reg_name == 'Reserved'):
292	self.put(self.command_start, self.ranges[1][0], self.ann, [
293	ANN_WARNING,
294	[
295	'Warning: Invalid register accessed.',
296	'Warning',
297	]])
298
299	def _put_data_byte(self, data, byte_index, binary=False):
300	if byte_index == len(self.mosi) - 1:
301	end_sample = self.command_end
302	else:
303	end_sample = self.ranges[byte_index + 1][0]
304
305	if binary:
306	self.put(self.ranges[byte_index][0], end_sample, self.ann, [
307	ANN_DATA,
308	[
309	'Data 0b{0:08b}'.format(data),
310	'{0:08b}'.format(data),
311	]])
312	else:
313	self.put(self.ranges[byte_index][0], end_sample, self.ann, [
314	ANN_DATA,
315	[
316	'Data 0x{0:02X}'.format(data),
317	'{0:02X}'.format(data),
318	]])
319
320	def _put_command_warning(self, reason):
321	self.put(self.command_start, self.command_end, self.ann, [
322	ANN_WARNING,
323	[
324	'Warning: {0}'.format(reason),
325	'Warning',
326	]])
327
328	def _process_rcr(self):
329	self.put(self.command_start, self.command_end,
330	self.ann, [ANN_RCR, ['Read Control Register', 'RCR']])
331
332	if (len(self.mosi) != 2) and (len(self.mosi) != 3):
333	self._put_command_warning('Invalid command length.')
334	return
335
336	self._put_register_header()
337
338	reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
339	if reg_name is None:
340	# We can't tell if we're accessing MAC/MII registers or not
341	# Let's trust the user in this case.
342	pass
343	else:
344	if (reg_name[0] == 'M') and (len(self.mosi) != 3):
345	self._put_command_warning('Attempting to read a MAC/MII '
346	+ 'register without using the dummy byte.')
347	return
348
349	if (reg_name[0] != 'M') and (len(self.mosi) != 2):
350	self._put_command_warning('Attempting to read a non-MAC/MII '
351	+ 'register using the dummy byte.')
352	return
353
354	if len(self.mosi) == 2:
355	self._put_data_byte(self.miso[1], 1)
356	else:
357	self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [
358	ANN_DATA,
359	[
360	'Dummy Byte',
361	'Dummy',
362	]])
363	self._put_data_byte(self.miso[2], 2)
364
365	def _process_rbm(self):
366	if self.mosi[0] != 0b00111010:
367	self._put_command_warning('Invalid header byte.')
368	return
369
370	self.put(self.command_start, self.command_end, self.ann, [
371	ANN_RBM,
372	[
373	'Read Buffer Memory: Length {0}'.format(
374	len(self.mosi) - 1),
375	'RBM',
376	]])
377
378	for i in range(1, len(self.miso)):
379	self._put_data_byte(self.miso[i], i)
380
381	def _process_wcr(self):
382	self.put(self.command_start, self.command_end,
383	self.ann, [ANN_WCR, ['Write Control Register', 'WCR']])
384
385	if len(self.mosi) != 2:
386	self._put_command_warning('Invalid command length.')
387	return
388
389	self._put_register_header()
390	self._put_data_byte(self.mosi[1], 1)
391
392	if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
393	self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
394	self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
395
396	def _process_wbm(self):
397	if self.mosi[0] != 0b01111010:
398	self._put_command_warning('Invalid header byte.')
399	return
400
401	self.put(self.command_start, self.command_end, self.ann, [
402	ANN_WBM,
403	[
404	'Write Buffer Memory: Length {0}'.format(
405	len(self.mosi) - 1),
406	'WBM',
407	]])
408
409	for i in range(1, len(self.mosi)):
410	self._put_data_byte(self.mosi[i], i)
411
412	def _process_bfc(self):
413	self.put(self.command_start, self.command_end,
414	self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']])
415
416	if len(self.mosi) != 2:
417	self._put_command_warning('Invalid command length.')
418	return
419
420	self._put_register_header()
421	self._put_data_byte(self.mosi[1], 1, True)
422
423	if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
424	if self.mosi[1] & BIT_ECON1_BSEL0:
425	self.bsel0 = 0
426	if self.mosi[1] & BIT_ECON1_BSEL1:
427	self.bsel1 = 0
428
429	def _process_bfs(self):
430	self.put(self.command_start, self.command_end,
431	self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']])
432
433	if len(self.mosi) != 2:
434	self._put_command_warning('Invalid command length.')
435	return
436
437	self._put_register_header()
438	self._put_data_byte(self.mosi[1], 1, True)
439
440	if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
441	if self.mosi[1] & BIT_ECON1_BSEL0:
442	self.bsel0 = 1
443	if self.mosi[1] & BIT_ECON1_BSEL1:
444	self.bsel1 = 1
445
446	def _process_src(self):
447	self.put(self.command_start, self.command_end,
448	self.ann, [ANN_SRC, ['System Reset Command', 'SRC']])
449
450	if len(self.mosi) != 1:
451	self._put_command_warning('Invalid command length.')
452	return
453
454	self.bsel0 = 0
455	self.bsel1 = 0
456
457	def decode(self, ss, es, data):
458	ptype, data1, data2 = data
459
460	if ptype == 'CS-CHANGE':
461	new_cs = data2
462
463	if new_cs == 0:
464	self.active = True
465	self.command_start = ss
466	self.mosi = []
467	self.miso = []
468	self.ranges = []
469	elif new_cs == 1:
470	if self.active:
471	self.command_end = es
472	self._process_command()
473	elif ptype == 'DATA':
474	mosi, miso = data1, data2
475
476	self.mosi.append(mosi)
477	self.miso.append(miso)
478	self.ranges.append((ss, es))