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702fa251 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
702fa251 | 3 | ## |
e20f455c | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
38b40330 | 5 | ## Copyright (C) 2019 Stephan Thiele <stephan.thiele@mailbox.org> |
702fa251 UH |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 18 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
702fa251 | 19 | ## |
702fa251 UH |
20 | |
21 | import sigrokdecode as srd | |
22 | ||
21cda951 UH |
23 | class SamplerateError(Exception): |
24 | pass | |
25 | ||
ad373029 UH |
26 | def dlc2len(dlc): |
27 | return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc] | |
28 | ||
702fa251 | 29 | class Decoder(srd.Decoder): |
64d87119 | 30 | api_version = 3 |
702fa251 UH |
31 | id = 'can' |
32 | name = 'CAN' | |
9e1437a0 | 33 | longname = 'Controller Area Network' |
702fa251 UH |
34 | desc = 'Field bus protocol for distributed realtime control.' |
35 | license = 'gplv2+' | |
36 | inputs = ['logic'] | |
6cbba91f | 37 | outputs = [] |
d6d8a8a4 | 38 | tags = ['Automotive'] |
6a15597a | 39 | channels = ( |
702fa251 | 40 | {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, |
da9bcbd9 | 41 | ) |
84c1c0b5 | 42 | options = ( |
3b593817 UH |
43 | {'id': 'nominal_bitrate', 'desc': 'Nominal bitrate (bits/s)', 'default': 1000000}, |
44 | {'id': 'fast_bitrate', 'desc': 'Fast bitrate (bits/s)', 'default': 2000000}, | |
b0918d40 | 45 | {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, |
84c1c0b5 | 46 | ) |
da9bcbd9 | 47 | annotations = ( |
e144452b | 48 | ('data', 'Payload data'), |
da9bcbd9 BV |
49 | ('sof', 'Start of frame'), |
50 | ('eof', 'End of frame'), | |
51 | ('id', 'Identifier'), | |
52 | ('ext-id', 'Extended identifier'), | |
53 | ('full-id', 'Full identifier'), | |
54 | ('ide', 'Identifier extension bit'), | |
55 | ('reserved-bit', 'Reserved bit 0 and 1'), | |
56 | ('rtr', 'Remote transmission request'), | |
57 | ('srr', 'Substitute remote request'), | |
58 | ('dlc', 'Data length count'), | |
59 | ('crc-sequence', 'CRC sequence'), | |
60 | ('crc-delimiter', 'CRC delimiter'), | |
61 | ('ack-slot', 'ACK slot'), | |
62 | ('ack-delimiter', 'ACK delimiter'), | |
63 | ('stuff-bit', 'Stuff bit'), | |
e144452b | 64 | ('warning', 'Warning'), |
544038d9 | 65 | ('bit', 'Bit'), |
d4a28d0f UH |
66 | ) |
67 | annotation_rows = ( | |
544038d9 | 68 | ('bits', 'Bits', (15, 17)), |
2fac4493 UH |
69 | ('fields', 'Fields', tuple(range(15))), |
70 | ('warnings', 'Warnings', (16,)), | |
da9bcbd9 | 71 | ) |
702fa251 | 72 | |
92b7b49f | 73 | def __init__(self): |
10aeb8ea GS |
74 | self.reset() |
75 | ||
76 | def reset(self): | |
f372d597 | 77 | self.samplerate = None |
702fa251 UH |
78 | self.reset_variables() |
79 | ||
f372d597 | 80 | def start(self): |
be465111 | 81 | self.out_ann = self.register(srd.OUTPUT_ANN) |
702fa251 | 82 | |
8abd7aa3 ST |
83 | def set_bit_rate(self, bitrate): |
84 | self.bit_width = float(self.samplerate) / float(bitrate) | |
85 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] | |
86 | ||
87 | def set_nominal_bitrate(self): | |
88 | self.set_bit_rate(self.options['nominal_bitrate']) | |
89 | ||
90 | def set_fast_bitrate(self): | |
91 | self.set_bit_rate(self.options['fast_bitrate']) | |
92 | ||
f372d597 BV |
93 | def metadata(self, key, value): |
94 | if key == srd.SRD_CONF_SAMPLERATE: | |
95 | self.samplerate = value | |
2d9e1115 | 96 | self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate']) |
300f9194 | 97 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] |
702fa251 | 98 | |
4b1813b4 UH |
99 | # Generic helper for CAN bit annotations. |
100 | def putg(self, ss, es, data): | |
300f9194 | 101 | left, right = int(self.sample_point), int(self.bit_width - self.sample_point) |
4b1813b4 UH |
102 | self.put(ss - left, es + right, self.out_ann, data) |
103 | ||
104 | # Single-CAN-bit annotation using the current samplenum. | |
e20f455c | 105 | def putx(self, data): |
4b1813b4 UH |
106 | self.putg(self.samplenum, self.samplenum, data) |
107 | ||
108 | # Single-CAN-bit annotation using the samplenum of CAN bit 12. | |
109 | def put12(self, data): | |
110 | self.putg(self.ss_bit12, self.ss_bit12, data) | |
111 | ||
6c890c08 | 112 | # Single-CAN-bit annotation using the samplenum of CAN bit 32. |
113 | def put32(self, data): | |
114 | self.putg(self.ss_bit32, self.ss_bit32, data) | |
115 | ||
4b1813b4 UH |
116 | # Multi-CAN-bit annotation from self.ss_block to current samplenum. |
117 | def putb(self, data): | |
118 | self.putg(self.ss_block, self.samplenum, data) | |
e20f455c | 119 | |
702fa251 UH |
120 | def reset_variables(self): |
121 | self.state = 'IDLE' | |
122 | self.sof = self.frame_type = self.dlc = None | |
123 | self.rawbits = [] # All bits, including stuff bits | |
124 | self.bits = [] # Only actual CAN frame bits (no stuff bits) | |
125 | self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) | |
126 | self.last_databit = 999 # Positive value that bitnum+x will never match | |
4b1813b4 UH |
127 | self.ss_block = None |
128 | self.ss_bit12 = None | |
6c890c08 | 129 | self.ss_bit32 = None |
4b1813b4 | 130 | self.ss_databytebits = [] |
6c890c08 | 131 | self.fd = False |
132 | self.rtr = None | |
702fa251 | 133 | |
45a50880 GS |
134 | # Poor man's clock synchronization. Use signal edges which change to |
135 | # dominant state in rather simple ways. This naive approach is neither | |
136 | # aware of the SYNC phase's width nor the specific location of the edge, | |
137 | # but improves the decoder's reliability when the input signal's bitrate | |
138 | # does not exactly match the nominal rate. | |
139 | def dom_edge_seen(self, force = False): | |
140 | self.dom_edge_snum = self.samplenum | |
141 | self.dom_edge_bcount = self.curbit | |
142 | ||
64d87119 GS |
143 | # Determine the position of the next desired bit's sample point. |
144 | def get_sample_point(self, bitnum): | |
45a50880 | 145 | samplenum = self.dom_edge_snum |
e4eeaab3 GS |
146 | samplenum += self.bit_width * (bitnum - self.dom_edge_bcount) |
147 | samplenum += self.sample_point | |
148 | return int(samplenum) | |
702fa251 UH |
149 | |
150 | def is_stuff_bit(self): | |
151 | # CAN uses NRZ encoding and bit stuffing. | |
152 | # After 5 identical bits, a stuff bit of opposite value is added. | |
a0128522 | 153 | # But not in the CRC delimiter, ACK, and end of frame fields. |
cffb6592 | 154 | if len(self.bits) > self.last_databit + 17: |
a0128522 | 155 | return False |
702fa251 UH |
156 | last_6_bits = self.rawbits[-6:] |
157 | if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): | |
158 | return False | |
159 | ||
160 | # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. | |
702fa251 UH |
161 | self.bits.pop() # Drop last bit. |
162 | return True | |
163 | ||
164 | def is_valid_crc(self, crc_bits): | |
165 | return True # TODO | |
166 | ||
167 | def decode_error_frame(self, bits): | |
168 | pass # TODO | |
169 | ||
170 | def decode_overload_frame(self, bits): | |
171 | pass # TODO | |
172 | ||
173 | # Both standard and extended frames end with CRC, CRC delimiter, ACK, | |
174 | # ACK delimiter, and EOF fields. Handle them in a common function. | |
175 | # Returns True if the frame ended (EOF), False otherwise. | |
176 | def decode_frame_end(self, can_rx, bitnum): | |
177 | ||
4b1813b4 UH |
178 | # Remember start of CRC sequence (see below). |
179 | if bitnum == (self.last_databit + 1): | |
180 | self.ss_block = self.samplenum | |
741dba78 | 181 | if self.fd: |
ad373029 | 182 | if dlc2len(self.dlc) < 16: |
741dba78 ST |
183 | self.crc_len = 27 # 17 + SBC + stuff bits |
184 | else: | |
fd41596a | 185 | self.crc_len = 32 # 21 + SBC + stuff bits |
741dba78 ST |
186 | else: |
187 | self.crc_len = 15 | |
188 | ||
189 | # CRC sequence (15 bits, 17 bits or 21 bits) | |
190 | elif bitnum == (self.last_databit + self.crc_len): | |
191 | if self.fd: | |
ad373029 | 192 | if dlc2len(self.dlc) < 16: |
3b593817 UH |
193 | crc_type = "CRC-17" |
194 | else: | |
195 | crc_type = "CRC-21" | |
741dba78 | 196 | else: |
9a76aa18 | 197 | crc_type = "CRC-15" |
741dba78 | 198 | |
702fa251 | 199 | x = self.last_databit + 1 |
741dba78 | 200 | crc_bits = self.bits[x:x + self.crc_len + 1] |
702fa251 | 201 | self.crc = int(''.join(str(d) for d in crc_bits), 2) |
741dba78 ST |
202 | self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc), |
203 | '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]]) | |
702fa251 | 204 | if not self.is_valid_crc(crc_bits): |
74c9bb3c | 205 | self.putb([16, ['CRC is invalid']]) |
702fa251 UH |
206 | |
207 | # CRC delimiter bit (recessive) | |
741dba78 | 208 | elif bitnum == (self.last_databit + self.crc_len + 1): |
74c9bb3c UH |
209 | self.putx([12, ['CRC delimiter: %d' % can_rx, |
210 | 'CRC d: %d' % can_rx, 'CRC d']]) | |
2fac4493 UH |
211 | if can_rx != 1: |
212 | self.putx([16, ['CRC delimiter must be a recessive bit']]) | |
702fa251 | 213 | |
8abd7aa3 ST |
214 | if self.fd: |
215 | self.set_nominal_bitrate() | |
216 | ||
702fa251 | 217 | # ACK slot bit (dominant: ACK, recessive: NACK) |
741dba78 | 218 | elif bitnum == (self.last_databit + self.crc_len + 2): |
702fa251 | 219 | ack = 'ACK' if can_rx == 0 else 'NACK' |
74c9bb3c | 220 | self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) |
702fa251 UH |
221 | |
222 | # ACK delimiter bit (recessive) | |
741dba78 | 223 | elif bitnum == (self.last_databit + self.crc_len + 3): |
74c9bb3c UH |
224 | self.putx([14, ['ACK delimiter: %d' % can_rx, |
225 | 'ACK d: %d' % can_rx, 'ACK d']]) | |
2fac4493 UH |
226 | if can_rx != 1: |
227 | self.putx([16, ['ACK delimiter must be a recessive bit']]) | |
702fa251 | 228 | |
4b1813b4 | 229 | # Remember start of EOF (see below). |
741dba78 | 230 | elif bitnum == (self.last_databit + self.crc_len + 4): |
4b1813b4 UH |
231 | self.ss_block = self.samplenum |
232 | ||
702fa251 | 233 | # End of frame (EOF), 7 recessive bits |
b177af15 | 234 | elif bitnum == (self.last_databit + self.crc_len + 10): |
74c9bb3c | 235 | self.putb([2, ['End of frame', 'EOF', 'E']]) |
2fac4493 UH |
236 | if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: |
237 | self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) | |
702fa251 UH |
238 | self.reset_variables() |
239 | return True | |
240 | ||
241 | return False | |
242 | ||
243 | # Returns True if the frame ended (EOF), False otherwise. | |
244 | def decode_standard_frame(self, can_rx, bitnum): | |
245 | ||
3b593817 UH |
246 | # Bit 14: FDF (Flexible data format) |
247 | # Has to be sent dominant when FD frame, has to be sent recessive | |
248 | # when classic CAN frame. | |
702fa251 | 249 | if bitnum == 14: |
38b40330 | 250 | self.fd = True if can_rx else False |
b177af15 | 251 | if self.fd: |
3b593817 UH |
252 | self.putx([7, ['Flexible data format: %d' % can_rx, |
253 | 'FDF: %d' % can_rx, 'FDF']]) | |
b177af15 ST |
254 | else: |
255 | self.putx([7, ['Reserved bit 0: %d' % can_rx, | |
3b593817 | 256 | 'RB0: %d' % can_rx, 'RB0']]) |
38b40330 | 257 | |
38b40330 | 258 | if self.fd: |
3b593817 UH |
259 | # Bit 12: Substitute remote request (SRR) bit |
260 | self.put12([8, ['Substitute remote request', 'SRR']]) | |
7f75d507 | 261 | self.dlc_start = 18 |
38b40330 ST |
262 | else: |
263 | # Bit 12: Remote transmission request (RTR) bit | |
264 | # Data frame: dominant, remote frame: recessive | |
265 | # Remote frames do not contain a data field. | |
266 | rtr = 'remote' if self.bits[12] == 1 else 'data' | |
267 | self.put12([8, ['Remote transmission request: %s frame' % rtr, | |
268 | 'RTR: %s frame' % rtr, 'RTR']]) | |
7f75d507 | 269 | self.dlc_start = 15 |
38b40330 | 270 | |
3b593817 UH |
271 | if bitnum == 15 and self.fd: |
272 | self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']]) | |
7f75d507 | 273 | |
3b593817 UH |
274 | if bitnum == 16 and self.fd: |
275 | self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']]) | |
702fa251 | 276 | |
3b593817 UH |
277 | if bitnum == 17 and self.fd: |
278 | self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']]) | |
4b1813b4 UH |
279 | |
280 | # Remember start of DLC (see below). | |
7f75d507 | 281 | elif bitnum == self.dlc_start: |
4b1813b4 | 282 | self.ss_block = self.samplenum |
702fa251 UH |
283 | |
284 | # Bits 15-18: Data length code (DLC), in number of bytes (0-8). | |
7f75d507 ST |
285 | elif bitnum == self.dlc_start + 3: |
286 | self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2) | |
b177af15 | 287 | self.putb([10, ['Data length code: %d' % self.dlc, |
3b593817 | 288 | 'DLC: %d' % self.dlc, 'DLC']]) |
ad373029 | 289 | self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8) |
b177af15 ST |
290 | if self.dlc > 8 and not self.fd: |
291 | self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) | |
702fa251 | 292 | |
4b1813b4 | 293 | # Remember all databyte bits, except the very last one. |
7f75d507 | 294 | elif bitnum in range(self.dlc_start + 4, self.last_databit): |
4b1813b4 UH |
295 | self.ss_databytebits.append(self.samplenum) |
296 | ||
702fa251 UH |
297 | # Bits 19-X: Data field (0-8 bytes, depending on DLC) |
298 | # The bits within a data byte are transferred MSB-first. | |
299 | elif bitnum == self.last_databit: | |
4b1813b4 | 300 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
ad373029 | 301 | for i in range(dlc2len(self.dlc)): |
7f75d507 | 302 | x = self.dlc_start + 4 + (8 * i) |
702fa251 | 303 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) |
4b1813b4 UH |
304 | ss = self.ss_databytebits[i * 8] |
305 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
306 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
307 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 308 | self.ss_databytebits = [] |
702fa251 UH |
309 | |
310 | elif bitnum > self.last_databit: | |
311 | return self.decode_frame_end(can_rx, bitnum) | |
312 | ||
313 | return False | |
314 | ||
315 | # Returns True if the frame ended (EOF), False otherwise. | |
316 | def decode_extended_frame(self, can_rx, bitnum): | |
317 | ||
4b1813b4 UH |
318 | # Remember start of EID (see below). |
319 | if bitnum == 14: | |
320 | self.ss_block = self.samplenum | |
655f8b16 | 321 | self.fd = False |
322 | self.dlc_start = 35 | |
4b1813b4 | 323 | |
702fa251 | 324 | # Bits 14-31: Extended identifier (EID[17..0]) |
4b1813b4 | 325 | elif bitnum == 31: |
702fa251 | 326 | self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) |
534ae912 | 327 | s = '%d (0x%x)' % (self.eid, self.eid) |
74c9bb3c | 328 | self.putb([4, ['Extended Identifier: %s' % s, |
534ae912 | 329 | 'Extended ID: %s' % s, 'Extended ID', 'EID']]) |
702fa251 UH |
330 | |
331 | self.fullid = self.id << 18 | self.eid | |
534ae912 | 332 | s = '%d (0x%x)' % (self.fullid, self.fullid) |
74c9bb3c | 333 | self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, |
534ae912 | 334 | 'Full ID', 'FID']]) |
702fa251 UH |
335 | |
336 | # Bit 12: Substitute remote request (SRR) bit | |
74c9bb3c | 337 | self.put12([9, ['Substitute remote request: %d' % self.bits[12], |
534ae912 | 338 | 'SRR: %d' % self.bits[12], 'SRR']]) |
702fa251 UH |
339 | |
340 | # Bit 32: Remote transmission request (RTR) bit | |
341 | # Data frame: dominant, remote frame: recessive | |
342 | # Remote frames do not contain a data field. | |
655f8b16 | 343 | |
344 | # Remember start of RTR (see below). | |
702fa251 | 345 | if bitnum == 32: |
6c890c08 | 346 | self.ss_bit32 = self.samplenum |
347 | self.rtr = can_rx | |
702fa251 | 348 | |
6c890c08 | 349 | if not self.fd: |
350 | rtr = 'remote' if can_rx == 1 else 'data' | |
351 | self.putx([8, ['Remote transmission request: %s frame' % rtr, | |
352 | 'RTR: %s frame' % rtr, 'RTR']]) | |
655f8b16 | 353 | |
702fa251 UH |
354 | # Bit 33: RB1 (reserved bit) |
355 | elif bitnum == 33: | |
655f8b16 | 356 | self.fd = True if can_rx else False |
655f8b16 | 357 | if self.fd: |
358 | self.dlc_start = 37 | |
3b593817 | 359 | self.putx([7, ['Flexible data format: %d' % can_rx, |
655f8b16 | 360 | 'FDF: %d' % can_rx, 'FDF']]) |
6c890c08 | 361 | self.put32([7, ['Reserved bit 1: %d' % self.rtr, |
362 | 'RB1: %d' % self.rtr, 'RB1']]) | |
655f8b16 | 363 | else: |
364 | self.putx([7, ['Reserved bit 1: %d' % can_rx, | |
365 | 'RB1: %d' % can_rx, 'RB1']]) | |
702fa251 UH |
366 | |
367 | # Bit 34: RB0 (reserved bit) | |
368 | elif bitnum == 34: | |
74c9bb3c | 369 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 370 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 | 371 | |
655f8b16 | 372 | elif bitnum == 35 and self.fd: |
373 | self.putx([7, ['Bit rate switch: %d' % can_rx, | |
374 | 'BRS: %d' % can_rx, 'BRS']]) | |
375 | ||
376 | elif bitnum == 36 and self.fd: | |
377 | self.putx([7, ['Error state indicator: %d' % can_rx, | |
378 | 'ESI: %d' % can_rx, 'ESI']]) | |
379 | ||
4b1813b4 | 380 | # Remember start of DLC (see below). |
655f8b16 | 381 | elif bitnum == self.dlc_start: |
4b1813b4 UH |
382 | self.ss_block = self.samplenum |
383 | ||
702fa251 | 384 | # Bits 35-38: Data length code (DLC), in number of bytes (0-8). |
655f8b16 | 385 | elif bitnum == self.dlc_start + 3: |
386 | self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2) | |
b177af15 ST |
387 | self.putb([10, ['Data length code: %d' % self.dlc, |
388 | 'DLC: %d' % self.dlc, 'DLC']]) | |
ad373029 | 389 | self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8) |
702fa251 | 390 | |
4b1813b4 | 391 | # Remember all databyte bits, except the very last one. |
655f8b16 | 392 | elif bitnum in range(self.dlc_start + 4, self.last_databit): |
4b1813b4 UH |
393 | self.ss_databytebits.append(self.samplenum) |
394 | ||
702fa251 UH |
395 | # Bits 39-X: Data field (0-8 bytes, depending on DLC) |
396 | # The bits within a data byte are transferred MSB-first. | |
397 | elif bitnum == self.last_databit: | |
4b1813b4 | 398 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
ad373029 | 399 | for i in range(dlc2len(self.dlc)): |
655f8b16 | 400 | x = self.dlc_start + 4 + (8 * i) |
702fa251 | 401 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) |
4b1813b4 UH |
402 | ss = self.ss_databytebits[i * 8] |
403 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
404 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
405 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 406 | self.ss_databytebits = [] |
702fa251 UH |
407 | |
408 | elif bitnum > self.last_databit: | |
409 | return self.decode_frame_end(can_rx, bitnum) | |
410 | ||
411 | return False | |
412 | ||
413 | def handle_bit(self, can_rx): | |
414 | self.rawbits.append(can_rx) | |
415 | self.bits.append(can_rx) | |
416 | ||
417 | # Get the index of the current CAN frame bit (without stuff bits). | |
418 | bitnum = len(self.bits) - 1 | |
419 | ||
8abd7aa3 ST |
420 | if self.fd and can_rx: |
421 | if bitnum == 16 and self.frame_type == 'standard' \ | |
422 | or bitnum == 35 and self.frame_type == 'extended': | |
423 | self.dom_edge_seen(force=True) | |
424 | self.set_fast_bitrate() | |
425 | ||
702fa251 UH |
426 | # If this is a stuff bit, remove it from self.bits and ignore it. |
427 | if self.is_stuff_bit(): | |
544038d9 | 428 | self.putx([15, [str(can_rx)]]) |
702fa251 UH |
429 | self.curbit += 1 # Increase self.curbit (bitnum is not affected). |
430 | return | |
544038d9 UH |
431 | else: |
432 | self.putx([17, [str(can_rx)]]) | |
702fa251 UH |
433 | |
434 | # Bit 0: Start of frame (SOF) bit | |
435 | if bitnum == 0: | |
2fac4493 UH |
436 | self.putx([1, ['Start of frame', 'SOF', 'S']]) |
437 | if can_rx != 0: | |
74c9bb3c | 438 | self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) |
702fa251 | 439 | |
4b1813b4 UH |
440 | # Remember start of ID (see below). |
441 | elif bitnum == 1: | |
442 | self.ss_block = self.samplenum | |
443 | ||
702fa251 UH |
444 | # Bits 1-11: Identifier (ID[10..0]) |
445 | # The bits ID[10..4] must NOT be all recessive. | |
446 | elif bitnum == 11: | |
447 | self.id = int(''.join(str(d) for d in self.bits[1:]), 2) | |
534ae912 | 448 | s = '%d (0x%x)' % (self.id, self.id), |
74c9bb3c | 449 | self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) |
2fac4493 UH |
450 | if (self.id & 0x7f0) == 0x7f0: |
451 | self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) | |
702fa251 UH |
452 | |
453 | # RTR or SRR bit, depending on frame type (gets handled later). | |
454 | elif bitnum == 12: | |
4b1813b4 UH |
455 | # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. |
456 | self.ss_bit12 = self.samplenum | |
702fa251 UH |
457 | |
458 | # Bit 13: Identifier extension (IDE) bit | |
459 | # Standard frame: dominant, extended frame: recessive | |
460 | elif bitnum == 13: | |
461 | ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' | |
74c9bb3c | 462 | self.putx([6, ['Identifier extension bit: %s frame' % ide, |
534ae912 | 463 | 'IDE: %s frame' % ide, 'IDE']]) |
702fa251 UH |
464 | |
465 | # Bits 14-X: Frame-type dependent, passed to the resp. handlers. | |
466 | elif bitnum >= 14: | |
467 | if self.frame_type == 'standard': | |
468 | done = self.decode_standard_frame(can_rx, bitnum) | |
469 | else: | |
470 | done = self.decode_extended_frame(can_rx, bitnum) | |
471 | ||
472 | # The handlers return True if a frame ended (EOF). | |
473 | if done: | |
474 | return | |
475 | ||
476 | # After a frame there are 3 intermission bits (recessive). | |
477 | # After these bits, the bus is considered free. | |
478 | ||
479 | self.curbit += 1 | |
480 | ||
64d87119 | 481 | def decode(self): |
21cda951 UH |
482 | if not self.samplerate: |
483 | raise SamplerateError('Cannot decode without samplerate.') | |
702fa251 | 484 | |
64d87119 | 485 | while True: |
702fa251 UH |
486 | # State machine. |
487 | if self.state == 'IDLE': | |
488 | # Wait for a dominant state (logic 0) on the bus. | |
64d87119 | 489 | (can_rx,) = self.wait({0: 'l'}) |
702fa251 | 490 | self.sof = self.samplenum |
45a50880 | 491 | self.dom_edge_seen(force = True) |
702fa251 UH |
492 | self.state = 'GET BITS' |
493 | elif self.state == 'GET BITS': | |
494 | # Wait until we're in the correct bit/sampling position. | |
64d87119 | 495 | pos = self.get_sample_point(self.curbit) |
45a50880 GS |
496 | (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) |
497 | if self.matched[1]: | |
498 | self.dom_edge_seen() | |
499 | if self.matched[0]: | |
500 | self.handle_bit(can_rx) |