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e96593c1 | 1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2016 fenugrec <fenugrec users.sourceforge.net> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # TODO: | |
22 | # - Annotations are very crude and could be improved. | |
23 | # - Annotate every nibble? Would give insight on interrupted shifts. | |
24 | # - Annotate invalid "command" nibbles while SYNC==1? | |
25 | ||
26 | import sigrokdecode as srd | |
27 | ||
28 | class Decoder(srd.Decoder): | |
29 | api_version = 2 | |
30 | id = 'aud' | |
31 | name = 'AUD' | |
32 | longname = 'Advanced User Debugger' | |
33 | desc = 'Renesas/Hitachi Advanced User Debugger (AUD) protocol.' | |
34 | license = 'gplv2+' | |
35 | inputs = ['logic'] | |
36 | outputs = ['aud'] | |
37 | channels = ( | |
38 | {'id': 'audck', 'name': 'AUDCK', 'desc': 'AUD clock'}, | |
39 | {'id': 'naudsync', 'name': 'nAUDSYNC', 'desc': 'AUD sync'}, | |
40 | {'id': 'audata3', 'name': 'AUDATA3', 'desc': 'AUD data line 3'}, | |
41 | {'id': 'audata2', 'name': 'AUDATA2', 'desc': 'AUD data line 2'}, | |
42 | {'id': 'audata1', 'name': 'AUDATA1', 'desc': 'AUD data line 1'}, | |
43 | {'id': 'audata0', 'name': 'AUDATA0', 'desc': 'AUD data line 0'}, | |
44 | ) | |
45 | annotations = ( | |
46 | ('dest', 'Destination address'), | |
47 | ) | |
48 | ||
92b7b49f | 49 | def __init__(self): |
e96593c1 | 50 | self.ncnt = 0 |
51 | self.nmax = 0 | |
52 | self.addr = 0 | |
53 | self.lastaddr = 0 | |
54 | self.samplenum = 0 | |
55 | self.oldclk = 0 | |
56 | self.ss = 0 | |
57 | ||
58 | def start(self): | |
59 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
60 | ||
61 | def putx(self, data): | |
62 | self.put(self.ss, self.samplenum, self.out_ann, data) | |
63 | ||
64 | def find_clk_edge(self, clk, sync, datapins): | |
65 | # Ignore sample if there's no edge. | |
66 | if clk == self.oldclk: | |
67 | return | |
68 | self.oldclk = clk | |
69 | # Ignore falling edges. | |
70 | if clk == 0: | |
71 | return | |
72 | ||
73 | # Reconstruct nibble. | |
74 | nib = 0 | |
75 | for i in range(4): | |
76 | nib |= datapins[3-i] << i | |
77 | ||
78 | # sync == 1: annotate if finished; update cmd. | |
79 | # TODO: Annotate idle level (nibble = 0x03 && SYNC=1). | |
80 | if sync == 1: | |
81 | if (self.ncnt == self.nmax) and (self.nmax != 0): | |
82 | # Done shifting an address: annotate. | |
83 | self.putx([0, ['0x%08X' % self.addr]]) | |
84 | self.lastaddr = self.addr | |
85 | ||
86 | self.ncnt = 0 | |
87 | self.addr = self.lastaddr | |
88 | self.ss = self.samplenum | |
89 | if nib == 0x08: | |
90 | self.nmax = 1 | |
91 | elif nib == 0x09: | |
92 | self.nmax = 2 | |
93 | elif nib == 0x0a: | |
94 | self.nmax = 4 | |
95 | elif nib == 0x0b: | |
96 | self.nmax = 8 | |
97 | else: | |
98 | # Undefined or idle. | |
99 | self.nmax = 0 | |
100 | else: | |
101 | # sync == 0, valid cmd: start or continue shifting in nibbles. | |
102 | if (self.nmax > 0): | |
103 | # Clear tgt nibble. | |
104 | self.addr &= ~(0x0F << (self.ncnt * 4)) | |
105 | # Set nibble. | |
106 | self.addr |= nib << (self.ncnt * 4) | |
107 | self.ncnt += 1 | |
108 | ||
109 | def decode(self, ss, es, data): | |
110 | for (self.samplenum, pins) in data: | |
111 | clk = pins[0] | |
112 | sync = pins[1] | |
113 | d = pins[2:] | |
114 | self.find_clk_edge(clk, sync, d) |