Created attachment 239 [details] minimal VCD dump with vector "var wire" The attached VCD file fails to open in PV-0.4.0-c6246dc (no channels are displayed). Removing theses lines $var wire 4 % AUDDATA [3:0] $end ... b1011 % ... b0000 % lets PV open the file correctly with the 2 remaining channels. Note : I think the issue is with the "b..." lines, because removing them and keeping " $var wire 4 ...." will let PV open the file, but show only 2 channels and not the vector.
Note : I just realized multi-bit vectors are explicitly not supported, so this is not really a "bug"
For your information: A proof of concept adds vector support to the sigrok VCD input module, see http://repo.or.cz/libsigrok/gsi.git vcd-vector This implementation can load the VCD file attached here, and other more complex copies. I plan to submit this work to mainline.
Is this a duplicate of bug 776? Current mainline does not support vectors in VCD input files, only single bit logic lines. For the record, log/debug output is: ... sr: [00:00.341861] input: Sending 1120 bytes to vcd module. sr: [00:00.341925] input/vcd: Section 'date', contents 'Thu May 10 22:31:28 2018'. sr: [00:00.341940] input/vcd: Section 'version', contents 'Icarus Verilog'. sr: [00:00.341951] input/vcd: Section 'timescale', contents '1s'. sr: [00:00.341965] input/vcd: Samplerate: 1 sr: [00:00.341975] input/vcd: Section 'scope', contents 'module UART_TB'. sr: [00:00.341986] input/vcd: Section 'var', contents 'wire 1 ! PIN'. sr: [00:00.342005] input/vcd: Channel 0 is 'PIN' identified by '!'. sr: [00:00.342018] input/vcd: Section 'var', contents 'wire 1 " DONE'. sr: [00:00.342029] input/vcd: Channel 1 is 'DONE' identified by '"'. sr: [00:00.342040] input/vcd: Section 'var', contents 'reg 1 # CLK'. sr: [00:00.342054] input/vcd: Channel 2 is 'CLK' identified by '#'. sr: [00:00.342066] input/vcd: Section 'var', contents 'reg 8 $ DATA [7:0]'. sr: [00:00.342076] input/vcd: Unsupported signal size: '8' sr: [00:00.342087] input/vcd: Section 'var', contents 'reg 1 % WRITE'. sr: [00:00.342097] input/vcd: Channel 3 is 'WRITE' identified by '%'. sr: [00:00.342108] input/vcd: Section 'scope', contents 'module uart'. sr: [00:00.342119] input/vcd: Section 'var', contents 'wire 1 # clk'. sr: [00:00.342129] input/vcd: Channel 4 is 'clk' identified by '#'. sr: [00:00.342140] input/vcd: Section 'var', contents 'wire 8 & data [7:0]'. sr: [00:00.342150] input/vcd: Unsupported signal size: '8' sr: [00:00.342161] input/vcd: Section 'var', contents 'wire 1 % write'. sr: [00:00.342172] input/vcd: Channel 5 is 'write' identified by '%'. sr: [00:00.342183] input/vcd: Section 'var', contents 'reg 8 ' Data_Buffer [7:0]'. sr: [00:00.342194] input/vcd: Unsupported signal size: '8' sr: [00:00.342204] input/vcd: Section 'var', contents 'reg 8 ( SM [7:0]'. sr: [00:00.342214] input/vcd: Unsupported signal size: '8' sr: [00:00.342225] input/vcd: Section 'var', contents 'reg 1 " done'. sr: [00:00.342235] input/vcd: Channel 6 is 'done' identified by '"'. sr: [00:00.342246] input/vcd: Section 'var', contents 'reg 1 ! pin'. sr: [00:00.342257] input/vcd: Channel 7 is 'pin' identified by '!'. sr: [00:00.342267] input/vcd: Section 'upscope', contents ''. sr: [00:00.342278] input/vcd: Section 'upscope', contents ''. sr: [00:00.342288] input/vcd: Section 'enddefinitions', contents ''. sr: [00:00.346042] input: Calling end() on vcd module. sr: [00:00.346093] std: unknown: Sending SR_DF_HEADER packet. sr: [00:00.346123] session: bus: Received SR_DF_HEADER packet. sr: [00:00.346177] session: bus: Received SR_DF_META packet. sr: [00:00.346301] input/vcd: Did not find channel for identifier '('. sr: [00:00.346323] input/vcd: Did not find channel for identifier '''. sr: [00:00.346339] input/vcd: Did not find channel for identifier '&'. sr: [00:00.346354] input/vcd: Did not find channel for identifier '$'. sr: [00:00.346370] input/vcd: New timestamp: 1 sr: [00:00.346390] input/vcd: New timestamp: 2 sr: [00:00.346406] input/vcd: Unexpected vector format! sr: [00:00.346426] session: bus: Received SR_DF_LOGIC packet (2 bytes, unitsize = 1). sr: [00:00.346537] std: unknown: Sending SR_DF_END packet. sr: [00:00.346558] session: bus: Received SR_DF_END packet. The "Did not find channel for identifier" and "New timestamp" messages are for information only (debug level). "Unexpected vector format" is serious.
Doh! Wanted to add comment 3 to bug 1194 instead. :(
*** Bug 1194 has been marked as a duplicate of this bug. ***
(In reply to Gerhard Sittig from comment #2) > For your information: A proof of concept adds vector support to the > sigrok VCD input module, see http://repo.or.cz/libsigrok/gsi.git vcd-vector > > This implementation can load the VCD file attached here, and other more > complex copies. I plan to submit this work to mainline. Are there any plans to get bit vector support into the mainline code? With the recent progression in open source FPGA tool chains, this would make sigrok / pulseview and the decoders invaluable for debugging and validating protocols during simulation.
Fixed in libsigrok 0ab36d2f544. Thanks for reporting.