Created attachment 419 [details] Pulse View image I started to fiddle with FPGA development and decided to use Icarus Verilog which lets you simulate and output the simulation of your verilog code to a vcd file. I am able to open this file in GTKWave with no fuss. When opening this in Pulseview I only see one transition. Being able to do this would be amazing because then then users can leverage the huge library of decoders sigrok offers while also making use of it's great GUI to this in the form of pulseview.
Created attachment 420 [details] GTK Wave image
Can you provide the VCD file? That's more important to reproduce than the screenshot is. If it's too large, ZIP it before upload.
Oh jeeze, I can't believe I forgot to upload the file itself, apologies!
Created attachment 421 [details] VCD file itself causing the issue
Is this a duplicate of bug 776? Current mainline does not support vectors in VCD input files, only single bit logic lines. For the record, log/debug output is: ... sr: [00:00.341861] input: Sending 1120 bytes to vcd module. sr: [00:00.341925] input/vcd: Section 'date', contents 'Thu May 10 22:31:28 2018'. sr: [00:00.341940] input/vcd: Section 'version', contents 'Icarus Verilog'. sr: [00:00.341951] input/vcd: Section 'timescale', contents '1s'. sr: [00:00.341965] input/vcd: Samplerate: 1 sr: [00:00.341975] input/vcd: Section 'scope', contents 'module UART_TB'. sr: [00:00.341986] input/vcd: Section 'var', contents 'wire 1 ! PIN'. sr: [00:00.342005] input/vcd: Channel 0 is 'PIN' identified by '!'. sr: [00:00.342018] input/vcd: Section 'var', contents 'wire 1 " DONE'. sr: [00:00.342029] input/vcd: Channel 1 is 'DONE' identified by '"'. sr: [00:00.342040] input/vcd: Section 'var', contents 'reg 1 # CLK'. sr: [00:00.342054] input/vcd: Channel 2 is 'CLK' identified by '#'. sr: [00:00.342066] input/vcd: Section 'var', contents 'reg 8 $ DATA [7:0]'. sr: [00:00.342076] input/vcd: Unsupported signal size: '8' sr: [00:00.342087] input/vcd: Section 'var', contents 'reg 1 % WRITE'. sr: [00:00.342097] input/vcd: Channel 3 is 'WRITE' identified by '%'. sr: [00:00.342108] input/vcd: Section 'scope', contents 'module uart'. sr: [00:00.342119] input/vcd: Section 'var', contents 'wire 1 # clk'. sr: [00:00.342129] input/vcd: Channel 4 is 'clk' identified by '#'. sr: [00:00.342140] input/vcd: Section 'var', contents 'wire 8 & data [7:0]'. sr: [00:00.342150] input/vcd: Unsupported signal size: '8' sr: [00:00.342161] input/vcd: Section 'var', contents 'wire 1 % write'. sr: [00:00.342172] input/vcd: Channel 5 is 'write' identified by '%'. sr: [00:00.342183] input/vcd: Section 'var', contents 'reg 8 ' Data_Buffer [7:0]'. sr: [00:00.342194] input/vcd: Unsupported signal size: '8' sr: [00:00.342204] input/vcd: Section 'var', contents 'reg 8 ( SM [7:0]'. sr: [00:00.342214] input/vcd: Unsupported signal size: '8' sr: [00:00.342225] input/vcd: Section 'var', contents 'reg 1 " done'. sr: [00:00.342235] input/vcd: Channel 6 is 'done' identified by '"'. sr: [00:00.342246] input/vcd: Section 'var', contents 'reg 1 ! pin'. sr: [00:00.342257] input/vcd: Channel 7 is 'pin' identified by '!'. sr: [00:00.342267] input/vcd: Section 'upscope', contents ''. sr: [00:00.342278] input/vcd: Section 'upscope', contents ''. sr: [00:00.342288] input/vcd: Section 'enddefinitions', contents ''. sr: [00:00.346042] input: Calling end() on vcd module. sr: [00:00.346093] std: unknown: Sending SR_DF_HEADER packet. sr: [00:00.346123] session: bus: Received SR_DF_HEADER packet. sr: [00:00.346177] session: bus: Received SR_DF_META packet. sr: [00:00.346301] input/vcd: Did not find channel for identifier '('. sr: [00:00.346323] input/vcd: Did not find channel for identifier '''. sr: [00:00.346339] input/vcd: Did not find channel for identifier '&'. sr: [00:00.346354] input/vcd: Did not find channel for identifier '$'. sr: [00:00.346370] input/vcd: New timestamp: 1 sr: [00:00.346390] input/vcd: New timestamp: 2 sr: [00:00.346406] input/vcd: Unexpected vector format! sr: [00:00.346426] session: bus: Received SR_DF_LOGIC packet (2 bytes, unitsize = 1). sr: [00:00.346537] std: unknown: Sending SR_DF_END packet. sr: [00:00.346558] session: bus: Received SR_DF_END packet. The "Did not find channel for identifier" and "New timestamp" messages are for information only (debug level). "Unexpected vector format" is serious.
Created attachment 422 [details] imported VCD file with vectors Yes the reported issue is that the VCD input module does not support vectors. My WIP branch can load the file, see the attached screenshot.
*** This bug has been marked as a duplicate of bug 776 ***
If you like to help improve the status of VCD import in the sigrok project, I'd suggest you join us on IRC. It would be nice to have users test the suggested changes on real world data.
Ah dang, I saw that mentioned earlier but then there was a post by Gerhard Sittig saying he had a proof of concept and was hoping to mainline it a while ago, so I thought it was mainlined by now. I would be happy to go on IRC to go back and forth with test cases, though I won't be able to sit there all day due to doing other things.
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