Difference between revisions of "Saanlima Pipistrello OLS"
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== Hardware == | == Hardware == | ||
'''Pipistrello 2.0 board''' | |||
* [http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf Xilinx Spartan-6 LX45] FPGA | |||
* [http://www.micron.com/-/media/documents/products/data%20sheet/nor%20flash/serial%20nor/n25q/n25q_128mb_3v_65nm.pdf Micron N25Q128A13ESE40G] 16MiB Flash | |||
* [http://www.micron.com/-/media/documents/products/data%20sheet/dram/mobile%20dram/low-power%20dram/lpddr/60-series/t67m_512mb_mobile_lpddr_sdram.pdf Micron MT46H32M16LFBF-5] 64MiB DRAM | |||
* [http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf FTDI FT2232H] USB interface | |||
'''Buffer wing''' | |||
* 2 x [http://www.nxp.com/documents/data_sheet/74LVC_LVCH16245A.pdf NXP 74LVC16245A] 16-bit 5V-tolerant transceivers | |||
== Protocol == | == Protocol == | ||
The protocol used is the same as the [[Openbench Logic Sniffer#Protocol|OLS protocol]], with the addition of commands for edge triggers. See the source code for details. | The protocol used is the same as the [[Openbench Logic Sniffer#Protocol|OLS protocol]], with the addition of commands for edge triggers. See the source code for details. | ||
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File:Saanlima Pipistrello buffer wing.jpg|<small>Buffer wing</small> | File:Saanlima Pipistrello buffer wing.jpg|<small>Buffer wing</small> | ||
</gallery> | </gallery> | ||
== Resources == | |||
* [http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello Saanlima Pipistrello] | |||
* [http://saanlima.com/forum/viewforum.php?f=3&sid=d8f2eaf446327493dd36a7132da1cc52 Pipistrello support forum] | |||
Revision as of 01:03, 25 August 2014
 | |
| Status | supported |
|---|---|
| Source code | pipistrello-ols |
| Channels | 32 |
| Samplerate | 0-100MHz |
| Samplerate (state) | — |
| Triggers | value, rising/falling edge |
| Min/max voltage | 0V — 5V |
| Memory | 64MiB |
| Compression | yes |
| Website | pipistrello.saanlima.com |
The Saanlima Pipistrello is an FPGA development board with many on-board peripherals and pin headers compatible with the Papilio series of boards. It has USB connectivity to a host PC, and, by adding the Saanlima buffer wing, can be used as a replacement for the Openbench Logic Sniffer (OLS).
The FPGA firmware for the OLS has been ported for the Pipistrello, and can thus use the full 64MiB memory to store samples. It also has triggers on rising/falling edges as an extra feature.
All design source for the Pipistrello, including schematics and Eagle board files, are available under the CC-BY-SA 4.0 license.
See Saanlima Pipistrello OLS/Info for more details (such as lsusb -vvv output) about the device.
Hardware
Pipistrello 2.0 board
- Xilinx Spartan-6 LX45 FPGA
- Micron N25Q128A13ESE40G 16MiB Flash
- Micron MT46H32M16LFBF-5 64MiB DRAM
- FTDI FT2232H USB interface
Buffer wing
- 2 x NXP 74LVC16245A 16-bit 5V-tolerant transceivers
Protocol
The protocol used is the same as the OLS protocol, with the addition of commands for edge triggers. See the source code for details.
Photos
Pipistrello board
Buffer wing
