2 * This file is part of the sigrok-firmware-fx2lafw project.
4 * Copyright (C) 2009 Ubixum, Inc.
5 * Copyright (C) 2015 Jochen Hoenicke
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <fx2macros.h>
24 #include <autovector.h>
28 /* Change to support as many interfaces as you need. */
29 static BYTE altiface = 0;
31 static volatile __bit dosud = FALSE;
32 static volatile __bit dosuspend = FALSE;
34 extern __code BYTE highspd_dscr;
35 extern __code BYTE fullspd_dscr;
37 void resume_isr(void) __interrupt RESUME_ISR
42 void sudav_isr(void) __interrupt SUDAV_ISR
48 void usbreset_isr(void) __interrupt USBRESET_ISR
50 handle_hispeed(FALSE);
54 void hispeed_isr(void) __interrupt HISPEED_ISR
60 void suspend_isr(void) __interrupt SUSPEND_ISR
66 void timer2_isr(void) __interrupt TF2_ISR
68 /* Toggle the 1kHz pin, only accurate up to ca 8MHz */
74 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage (attentuator). The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.
76 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
77 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
78 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
79 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
80 * PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
81 * PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
83 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
84 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
85 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
86 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
87 * PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
88 * PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
90 static BOOL set_voltage(BYTE channel, BYTE val)
92 BYTE bits_C, bit_E, mask_C, mask_E;
117 } else if (channel == 1) {
147 IOC = (IOC & ~mask_C) | (bits_C & mask_C);
148 IOE = (IOE & ~mask_E) | (bit_E & mask_E);
153 static BOOL set_numchannels(BYTE numchannels)
155 if (numchannels == 1 || numchannels == 2) {
156 BYTE fifocfg = 7 + numchannels;
157 EP2FIFOCFG = fifocfg;
158 EP6FIFOCFG = fifocfg;
165 static void clear_fifo(void)
178 static void stop_sampling(void)
182 INPKTEND = (altiface == 0) ? 6 : 2;
185 static void start_sampling(void)
191 for (i = 0; i < 1000; i++);
193 while (!(GPIFTRIG & 0x80))
200 GPIFTRIG = (altiface == 0) ? 6 : 4;
204 static void select_interface(BYTE alt)
206 const BYTE *pPacketSize = \
207 ((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
208 + (9 + (16 * alt) + 9 + 4);
217 EP6AUTOINLENL = pPacketSize[0];
218 EP6AUTOINLENH = pPacketSize[1];
224 EP2AUTOINLENL = pPacketSize[0];
225 EP2AUTOINLENH = pPacketSize[1] & 0x7;
226 EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
230 static const struct samplerate_info {
239 { 48, 0x80, 0, 3, 0, 0x00, 0xea },
240 { 30, 0x80, 0, 3, 0, 0x00, 0xaa },
241 { 24, 1, 0, 2, 1, 0x40, 0xea },
242 { 16, 1, 1, 2, 0, 0x40, 0xea },
243 { 12, 2, 1, 2, 0, 0x40, 0xea },
244 { 8, 3, 2, 2, 0, 0x40, 0xea },
245 { 4, 6, 5, 2, 0, 0x40, 0xea },
246 { 2, 12, 11, 2, 0, 0x40, 0xea },
247 { 1, 24, 23, 2, 0, 0x40, 0xea },
248 { 50, 48, 47, 2, 0, 0x40, 0xea },
249 { 20, 120, 119, 2, 0, 0x40, 0xea },
250 { 10, 240, 239, 2, 0, 0x40, 0xea },
253 static BOOL set_samplerate(BYTE rate)
257 while (samplerates[i].rate != rate) {
259 if (i == sizeof(samplerates) / sizeof(samplerates[0]))
263 IFCONFIG = samplerates[i].ifcfg;
270 * The program for low-speed, e.g. 1 MHz, is:
271 * wait 24, CTL2=0, FIFO
275 * The program for 24 MHz is:
276 * wait 1, CTL2=0, FIFO
279 * The program for 30/48 MHz is:
280 * jump 0, CTL2=Z, FIFO, LOOP
283 EXTAUTODAT2 = samplerates[i].wait0;
284 EXTAUTODAT2 = samplerates[i].wait1;
292 EXTAUTODAT2 = samplerates[i].opc0;
293 EXTAUTODAT2 = samplerates[i].opc1;
301 EXTAUTODAT2 = samplerates[i].out0;
319 for (i = 0; i < 96; i++)
325 /* Set *alt_ifc to the current alt interface for ifc. */
326 BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
336 * Return TRUE if you set the interface requested.
338 * Note: This function should reconfigure and reset the endpoints
339 * according to the interface descriptors you provided.
341 BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
344 select_interface(alt_ifc);
349 BYTE handle_get_configuration(void)
351 /* We only support configuration 0. */
355 BOOL handle_set_configuration(BYTE cfg)
357 /* We only support configuration 0. */
363 BOOL handle_vendorcommand(BYTE cmd)
367 /* Clear EP0BCH/L for each valid command. */
368 if (cmd >= 0xe0 && cmd <= 0xe4) {
371 while (EP0CS & bmEPBUSY);
377 set_voltage(cmd - 0xe0, EP0BUF[0]);
380 set_samplerate(EP0BUF[0]);
387 set_numchannels(EP0BUF[0]);
391 return FALSE; /* Not handled by handlers. */
394 static void init(void)
399 /* In idle mode tristate all outputs. */
403 GPIFREADYSTAT = 0x00;
414 static void main(void)
421 /* Set up interrupts. */
430 /* Global (8051) interrupt enable. */
434 RCAP2L = -1000 & 0xff;
435 RCAP2H = (-1000 >> 8) & 0xff;
460 /* Make sure ext wakeups are cleared. */
461 WAKEUPCS |= bmWU|bmWU2;
473 } while (!remote_wakeup_allowed && REMOTE_WAKEUP());
475 /* Resume (TRM 6.4). */
476 if (REMOTE_WAKEUP()) {
478 USBCS |= bmSIGRESUME;
480 USBCS &= ~bmSIGRESUME;