2 * This file is part of the sigrok-firmware-fx2lafw project.
4 * Copyright (C) 2009 Ubixum, Inc.
5 * Copyright (C) 2015 Jochen Hoenicke
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include <fx2macros.h>
23 #include <autovector.h>
27 #define SET_ANALOG_MODE()
29 /* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
30 #define TOGGLE_CALIBRATION_PIN() PA7 = !PA7
32 #define LED_CLEAR() PC0 = 1; PC1 = 1;
33 #define LED_GREEN() PC0 = 1; PC1 = 0;
34 #define LED_RED() PC0 = 0; PC1 = 1;
36 /* CTLx pin index (IFCLK, ADC clock input). */
39 #define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
40 #define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */
42 /* Change to support as many interfaces as you need. */
43 static BYTE altiface = 0;
45 static volatile WORD ledcounter = 0;
47 static volatile __bit dosud = FALSE;
48 static volatile __bit dosuspend = FALSE;
50 extern __code BYTE highspd_dscr;
51 extern __code BYTE fullspd_dscr;
53 void resume_isr(void) __interrupt RESUME_ISR
58 void sudav_isr(void) __interrupt SUDAV_ISR
64 void usbreset_isr(void) __interrupt USBRESET_ISR
66 handle_hispeed(FALSE);
70 void hispeed_isr(void) __interrupt HISPEED_ISR
76 void suspend_isr(void) __interrupt SUSPEND_ISR
82 void timer2_isr(void) __interrupt TF2_ISR
84 TOGGLE_CALIBRATION_PIN();
86 if (ledcounter && (--ledcounter == 0))
93 * This sets three bits for each channel, one channel at a time.
94 * For channel 0 we want to set bits 5, 6 & 7
95 * For channel 1 we want to set bits 2, 3 & 4
97 * We convert the input values that are strange due to original
98 * firmware code into the value of the three bits as follows:
106 * The third bit is always zero since there are only four outputs connected
107 * in the serial selector chip.
109 * The multiplication of the converted value by 0x24 sets the relevant bits in
110 * both channels and then we mask it out to only affect the channel currently
113 static BOOL set_voltage(BYTE channel, BYTE val)
134 mask = (channel) ? 0xe0 : 0x1c;
135 IOC = (IOC & ~mask) | (bits & mask);
140 static BOOL set_numchannels(BYTE numchannels)
142 if (numchannels == 1 || numchannels == 2) {
143 BYTE fifocfg = 7 + numchannels;
144 EP2FIFOCFG = fifocfg;
145 EP6FIFOCFG = fifocfg;
152 static void clear_fifo(void)
165 static void stop_sampling(void)
169 INPKTEND = (altiface == 0) ? 6 : 2;
172 static void start_sampling(void)
180 for (i = 0; i < 1000; i++);
182 while (!(GPIFTRIG & 0x80))
189 GPIFTRIG = (altiface == 0) ? 6 : 4;
191 /* Set green LED, don't clear LED afterwards (ledcounter = 0). */
196 static void select_interface(BYTE alt)
198 const BYTE *pPacketSize = \
199 ((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
200 + (9 + (16 * alt) + 9 + 4);
209 EP6AUTOINLENL = pPacketSize[0];
210 EP6AUTOINLENH = pPacketSize[1];
216 EP2AUTOINLENL = pPacketSize[0];
217 EP2AUTOINLENH = pPacketSize[1] & 0x7;
218 EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
222 static const struct samplerate_info {
231 { 48, 0x80, 0, 3, 0, 0x00, 0xea },
232 { 30, 0x80, 0, 3, 0, 0x00, 0xaa },
233 { 24, 1, 0, 2, 1, OUT0, 0xca },
234 { 16, 1, 1, 2, 0, OUT0, 0xca },
235 { 12, 2, 1, 2, 0, OUT0, 0xca },
236 { 8, 3, 2, 2, 0, OUT0, 0xca },
237 { 4, 6, 5, 2, 0, OUT0, 0xca },
238 { 2, 12, 11, 2, 0, OUT0, 0xca },
239 { 1, 24, 23, 2, 0, OUT0, 0xca },
240 { 50, 48, 47, 2, 0, OUT0, 0xca },
241 { 20, 120, 119, 2, 0, OUT0, 0xca },
242 { 10, 240, 239, 2, 0, OUT0, 0xca },
245 static BOOL set_samplerate(BYTE rate)
249 while (samplerates[i].rate != rate) {
251 if (i == sizeof(samplerates) / sizeof(samplerates[0]))
255 IFCONFIG = samplerates[i].ifcfg;
258 AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
262 * The program for low-speed, e.g. 1 MHz, is:
263 * wait 24, CTLx=0, FIFO
267 * The program for 24 MHz is:
268 * wait 1, CTLx=0, FIFO
271 * The program for 30/48 MHz is:
272 * jump 0, CTLx=Z, FIFO, LOOP
274 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
277 /* LENGTH / BRANCH 0-7 */
278 EXTAUTODAT2 = samplerates[i].wait0;
279 EXTAUTODAT2 = samplerates[i].wait1;
288 EXTAUTODAT2 = samplerates[i].opc0;
289 EXTAUTODAT2 = samplerates[i].opc1;
290 EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
298 EXTAUTODAT2 = samplerates[i].out0;
299 EXTAUTODAT2 = OE_CTL;
300 EXTAUTODAT2 = OE_CTL;
307 /* LOGIC FUNCTION 0-7 */
317 for (i = 0; i < 96; i++)
323 /* Set *alt_ifc to the current alt interface for ifc. */
324 BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
334 * Return TRUE if you set the interface requested.
336 * Note: This function should reconfigure and reset the endpoints
337 * according to the interface descriptors you provided.
339 BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
342 select_interface(alt_ifc);
347 BYTE handle_get_configuration(void)
349 /* We only support configuration 0. */
353 BOOL handle_set_configuration(BYTE cfg)
355 /* We only support configuration 0. */
361 BOOL handle_vendorcommand(BYTE cmd)
365 /* Set red LED, clear after timeout. */
369 /* Clear EP0BCH/L for each valid command. */
370 if (cmd >= 0xe0 && cmd <= 0xe4) {
373 while (EP0CS & bmEPBUSY);
379 set_voltage(cmd - 0xe0, EP0BUF[0]);
382 set_samplerate(EP0BUF[0]);
389 set_numchannels(EP0BUF[0]);
393 return FALSE; /* Not handled by handlers. */
396 static void init(void)
403 /* In idle mode tristate all outputs. */
404 GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
405 GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
407 GPIFREADYSTAT = 0x00;
418 static void main(void)
425 /* Set up interrupts. */
434 /* Global (8051) interrupt enable. */
438 RCAP2L = -500 & 0xff;
439 RCAP2H = (-500 & 0xff00) >> 8;
462 /* Make sure ext wakeups are cleared. */
463 WAKEUPCS |= bmWU | bmWU2;
475 } while (!remote_wakeup_allowed && REMOTE_WAKEUP());
477 /* Resume (TRM 6.4). */
478 if (REMOTE_WAKEUP()) {
480 USBCS |= bmSIGRESUME;
482 USBCS &= ~bmSIGRESUME;