2 * This file is part of the sigrok-firmware-fx2lafw project.
4 * Copyright (C) 2009 Ubixum, Inc.
5 * Copyright (C) 2015 Jochen Hoenicke
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <fx2macros.h>
24 #include <autovector.h>
28 /* Change to support as many interfaces as you need. */
31 volatile WORD ledcounter = 0;
33 volatile __bit dosud = FALSE;
34 volatile __bit dosuspend = FALSE;
36 extern __code BYTE highspd_dscr;
37 extern __code BYTE fullspd_dscr;
39 extern void main_init();
48 /* Set up interrupts. */
57 /* Global (8051) interrupt enable. */
62 RCAP2H = (-500 >> 8) & 0xff;
83 /* Make sure ext wakeups are cleared. */
84 WAKEUPCS |= bmWU|bmWU2;
96 } while (!remote_wakeup_allowed && REMOTE_WAKEUP());
98 /* Resume (TRM 6.4). */
99 if (REMOTE_WAKEUP()) {
101 USBCS |= bmSIGRESUME;
103 USBCS &= ~bmSIGRESUME;
109 void resume_isr(void) __interrupt RESUME_ISR
114 void sudav_isr(void) __interrupt SUDAV_ISR
120 void usbreset_isr(void) __interrupt USBRESET_ISR
122 handle_hispeed(FALSE);
126 void hispeed_isr(void) __interrupt HISPEED_ISR
128 handle_hispeed(TRUE);
132 void suspend_isr(void) __interrupt SUSPEND_ISR
138 void timer2_isr(void) __interrupt TF2_ISR
142 if (--ledcounter == 0) {
152 * This sets three bits for each channel, one channel at a time.
153 * For channel 0 we want to set bits 5, 6 & 7
154 * For channel 1 we want to set bits 2, 3 & 4
156 * We convert the input values that are strange due to original
157 * firmware code into the value of the three bits as follows:
165 * The third bit is always zero since there are only four outputs connected
166 * in the serial selector chip.
168 * The multiplication of the converted value by 0x24 sets the relevant bits in
169 * both channels and then we mask it out to only affect the channel currently
172 BOOL set_voltage(BYTE channel, BYTE val)
193 mask = (channel) ? 0xe0 : 0x1c;
194 IOC = (IOC & ~mask) | (bits & mask);
199 BOOL set_numchannels(BYTE numchannels)
201 if (numchannels == 1 || numchannels == 2) {
202 BYTE fifocfg = 7 + numchannels;
203 EP2FIFOCFG = fifocfg;
204 EP6FIFOCFG = fifocfg;
211 void clear_fifo(void)
224 void stop_sampling(void)
228 INPKTEND = (altiface == 0) ? 6 : 2;
231 void start_sampling(void)
237 for (i = 0; i < 1000; i++);
239 while (!(GPIFTRIG & 0x80))
246 GPIFTRIG = (altiface == 0) ? 6 : 4;
248 /* Set green LED, don't clear LED. */
254 void select_interface(BYTE alt)
256 const BYTE *pPacketSize = \
257 (USBCS & bmHSM ? &highspd_dscr : &fullspd_dscr)
258 + (9 + (16 * alt) + 9 + 4);
267 EP6AUTOINLENL = pPacketSize[0];
268 EP6AUTOINLENH = pPacketSize[1];
274 EP2AUTOINLENL = pPacketSize[0];
275 EP2AUTOINLENH = pPacketSize[1] & 0x7;
276 EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
280 const struct samplerate_info {
289 { 48,0x80, 0, 3, 0, 0x00, 0xea },
290 { 30,0x80, 0, 3, 0, 0x00, 0xaa },
291 { 24, 1, 0, 2, 1, 0x40, 0xca },
292 { 16, 1, 1, 2, 0, 0x40, 0xca },
293 { 12, 2, 1, 2, 0, 0x40, 0xca },
294 { 8, 3, 2, 2, 0, 0x40, 0xca },
295 { 4, 6, 5, 2, 0, 0x40, 0xca },
296 { 2, 12, 11, 2, 0, 0x40, 0xca },
297 { 1, 24, 23, 2, 0, 0x40, 0xca },
298 { 50, 48, 47, 2, 0, 0x40, 0xca },
299 { 20, 120, 119, 2, 0, 0x40, 0xca },
300 { 10, 240, 239, 2, 0, 0x40, 0xca },
303 BOOL set_samplerate(BYTE rate)
307 while (samplerates[i].rate != rate) {
309 if (i == sizeof(samplerates) / sizeof(samplerates[0]))
313 IFCONFIG = samplerates[i].ifcfg;
320 * The program for low-speed, e.g. 1 MHz, is:
321 * wait 24, CTL2=0, FIFO
325 * The program for 24 MHz is:
326 * wait 1, CTL2=0, FIFO
329 * The program for 30/48 MHz is:
330 * jump 0, CTL2=Z, FIFO, LOOP
333 EXTAUTODAT2 = samplerates[i].wait0;
334 EXTAUTODAT2 = samplerates[i].wait1;
342 EXTAUTODAT2 = samplerates[i].opc0;
343 EXTAUTODAT2 = samplerates[i].opc1;
351 EXTAUTODAT2 = samplerates[i].out0;
369 for (i = 0; i < 96; i++)
375 /* Set *alt_ifc to the current alt interface for ifc. */
376 BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
386 * Return TRUE if you set the interface requested.
388 * Note: This function should reconfigure and reset the endpoints
389 * according to the interface descriptors you provided.
391 BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
394 select_interface(alt_ifc);
399 BYTE handle_get_configuration(void)
401 /* We only support configuration 0. */
405 BOOL handle_set_configuration(BYTE cfg)
407 /* We only support configuration 0. */
413 BOOL handle_vendorcommand(BYTE cmd)
427 while (EP0CS & bmEPBUSY);
428 set_voltage(cmd - 0xe0, EP0BUF[0]);
433 while (EP0CS & bmEPBUSY);
434 set_samplerate(EP0BUF[0]);
439 while (EP0CS & bmEPBUSY);
446 while (EP0CS & bmEPBUSY);
447 set_numchannels(EP0BUF[0]);
451 return FALSE; /* Not handled by handlers. */
459 /* In idle mode tristate all outputs. */
463 GPIFREADYSTAT = 0x00;