2 * This file is part of the fx2lafw project.
4 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
24 * It is written in C, using fx2lib as helper library, and sdcc as compiler.
25 * The code is licensed under the terms of the GNU GPL, version 2 or later.
29 * - We use the FX2 in GPIF mode to sample the data (asynchronously).
30 * - We use the internal 48MHz clock for GPIF.
31 * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7.
32 * Support for 16 channels is not yet included, but might be added later.
33 * - Endpoint 2 is used for data transfers from FX2 to host.
34 * - The endpoint is quad-buffered.
38 * - See http://sigrok.org/wiki/Fx2lafw
42 #include <fx2macros.h>
44 #include <autovector.h>
49 /* Protocol commands */
50 #define CMD_SET_SAMPLERATE 0xb0
51 #define CMD_START 0xb1
53 #define CMD_GET_FW_VERSION 0xb3
56 #define SYNCDELAY() SYNCDELAY4
61 /* GPIF terminology: DP = decision point, NDP = non-decision-point */
66 * See section "10.3.4 State Instructions" in the TRM for details.
68 static const BYTE wavedata[128] = {
72 * This is the basic algorithm implemented in our GPIF state machine:
74 * State 0: NDP: Sample the FIFO data bus.
75 * State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
76 * end the current waveform. Otherwise, go to state 0 again,
77 * i.e., sample data until EP2 is full.
85 /* S0-S6: LENGTH/BRANCH */
87 * For NDPs (LENGTH): Number of IFCLK cycles to stay in this state.
88 * For DPs (BRANCH): [7] ReExec, [5:3]: BRANCHON1, [2:0]: BRANCHON0.
90 * 0x01: Stay one IFCLK cycle in this state.
91 * 0x38: No Re-execution, BRANCHON1 = state 7, BRANCHON0 = state 0.
93 // 0x01, 0x38, 0x01, 0x01, 0x01, 0x01, 0x01,
94 // FIXME: For now just loop over the "sample data" state forever.
95 0x01, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,
96 /* TRM says "reserved", but GPIF designer always puts a 0x07 here. */
101 * 0x02: NDP, sample the FIFO data bus.
102 * 0x01: DP, don't sample the FIFO data bus.
104 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
109 /* Unused, we don't output anything, we only sample the pins. */
110 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
114 /* S0-S6: LOGIC FUNCTION (not used for NDPs) */
116 * 0x36: LFUNC = "A AND B", A = FIFO flag, B = FIFO flag.
117 * The FIFO flag (FF == full flag, in our case) is configured via
120 * So: If the EP2 FIFO is full and the EP2 FIFO is full, go to
121 * the state specified by BRANCHON1 (state 7), otherwise BRANCHON0
122 * (state 0). See the LENGTH/BRANCH value above for details.
124 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00,
125 /* TRM says "reserved", but GPIF designer always puts a 0x3f here. */
128 /* TODO: Must unused waveforms be "valid"? */
130 /* Waveform 1 (unused): */
131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
136 /* Waveform 2 (unused): */
137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
140 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
142 /* Waveform 3 (unused): */
143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
144 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
149 static void gpif_setup_registers(void)
151 /* TODO. Value probably irrelevant, as we don't use RDY* signals? */
155 * Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
156 * TODO: Probably irrelevant, as we don't use CTL0-CTL5?
160 /* When GPIF is idle, tri-state the data bus. */
161 /* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
162 GPIFIDLECS = (1 << 0);
164 /* When GPIF is idle, set CTL0-CTL5 to 0. */
168 * Map index 0 in wavedata[] to FIFORD. The rest is assigned too,
169 * but not used by us.
171 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
172 * [3:2] = FIFOWR index, [1:0] = FIFORD index
174 GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0);
176 /* Contains RDY* pin values. Read-only according to TRM. */
180 static void gpif_write_waveforms(void)
185 * Write the four waveforms into the respective WAVEDATA register
186 * locations (0xe400 - 0xe47f) using the FX2's autopointer feature.
188 AUTOPTRSETUP = 0x07; /* Increment autopointers 1 & 2. */
189 AUTOPTRH1 = MSB((WORD)wavedata); /* Source is the 'wavedata' array. */
190 AUTOPTRL1 = LSB((WORD)wavedata);
191 AUTOPTRH2 = 0xe4; /* Dest is WAVEDATA (0xe400). */
193 for (i = 0; i < 128; i++)
194 EXTAUTODAT2 = EXTAUTODAT1;
197 static void gpif_init_addr_pins(void)
200 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
201 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
202 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
204 PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
205 OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
206 PORTECFG |= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
207 OEE |= 0x80; /* Configure PORTE[7] as output. */
209 GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
211 GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
214 static void gpif_init_flowstates(void)
216 /* Clear all flowstate registers, we don't use this functionality. */
227 static void gpif_init_la(void)
230 * Setup the FX2 in GPIF master mode, using the internal clock
231 * (non-inverted) at 48MHz, and using async sampling.
235 /* Abort currently executing GPIF waveform (if any). */
238 /* Setup the GPIF registers. */
239 gpif_setup_registers();
241 /* Write the four GPIF waveforms into the WAVEDATA register. */
242 gpif_write_waveforms();
244 /* Initialize GPIF address pins, output initial values. */
245 gpif_init_addr_pins();
247 /* Initialize flowstate registers (not used by us). */
248 gpif_init_flowstates();
251 static void setup_endpoints(void)
253 /* Setup EP2 (IN). */
254 EP2CFG = (1 << 7) | /* EP is valid/activated */
255 (1 << 6) | /* EP direction: IN */
256 (1 << 5) | (0 << 4) | /* EP Type: bulk */
257 (0 << 3) | /* EP buffer size: 512 */
258 (0 << 2) | /* Reserved. */
259 (0 << 1) | (0 << 0); /* EP buffering: quad buffering */
262 /* Setup EP6 (IN) in the debug build. */
264 EP6CFG = (1 << 7) | /* EP is valid/activated */
265 (1 << 6) | /* EP direction: IN */
266 (1 << 5) | (0 << 4) | /* EP Type: bulk */
267 (0 << 3) | /* EP buffer size: 512 */
268 (0 << 2) | /* Reserved */
269 (1 << 1) | (0 << 0); /* EP buffering: double buffering */
275 /* Disable all other EPs (EP4 and EP8). */
276 EP1INCFG &= ~bmVALID;
278 EP1OUTCFG &= ~bmVALID;
285 /* EP2: Reset the FIFOs. */
286 /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
289 /* Reset the FIFOs of EP6 when in debug mode. */
293 /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
294 EP2FIFOCFG = bmAUTOIN | ~bmWORDWIDE;
297 /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
298 EP2AUTOINLENH = 0x02;
300 EP2AUTOINLENL = 0x00;
303 /* EP2: Set the GPIF flag to 'full'. */
304 EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
308 BOOL handle_vendorcommand(BYTE cmd)
310 /* Protocol implementation */
313 case CMD_SET_SAMPLERATE:
324 case CMD_GET_FW_VERSION:
328 /* Unimplemented command. */
335 BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
337 /* We only support interface 0, alternate interface 0. */
345 BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
347 /* We only support interface 0, alternate interface 0. */
348 if (ifc != 0 || alt_ifc != 0)
351 /* Perform procedure from TRM, section 2.3.7: */
355 /* (2) Reset data toggles of the EPs in the interface. */
356 /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
360 /* (3) Restore EPs to their default conditions. */
361 /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
367 /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
372 BYTE handle_get_configuration(void)
374 /* We only support configuration 1. */
378 BOOL handle_set_configuration(BYTE cfg)
380 /* We only support configuration 1. */
381 return (cfg == 1) ? TRUE : FALSE;
384 void sudav_isr(void) interrupt SUDAV_ISR
390 void sof_isr(void) interrupt SOF_ISR using 1
395 void usbreset_isr(void) interrupt USBRESET_ISR
397 handle_hispeed(FALSE);
401 void hispeed_isr(void) interrupt HISPEED_ISR
403 handle_hispeed(TRUE);
407 void fx2lafw_init(void)
409 /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
410 REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;
421 /* TODO: Does the order of the following lines matter? */
427 /* Global (8051) interrupt enable. */
430 /* Setup the endpoints. */
433 /* Put the FX2 into GPIF master mode and setup the GPIF. */
436 /* Perform the initial GPIF read. */
437 gpif_fifo_read(GPIF_EP2);
440 void fx2lafw_run(void)